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JP2006032541A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006032541A
JP2006032541A JP2004207205A JP2004207205A JP2006032541A JP 2006032541 A JP2006032541 A JP 2006032541A JP 2004207205 A JP2004207205 A JP 2004207205A JP 2004207205 A JP2004207205 A JP 2004207205A JP 2006032541 A JP2006032541 A JP 2006032541A
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film
gate electrode
nitride film
semiconductor device
oxide film
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JP2006032541A5 (en
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Jun Sumino
潤 角野
Satoru Shimizu
悟 清水
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Renesas Technology Corp
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Renesas Technology Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device capable of preventing the side of a gate electrode from being exposed due to the etching of an oxide film for constituting a sidewall at the time of contact etching, in the semiconductor device with the sidewall composed of the oxide film and a multilayer nitride film. <P>SOLUTION: The semiconductor device comprises a gate insulating layer formed on the semiconductor substrate; a gate electrode formed on the gate insulating layer; a first nitride film formed on the gate electrode; and sidewalls each composed of the first oxide film formed at the side of the gate electrode and the first nitride film in order, a second nitride film, a second oxide film, and a third nitride. The upper outer diameter of the first nitride film is smaller than that of a lower outer diameter. The side of the gate electrode of the first oxide film is partially covered with the second nitride film when viewed from the upper surface. The side of the gate electrode of the second oxide film is partially covered with the third nitride film when viewed from the upper surface. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多層膜よりなるサイドウォールを有する半導体装置に関するものである。   The present invention relates to a semiconductor device having a sidewall made of a multilayer film.

近年、トランジスタやメモリセル等の半導体装置において、微細化に伴い、ゲート電極とコンタクトの間隔を狭くする傾向にある。このため、ゲート電極上にコンタクトが乗り上げるＳＡＣ（Self Aligned Contact）構造が用いられる。このＳＡＣ構造では、酸化膜からなる層間絶縁膜との選択比を確保するため、ゲート上のハードカバーやサイドウォールに窒化膜を用いる。   In recent years, in a semiconductor device such as a transistor or a memory cell, the distance between the gate electrode and the contact tends to be narrowed with miniaturization. For this reason, a SAC (Self Aligned Contact) structure in which a contact is placed on the gate electrode is used. In this SAC structure, a nitride film is used for the hard cover and the sidewall on the gate in order to ensure a selection ratio with the interlayer insulating film made of an oxide film.

また、フラッシュメモリでは、ゲート−コンタクト間に約２０Ｖの高い電圧が印加されるため、耐圧向上が課題となっている。特に、サイドウォールとして窒化膜のみを用いた場合、ゲートを負バイアスにすると、ゲート近傍の窒化膜にホールが蓄積され、実効的な耐圧が低下するという問題があった。   In addition, in a flash memory, since a high voltage of about 20 V is applied between the gate and the contact, improvement in breakdown voltage is a problem. In particular, when only the nitride film is used as the sidewall, there is a problem that if the gate is negatively biased, holes are accumulated in the nitride film in the vicinity of the gate and the effective breakdown voltage is reduced.

そこで、ゲートとサイドウォールの窒化膜の間にＯＮＯ膜を設けた半導体装置が提案されている（例えば、特許文献１参照）。この従来の半導体装置の断面図を図９に示す。半導体基板１１上にゲート絶縁膜１２が形成されている。そして、ゲート絶縁膜１２上に、ゲート電極として、ポリシリコン膜１３、ＯＮＯ膜１４、ポリシリコン膜１５、ＷＳｉ膜１６が形成されている。また、ゲート電極上にＳｉＮ膜１７が形成され、ゲート電極及びＳｉＮ膜１７の側壁には、順番に形成されたＳｉＯ２膜１８、ＳｉＮ膜１９、ＳｉＯ２膜２０及びＳｉＮ膜２１からなるサイドウォールが形成されている。 Therefore, a semiconductor device in which an ONO film is provided between a gate and a sidewall nitride film has been proposed (see, for example, Patent Document 1). A cross-sectional view of this conventional semiconductor device is shown in FIG. A gate insulating film 12 is formed on the semiconductor substrate 11. On the gate insulating film 12, a polysilicon film 13, an ONO film 14, a polysilicon film 15, and a WSi film 16 are formed as gate electrodes. Further, a SiN film 17 is formed on the gate electrode, and sidewalls made of the SiO 2 film 18, the SiN film 19, the SiO 2 film 20, and the SiN film 21 formed in order on the side walls of the gate electrode and the SiN film 17. Is formed.

従来の半導体装置を用いてコンタクトエッチングを行った状態を図１０に示す。半導体装置を覆うようにＳｉＯ２からなる層間絶縁膜２２を形成し、この層間絶縁膜２２をフォトリソグラフィ等により異方性エッチングする。この際、エッチングの選択性を持たせることでＳｉＮ膜２１はエッチングされないようにする。これにより、ゲート電極上にコンタクトが乗り上げたＳＡＣ構造を形成することができる。 FIG. 10 shows a state where contact etching is performed using a conventional semiconductor device. An interlayer insulating film 22 made of SiO 2 is formed so as to cover the semiconductor device, and this interlayer insulating film 22 is anisotropically etched by photolithography or the like. At this time, the SiN film 21 is prevented from being etched by providing etching selectivity. Thereby, it is possible to form a SAC structure in which a contact rides on the gate electrode.

特開２００２−２５２２３２号公報JP 2002-252232 A

しかし、従来の半導体装置では、サイドウォールを構成する酸化膜と窒化膜の多層膜が垂直に形成されているため、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされて、ゲート電極の側面が露出するという問題があった。   However, in the conventional semiconductor device, since the multilayer film of the oxide film and the nitride film constituting the sidewall is formed vertically, the oxide film constituting the sidewall is etched at the time of contact etching, and the gate electrode There was a problem that the side was exposed.

本発明は、上述のような課題を解決するためになされたもので、その目的は、酸化膜と窒化膜の多層膜よりなるサイドウォールを有する半導体装置において、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされてゲート電極の側面が露出するのを防ぐことができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a contact of an oxide film constituting a sidewall in a semiconductor device having a sidewall made of a multilayer film of an oxide film and a nitride film. A semiconductor device capable of preventing the side surface of the gate electrode from being exposed by etching during etching is obtained.

本発明に係る半導体装置は、半導体基板上に形成されたゲート絶縁膜と、ゲート絶縁膜上に形成されたゲート電極と、ゲート電極上に形成された第１の窒化膜と、ゲート電極及び第１の窒化膜の側面に順番に形成された第１の酸化膜、第２の窒化膜、第２の酸化膜及び第３の窒化膜からなるサイドウォールとを有し、第１の窒化膜は、上部の外径が下部の外径よりも小さく、第１の酸化膜のゲート電極の側面にある部分は、上面から見て第２の窒化膜で覆われ、第２の酸化膜のゲート電極の側面にある部分は、上面から見て第３の窒化膜で覆われている。本発明のその他の特徴は以下に明らかにする。   A semiconductor device according to the present invention includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, a first nitride film formed on the gate electrode, a gate electrode, The first nitride film has a first oxide film, a second nitride film, a second oxide film, and a sidewall made of a third nitride film sequentially formed on the side surface of the first nitride film. The outer diameter of the upper portion is smaller than the outer diameter of the lower portion, and the portion on the side surface of the gate electrode of the first oxide film is covered with the second nitride film as viewed from above, and the gate electrode of the second oxide film The portion on the side surface is covered with a third nitride film as viewed from above. Other features of the present invention will become apparent below.

本発明により、酸化膜と窒化膜の多層膜よりなるサイドウォールを有する半導体装置において、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされてゲート電極の側面が露出するのを防ぐことができる。   According to the present invention, in a semiconductor device having a sidewall made of a multilayer film of an oxide film and a nitride film, it is possible to prevent the oxide film constituting the sidewall from being etched during contact etching and exposing the side surface of the gate electrode. it can.

実施の形態１．
本発明の実施の形態１に係る半導体装置の製造工程について図１及び図２を用いて説明する。 Embodiment 1 FIG.
A manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

まず、図１（ａ）に示すように、半導体基板１１上に、ゲート絶縁膜１２、ポリシリコン膜１３、ＯＮＯ膜１４、ポリシリコン膜１５、ＷＳｉ膜１６、及び、第１の窒化膜であるＳｉＮ膜１７を順番に形成する。   First, as shown in FIG. 1A, a gate insulating film 12, a polysilicon film 13, an ONO film 14, a polysilicon film 15, a WSi film 16, and a first nitride film are formed on a semiconductor substrate 11. SiN films 17 are formed in order.

次に、図１（ｂ）に示すように、ＳｉＮ膜１７をフォトリソグラフィ等によりパターニングする。そして、図１（ｃ）に示すように、エッチングによりＳｉＮ膜１７の上面の角を丸くする。   Next, as shown in FIG. 1B, the SiN film 17 is patterned by photolithography or the like. Then, as shown in FIG. 1C, the corners of the upper surface of the SiN film 17 are rounded by etching.

次に、図２（ａ）に示すように、ＳｉＮ膜１７をマスクにして、ＷＳｉ膜１６、ポリシリコン膜１５、ＯＮＯ膜１４、ポリシリコン膜１３及びゲート絶縁膜１２を異方性エッチングする。これにより、ポリシリコン膜１３、ポリシリコン膜１５及びＷＳｉ膜１６からなるゲート電極が形成される。より具体的には、ポリシリコン膜１３がフローティングゲートであり、ポリシリコン膜１５がコントロールゲートである。   Next, as shown in FIG. 2A, anisotropic etching is performed on the WSi film 16, the polysilicon film 15, the ONO film 14, the polysilicon film 13, and the gate insulating film 12 using the SiN film 17 as a mask. Thereby, a gate electrode composed of the polysilicon film 13, the polysilicon film 15, and the WSi film 16 is formed. More specifically, the polysilicon film 13 is a floating gate, and the polysilicon film 15 is a control gate.

次に、図２（ｂ）に示すように、全面に、第１の酸化膜であるＳｉＯ２膜１８、第２の窒化膜であるＳｉＮ膜１９、第２の酸化膜であるＳｉＯ２膜２０、及び、第３の窒化膜であるＳｉＮ膜２１を順番に形成する。ここで、ＳｉＯ２膜１８及びＳｉＯ２膜２０として、ＴＥＯＳ膜又は熱酸化膜を用いることができる。また、ＳｉＮ膜１９及びＳｉＮ膜２１はＣＶＤ法により形成することができる。なお、ＳｉＯ２膜１８を形成する前に、ゲート電極の側壁を保護するために、熱酸化又はラジカル酸化によりゲート電極の側壁に酸化膜を形成してもよい。ただし、ラジカル酸化は酸化力が強く、ゲート電極全体と半導体基板１１を酸化膜で覆うように酸化膜を形成できるため、ＳｉＯ２膜１８及びＳｉＯ２膜２０をラジカル酸化により形成してもよい。 Next, as shown in FIG. 2B, the SiO 2 film 18 as the first oxide film, the SiN film 19 as the second nitride film, and the SiO 2 film 20 as the second oxide film are formed on the entire surface. Then, a SiN film 21 as a third nitride film is formed in order. Here, as the SiO 2 film 18 and the SiO 2 film 20, a TEOS film or a thermal oxide film can be used. The SiN film 19 and the SiN film 21 can be formed by a CVD method. Before forming the SiO 2 film 18, an oxide film may be formed on the side wall of the gate electrode by thermal oxidation or radical oxidation in order to protect the side wall of the gate electrode. However, since radical oxidation has strong oxidizing power and an oxide film can be formed so as to cover the entire gate electrode and the semiconductor substrate 11 with an oxide film, the SiO 2 film 18 and the SiO 2 film 20 may be formed by radical oxidation.

次に、図２（ｃ）に示すように、全面エッチバックにより、ゲート電極及びＳｉＮ膜１７の側壁にサイドウォールを形成する。このサイドウォールは、ＳｉＯ２膜１８、ＳｉＮ膜１９、ＳｉＯ２膜２０及びＳｉＮ膜２１からなる。 Next, as shown in FIG. 2C, sidewalls are formed on the sidewalls of the gate electrode and the SiN film 17 by etch-back of the entire surface. This sidewall is composed of a SiO 2 film 18, a SiN film 19, a SiO 2 film 20 and a SiN film 21.

このように、ゲート電極と、サイドウォールのＳｉＮ膜２１との間に、ＳｉＯ２膜１８、ＳｉＮ膜１９及びＳｉＯ２膜２０からなるＯＮＯ膜を設ける。このＯＮＯ膜により、ゲート電極に負バイアスを印加した場合でも、窒化膜中の電気伝導を支配している正孔の流れを阻止し、ゲート電極の特にＷＳｉ膜１６近傍の窒化膜にホールが蓄積されるのを防ぎ、実効的な耐圧の低下を防ぐことができる。 Thus, an ONO film composed of the SiO 2 film 18, the SiN film 19, and the SiO 2 film 20 is provided between the gate electrode and the SiN film 21 on the sidewall. Even when a negative bias is applied to the gate electrode, this ONO film prevents the flow of holes that governs electrical conduction in the nitride film, and accumulates holes in the nitride film of the gate electrode, particularly in the vicinity of the WSi film 16. It is possible to prevent the effective breakdown voltage from being lowered.

ただし、ゲート電極―コンタクト間に電圧が印加された場合でもFN(Fowler-Nordheim)トンネルが起こらないように、ゲート電極側にあるＳｉＯ２膜１８の膜厚は５０Å以上、好ましくは７０Å以上に設定する必要がある。 However, the thickness of the SiO 2 film 18 on the gate electrode side is set to 50 mm or more, preferably 70 mm or more so that no FN (Fowler-Nordheim) tunnel occurs even when a voltage is applied between the gate electrode and the contact. There is a need to.

実施の形態１に係る半導体装置を用いてコンタクトエッチングを行った状態を図３に示す。半導体装置を覆うようにＳｉＯ２からなる層間絶縁膜２２を形成し、この層間絶縁膜２２をフォトリソグラフィ等により異方性エッチングする。この際、エッチングの選択性を持たせることでＳｉＮ膜２１はエッチングされないようにする。これにより、ゲート電極上にコンタクトが乗り上げたＳＡＣ構造を形成することができる。 FIG. 3 shows a state where contact etching is performed using the semiconductor device according to the first embodiment. An interlayer insulating film 22 made of SiO 2 is formed so as to cover the semiconductor device, and this interlayer insulating film 22 is anisotropically etched by photolithography or the like. At this time, the SiN film 21 is prevented from being etched by providing etching selectivity. Thereby, it is possible to form a SAC structure in which a contact rides on the gate electrode.

このコンタクトエッチングでは、酸化膜を選択的に異方性エッチングするため、サイドウォールを構成するＳｉＯ２膜１８及びＳｉＯ２膜２０もエッチングされる。しかし、ＳｉＮ膜１７は、上面の角が丸まっていて、上部の外径が下部の外径よりも小さいため、ＳｉＯ２膜１８のゲート電極の側面にある部分は、上面から見てＳｉＮ膜１９で覆われ、ＳｉＯ２膜２０のゲート電極の側面にある部分は、上面から見てＳｉＮ膜２１で覆われている。これにより、コンタクトエッチングにおいて、ＳｉＯ２膜１８及びＳｉＯ２膜２０は、ゲート電極の側面にある部分まではエッチングされない。 In this contact etching, since the oxide film is selectively anisotropically etched, the SiO 2 film 18 and the SiO 2 film 20 constituting the sidewall are also etched. However, since the upper corner of the SiN film 17 is rounded and the outer diameter of the upper part is smaller than the outer diameter of the lower part, the portion of the SiO 2 film 18 on the side surface of the gate electrode is viewed from the upper surface. The portion on the side surface of the gate electrode of the SiO 2 film 20 is covered with the SiN film 21 as viewed from above. Thereby, in the contact etching, the SiO 2 film 18 and the SiO 2 film 20 are not etched up to the portion on the side surface of the gate electrode.

従って、本実施の形態１に係る半導体装置ならば、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされてゲート電極の側面が露出するのを防ぐことができる。   Therefore, in the semiconductor device according to the first embodiment, it is possible to prevent the oxide film constituting the sidewall from being etched during contact etching and exposing the side surface of the gate electrode.

なお、フラッシュメモリの構造を例に挙げて説明したが、本発明は、ＭＯＳトランジスタ等に使用しても同様の効果を奏する。   Although the structure of the flash memory has been described as an example, the present invention provides the same effect even when used for a MOS transistor or the like.

実施の形態２．
図４は、本発明の実施の形態２に係る半導体装置を示す断面図である。図１及び２と同様の構成要素には同じ番号を付し、説明を省略する。 Embodiment 2. FIG.
FIG. 4 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. Constituent elements similar to those in FIGS.

実施の形態２に係る半導体装置では、第１の窒化膜であるＳｉＮ膜１７が、上方にいくほど外径が小さくなるテーパー形状であり、上部の外径が下部の外径よりも小さくなっている。このため、ＳｉＯ２膜１８のゲート電極の側面にある部分は、上面から見てＳｉＮ膜１９で覆われ、ＳｉＯ２膜２０のゲート電極の側面にある部分は、上面から見てＳｉＮ膜２１で覆われている。これにより、コンタクトエッチングにおいて、ＳｉＯ２膜１８及びＳｉＯ２膜２０は、ゲート電極の側面にある部分まではエッチングされない。 In the semiconductor device according to the second embodiment, the SiN film 17 that is the first nitride film has a tapered shape in which the outer diameter decreases as it goes upward, and the outer diameter of the upper part becomes smaller than the outer diameter of the lower part. Yes. For this reason, the portion of the SiO 2 film 18 on the side surface of the gate electrode is covered with the SiN film 19 as viewed from above, and the portion of the SiO 2 film 20 on the side surface of the gate electrode is covered with the SiN film 21 as viewed from above. Covered. Thereby, in the contact etching, the SiO 2 film 18 and the SiO 2 film 20 are not etched up to the portion on the side surface of the gate electrode.

従って、実施の形態２に係る半導体装置ならば、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされてゲート電極の側面が露出するのを防ぐことができる。   Therefore, in the semiconductor device according to the second embodiment, it is possible to prevent the oxide film constituting the sidewall from being etched during contact etching and exposing the side surface of the gate electrode.

実施の形態３．
本発明の実施の形態３に係る半導体装置の製造工程について図５を用いて説明する。図１及び２と同様の構成要素には同じ番号を付し、説明を省略する。 Embodiment 3 FIG.
A manufacturing process of the semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. Constituent elements similar to those in FIGS.

まず、図５（ａ）に示すように、半導体基板１１上に、ゲート絶縁膜１２、ポリシリコン膜１３、ＯＮＯ膜１４、ポリシリコン膜１５、ＷＳｉ膜１６、及び、第１の窒化膜であるＳｉＮ膜１７を順番に形成する。そして、フォトレジスト２３によりＳｉＮ膜１７の一部を覆った状態で、ＳｉＮ膜１７を途中まで異方性エッチングする。これにより、ＳｉＮ膜１７には凸部が形成される。   First, as shown in FIG. 5A, a gate insulating film 12, a polysilicon film 13, an ONO film 14, a polysilicon film 15, a WSi film 16, and a first nitride film are formed on a semiconductor substrate 11. SiN films 17 are formed in order. Then, the SiN film 17 is anisotropically etched halfway with the photoresist 23 covering a part of the SiN film 17. Thereby, a convex portion is formed in the SiN film 17.

次に、図５（ｂ）に示すように、ＳｉＮ膜１７の上にＴＥＯＳ膜２４を形成し、全面エッチバックにより、ＳｉＮ膜１７の凸部の側壁のみにＴＥＯＳ膜２４が残るようにしてサイドウォールを形成する。   Next, as shown in FIG. 5B, a TEOS film 24 is formed on the SiN film 17, and the TEOS film 24 remains on only the side walls of the convex portions of the SiN film 17 by etching back the entire surface. Form a wall.

次に、図５（ｃ）に示すように、ＳｉＮ膜１７をエッチングして凸部及びＴＥＯＳ膜２４で覆われた部分以外を除去する。そして、残ったＳｉＮ膜１７及びＴＥＯＳ膜２４をマスクにして、ＷＳｉ膜１６、ポリシリコン膜１５、ＯＮＯ膜１４、ポリシリコン膜１３及びゲート絶縁膜１２を異方性エッチングする。これにより、ポリシリコン膜１３、ポリシリコン膜１５及びＷＳｉ膜１６からなるゲート電極が形成される。   Next, as shown in FIG. 5C, the SiN film 17 is etched to remove portions other than the convex portions and the portions covered with the TEOS film 24. Then, using the remaining SiN film 17 and TEOS film 24 as a mask, the WSi film 16, the polysilicon film 15, the ONO film 14, the polysilicon film 13 and the gate insulating film 12 are anisotropically etched. Thereby, a gate electrode composed of the polysilicon film 13, the polysilicon film 15, and the WSi film 16 is formed.

そして、APM (ammoniaperoxide-mixture)等によるウェットエッチングによりＴＥＯＳ膜２４を完全に除去して、実施の形態１と同様にサイドウォールを形成すると、図６に示すような実施の形態３に係る半導体装置が形成される。ただし、図７に示すようにＴＥＯＳ膜２４を少しだけ残すか、ウェットエッチングをしないで図８に示すようにＴＥＯＳ膜２４をそのまま残してもよい。   Then, when the TEOS film 24 is completely removed by wet etching using APM (ammoniaperoxide-mixture) or the like and a sidewall is formed as in the first embodiment, the semiconductor device according to the third embodiment as shown in FIG. Is formed. However, the TEOS film 24 may be left slightly as shown in FIG. 7, or the TEOS film 24 may be left as it is as shown in FIG. 8 without performing wet etching.

この実施の形態３に係る半導体装置では、第１の窒化膜は、上部の外径が下部の外径に比べて階段状に小さくなっているノッチ形状であり、上部の外径が下部の外径よりも小さいため、ＳｉＯ２膜１８のゲート電極の側面にある部分は、上面から見てＳｉＮ膜１９で覆われ、ＳｉＯ２膜２０のゲート電極の側面にある部分は、上面から見てＳｉＮ膜２１で覆われている。これにより、コンタクトエッチングにおいて、ＳｉＯ２膜１８及びＳｉＯ２膜２０は、ゲート電極の側面にある部分まではエッチングされない。 In the semiconductor device according to the third embodiment, the first nitride film has a notch shape in which the upper outer diameter is stepwise smaller than the lower outer diameter, and the upper outer diameter is the outer diameter of the lower part. Since the diameter is smaller than the diameter, the portion of the SiO 2 film 18 on the side surface of the gate electrode is covered with the SiN film 19 when viewed from the upper surface, and the portion of the SiO 2 film 20 on the side surface of the gate electrode is SiN when viewed from the upper surface. Covered with a membrane 21. Thereby, in the contact etching, the SiO 2 film 18 and the SiO 2 film 20 are not etched up to the portion on the side surface of the gate electrode.

従って、実施の形態３に係る半導体装置ならば、サイドウォールを構成する酸化膜がコンタクトエッチングの際にエッチングされてゲート電極の側面が露出するのを防ぐことができる。   Therefore, the semiconductor device according to the third embodiment can prevent the oxide film constituting the sidewall from being etched during contact etching and exposing the side surface of the gate electrode.

本発明の実施の形態１に係る半導体装置の製造工程を示す断面図（１）である。It is sectional drawing (1) which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の製造工程を示す断面図（２）である。It is sectional drawing (2) which shows the manufacturing process of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置を用いてコンタクトエッチングを行った状態を示す断面図である。It is sectional drawing which shows the state which performed contact etching using the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の別の例を示す断面図である。It is sectional drawing which shows another example of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の更に別の例を示す断面図である。It is sectional drawing which shows another example of the semiconductor device which concerns on Embodiment 3 of this invention. 従来の半導体装置の断面図を示す断面図である。It is sectional drawing which shows sectional drawing of the conventional semiconductor device. 従来の半導体装置を用いてコンタクトエッチングを行った状態を示す断面図である。It is sectional drawing which shows the state which performed contact etching using the conventional semiconductor device.

符号の説明Explanation of symbols

１１ 半導体基板
１２ ゲート絶縁膜
１３ ポリシリコン膜（ゲート電極）
１５ ポリシリコン膜（ゲート電極）
１６ ＷＳｉ膜（ゲート電極）
１７ ＳｉＮ膜（第１の窒化膜）
１８ ＳｉＯ２膜（サイドウォール）
１９ ＳｉＮ膜（サイドウォール）
２０ ＳｉＯ２膜（サイドウォール）
２１ ＳｉＮ膜（サイドウォール） 11 Semiconductor substrate 12 Gate insulating film 13 Polysilicon film (gate electrode)
15 Polysilicon film (gate electrode)
16 WSi film (gate electrode)
17 SiN film (first nitride film)
18 SiO 2 film (side wall)
19 SiN film (side wall)
20 SiO 2 film (side wall)
21 SiN film (side wall)

Claims (4)

半導体基板上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記ゲート電極上に形成された第１の窒化膜と、
前記ゲート電極及び前記第１の窒化膜の側面に順番に形成された第１の酸化膜、第２の窒化膜、第２の酸化膜及び第３の窒化膜からなるサイドウォールとを有し、
前記第１の窒化膜は、上部の外径が下部の外径よりも小さく、
前記第１の酸化膜の前記ゲート電極の側面にある部分は、上面から見て前記第２の窒化膜で覆われ、
前記第２の酸化膜の前記ゲート電極の側面にある部分は、上面から見て前記第３の窒化膜で覆われていることを特徴とする半導体装置。 A gate insulating film formed on a semiconductor substrate;
A gate electrode formed on the gate insulating film;
A first nitride film formed on the gate electrode;
A side wall including a first oxide film, a second nitride film, a second oxide film, and a third nitride film sequentially formed on the side surfaces of the gate electrode and the first nitride film;
The first nitride film has an upper outer diameter smaller than a lower outer diameter,
A portion of the first oxide film on a side surface of the gate electrode is covered with the second nitride film as viewed from above.
A portion of the second oxide film on the side surface of the gate electrode is covered with the third nitride film as viewed from above. 前記第１の窒化膜は、上面の角が丸まっていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first nitride film has rounded corners on the upper surface. 前記第１の窒化膜は、上方にいくほど外径が小さくなるテーパー形状であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first nitride film has a tapered shape in which an outer diameter decreases toward an upper side. 前記第１の窒化膜は、上部の外径が下部の外径に比べて階段状に小さくなることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first nitride film has an upper outer diameter that is smaller than a lower outer diameter in a stepped manner.
JP2004207205A 2004-07-14 2004-07-14 Semiconductor device Pending JP2006032541A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461138B2 (en) 2012-02-28 2016-10-04 Seiko Epson Corporation Non-volatile semiconductor memory with nitride sidewall contacting nitride layer of ONO gate stack and methods for producing the same

Citations (2)

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JPH10144787A (en) * 1996-11-07 1998-05-29 Fujitsu Ltd Semiconductor device and fabrication thereof
JP2002252232A (en) * 2001-02-13 2002-09-06 Samsung Electronics Co Ltd Semiconductor device having spacer comprised of multi- layer film and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144787A (en) * 1996-11-07 1998-05-29 Fujitsu Ltd Semiconductor device and fabrication thereof
JP2002252232A (en) * 2001-02-13 2002-09-06 Samsung Electronics Co Ltd Semiconductor device having spacer comprised of multi- layer film and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461138B2 (en) 2012-02-28 2016-10-04 Seiko Epson Corporation Non-volatile semiconductor memory with nitride sidewall contacting nitride layer of ONO gate stack and methods for producing the same

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