JP2006087257A - Multilevel converter and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high performance multilevel converter which has many output voltage levels and a low high-frequency voltage with the number of devices fewer than a conventional one, thereby preventing the device from being damaged by an excessive voltage and simplifying the control of the multilevel converter by avoiding loss concentrated on a specified device without using a specified means. <P>SOLUTION: First to third capacitors C1 to C3 are sequentially connected in series between the positive electrode and the negative electrode of a DC power source, a controllable device and a diode are connected inversely parallel with each other to constitute a reverse conduction switch, and first to fourth reverse conduction switches Q1 to Q4 are sequentially connected in series between the positive electrode and the negative electrode. The junction point of the Q2, Q3 is made to be an AC input/output terminal AC, a fifth reverse conduction switch Q5 is connected between the junction point of the Q1, Q2 and the junction point of the capacitors C1, C2, and a sixth reverse conduction switch Q6 is connected between the junction point of the Q3, Q4 and the junction point of the capacitors C2, C3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power converter that converts AC power into DC power or converts DC power into AC power, and is a multilevel converter (multilevel rectifier or multilevel inverter) having a plurality of voltage levels on the AC power side. ) And its control method.

FIG. 16 is a circuit diagram of a minimum unit (hereinafter referred to as a unit converter) of a three-level converter using an IGBT as a controllable device.
In FIG. 16, the potential at the neutral point M is approximately halfway between the positive electrode P and the negative electrode N with respect to the positive electrode P and the negative electrode N of the DC power supply, and a capacitor C1 is interposed between the positive electrode P and the neutral point M. A capacitor C2 is connected between the neutral point M and the negative electrode N.
IGBTs T1, T2, T3, and T4 are sequentially connected in series between the positive electrode P and the negative electrode N, and diodes D1, D2, D3, and D4 are connected in antiparallel to each IGBT. Here, the connection point of the IGBTs T2 and T3 is an AC input / output terminal AC.

IGBTs T5 and T6 are connected between the connection points of the IGBTs T1 and T2 and the neutral point M, and between the connection points of the IGBTs T3 and T4 and the neutral point M, respectively. Diodes D5 and D6 are connected to each other.
A pair formed by connecting a controllable device such as IGBT and a diode in reverse parallel to each other is in a conductive state with respect to the reverse voltage direction of the controllable device due to the action of the diode. The pair is called a reverse conduction switch, and these reverse conduction switches are represented by reference numerals Q1 to Q6 as shown in FIG.
If necessary, the reverse conduction switches Q1 and Q4 are called outer switches, Q2 and Q3 are called inner switches, Q5 and Q6 are called clamp switches, and the diodes D5 and D6 of the clamp switches Q5 and Q6 are particularly called clamp diodes.

In order to increase the high-voltage and large-capacity of the multilevel converter, there are cases where a series reverse conduction switch is configured by connecting a plurality of switching devices such as controllable devices and diodes in series.
FIG. 17 is a circuit diagram of a conventional three-level unit converter in which two reverse conduction switches shown in FIG. 16 are connected in series to constitute reverse conduction switches Q1A to Q6A.
Note that these reverse conduction switches Q1A to Q6A are sometimes referred to as n series (two series in the example of FIG. 17) reverse conduction switches.

Since the principle of the present invention does not change in the case of a rectifier or an inverter as a multilevel converter, a multilevel inverter will be described below as an example.
18 is a configuration diagram of a single-phase three-level inverter configured by connecting two unit converters (hereinafter referred to as unit inverter INV) shown in FIG. 16 or FIG. 17 in parallel, and FIG. 19 is a diagram illustrating a unit inverter INV. It is a block diagram of the three-phase three-level inverter comprised by connecting three in parallel.
Since the number of phases of the inverter is not related to the principle of the present invention, the unit inverter will be described below.

As the three-level inverter, a three-level inverter constituted by only a clamp diode except for a controllable device from the clamp switch of FIG. 16 or FIG. 17 is generally used.
On the other hand, in the case where the clamp switch includes a controllable device, the controllable device is always turned off to use only the function of the clamp diode, or applied to the outer switch and the inner switch in the off state. It is common to use a clamp switch to make the voltages approximately equal.
However, in order to use the clamp switch more effectively, the following proposals have been conventionally made.

In Patent Document 1, the outer switch and the clamp switch are switched in synchronization with the output voltage command of the inverter, and the two inner switches are alternately turned on and off at a predetermined switching frequency. As a result, since the target output voltage can be obtained without pulse width modulation between the outer switch and the clamp switch, there is an advantage that an inexpensive and low-speed controllable device can be applied to the outer switch and the clamp switch.
In Patent Document 2, the clamp switch is turned on immediately before the inner switch is turned off in order to reduce an overvoltage generated when the inner switch is turned off.
In Patent Document 3, for example, the inner switch Q3 and the clamp switch Q5 in FIG. 16 and the inner switch Q2 and the clamp switch Q6 are controlled to conduct at the same time or almost simultaneously, thereby reducing the inductance of the commutation loop. Reduce the overvoltage that occurs when the switch turns off.

  In Non-Patent Document 1, for the purpose of increasing the output limit of the three-level converter, the gate signal of the controllable device is controlled so as to equalize the generated loss of each switching device.

JP-A-5-211776 (paragraphs [0009] to [0011], FIG. 1, FIG. 2, etc.) JP-A-6-165511 (paragraph [0014], FIG. 1, FIG. 2, etc.) JP 2003-88138 A (paragraphs [0008], [0013], [0140], FIG. 1, FIG. 3, etc.) US Patent Application Publication No. 2003/0165071 (paragraphs [0012] to [0020], FIGS. 2 to 5 etc.)

Here, in order to clarify the problem to be solved and the basic idea of the present invention, the path of the output current when the output voltage of the inverter is zero will be described using the prior art of FIG. 16 or FIG.
16 or 17, when the output current _Io is a positive value, the path of the output current is a path that flows through the reverse conduction switches Q5 and Q2 (hereinafter referred to as an upper path) and a path that flows through the reverse conduction switches Q6 and Q3. (Hereinafter referred to as the lower path) can be selected by gate control of the controllable device. Similarly, when the output current _Io is a negative value, two paths can be selected: an upper path through the reverse conduction switches Q2 and Q5 and a lower path through the reverse conduction switches Q3 and Q6. In Non-Patent Document 1 described above, the loss of each switching device is balanced by appropriately selecting the two current paths, and the output limit of the inverter is expanded.

  By the way, in the prior art shown in FIG. 16 or FIG. 17, since the clamp switches Q5, Q6 or Q5A, Q6A are all connected to the neutral point M, the lower path is selected even if the upper path is selected. However, the output voltage has a zero value, which hinders an increase in the number of levels of the output voltage. Moreover, in FIG. 17, since all reverse conducting switches are constituted by series reverse conducting switches, the number of switching devices is large, which causes an increase in the size of the inverter.

Therefore, in the present invention, as shown in FIGS. 16 and 17, the two clamp switches are connected to a neutral point having the same potential, and the large number of switching devices improves the performance of the multilevel converter. In view of the fact that the miniaturization is hindered.
That is, the problems to be solved by the present invention are as follows.
(1) To provide a high-performance multilevel converter with a smaller number of switching devices than before, a large number of output voltage levels, and a low harmonic voltage.
(2) The overvoltage generated at the time of switching of the controllable device is shared by the plurality of switching devices, thereby preventing the switching device from being damaged by the overvoltage.
(3) The control of the multilevel converter is simplified by making it possible to avoid loss concentration on a specific switching device without using special means.

In order to solve the above-mentioned problem, a multilevel converter according to claim 1 is:
The first to third capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power supply,
A controllable device and a diode are connected in antiparallel to form a reverse conduction switch, and first to fourth reverse conduction switches are sequentially connected in series between the positive electrode and the negative electrode,
The connection point between the second reverse conduction switch and the third reverse conduction switch is an AC input / output terminal,
A fifth reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
A sixth reverse conduction switch is connected between a connection point between the third reverse conduction switch and the fourth reverse conduction switch and a connection point between the second capacitor and the third capacitor.

The multi-level converter according to claim 2 is:
The first to third capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power supply,
A reverse conduction switch is configured by a pair of controllable devices and diodes connected in antiparallel, or by connecting a plurality of pairs in series, and the first to fourth reverse conductions between the positive electrode and the negative electrode Connect the switches in series,
At least two of the first to fourth reverse conducting switches are configured by connecting a plurality of pairs in which a controllable device and a diode are connected in antiparallel, connected in series,
The connection point between the second reverse conduction switch and the third reverse conduction switch is an AC input / output terminal,
A fifth reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
A sixth reverse conduction switch is connected between a connection point between the third reverse conduction switch and the fourth reverse conduction switch and a connection point between the second capacitor and the third capacitor.

The multi-level converter according to claim 3 is characterized in that in claim 2,
The second and third reverse conducting switches are configured by connecting two pairs of controllable devices and diodes connected in antiparallel in series, and the voltages of the first to third capacitors are substantially equal. It is.

A multi-level converter according to claim 4 is the method of claim 2,
The second and third reverse conduction switches are configured by connecting three pairs of controllable devices and diodes connected in antiparallel in series, and the voltage of the first capacitor is set to the voltage of the third capacitor. The voltage of the second capacitor is approximately equal to the voltage of the first or third capacitor.

The multi-level converter according to claim 5 is the method of claim 2,
The second and third reverse conducting switches are configured by connecting four pairs of controllable devices and diodes connected in antiparallel in series, and the voltage of the first capacitor is set to the voltage of the third capacitor. The voltage of the second capacitor is approximately equal to the voltage of the first or third capacitor.

The control method according to claim 6 is the multilevel converter according to any one of claims 1 to 5,
An ON signal is given to the sixth reverse conduction switch when the first or second reverse conduction switch is in the ON state;
A mode in which an ON signal is applied to the fifth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the first reverse conduction switch;
A mode in which an ON signal is applied to the third reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the second reverse conduction switch;
And a mode in which an ON signal is supplied to the fourth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is supplied to the sixth reverse conduction switch.

The control method according to claim 7 is the multilevel converter according to any one of claims 1 to 5,
An ON signal is given to the fifth reverse conduction switch when the third or fourth reverse conduction switch is in the ON state,
A mode in which an ON signal is applied to the sixth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the fourth reverse conduction switch;
A mode in which an ON signal is applied to the second reverse conducting switch after a predetermined delay time has elapsed since the OFF signal is applied to the third reverse conducting switch;
And a mode in which an ON signal is applied to the first reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the fifth reverse conduction switch.

The control method according to claim 8 is the control method according to claim 6 or 7,
When the second or third reverse conducting switch is switched, an ON signal is given to both the fifth and sixth reverse conducting switches.

The multi-level converter according to claim 9 is:
The first to fifth capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power source,
A reverse conduction switch is formed by a pair of controllable devices and diodes connected in antiparallel or by connecting a plurality of pairs in series, and first to sixth reverse conductions between the positive electrode and the negative electrode Connect the switches in series,
The connection point between the third reverse conduction switch and the fourth reverse conduction switch is an AC input / output terminal,
A seventh reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
An eighth reverse conduction switch is connected between a connection point between the second reverse conduction switch and the third reverse conduction switch and a connection point between the second capacitor and the third capacitor;
A ninth reverse conduction switch is connected between a connection point between the fourth reverse conduction switch and the fifth reverse conduction switch and a connection point between the third capacitor and the fourth capacitor;
The tenth reverse conduction switch is connected between the connection point of the fifth reverse conduction switch and the sixth reverse conduction switch and the connection point of the fourth capacitor and the fifth capacitor.

The control method according to claim 10 is the multilevel converter according to claim 9,
An ON signal is given to the ninth and tenth reverse conduction switches when any of the first to third reverse conduction switches is in an ON state,
A mode in which an ON signal is supplied to the seventh reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is supplied to the first reverse conduction switch, and a predetermined delay time after the OFF signal is supplied to the second reverse conduction switch A mode in which an ON signal is given to the eighth reverse conduction switch after the elapse of time, a mode in which an ON signal is given to the fourth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal has been given to the third reverse conduction switch, A mode in which an ON signal is applied to the fifth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the reverse conduction switch 9 and a predetermined delay time has elapsed since the OFF signal is applied to the tenth reverse conduction switch And a mode in which an ON signal is applied to the sixth reverse conduction switch later.

The control method according to claim 11 is the multilevel converter according to claim 9,
An ON signal is given to the seventh and eighth reverse conduction switches when any of the fourth to sixth reverse conduction switches is in an ON state,
A mode in which an ON signal is supplied to the tenth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is supplied to the sixth reverse conduction switch, and a predetermined delay time after the OFF signal is supplied to the fifth reverse conduction switch A mode in which an ON signal is applied to the ninth reverse conducting switch after the elapse of time, a mode in which an ON signal is applied to the third reverse conducting switch after a predetermined delay time has elapsed since the OFF signal is applied to the fourth reverse conducting switch, A mode in which an ON signal is applied to the second reverse conducting switch after a predetermined delay time has elapsed since the OFF signal is applied to the 8 reverse conducting switch, and a predetermined delay time has elapsed after the OFF signal is applied to the seventh reverse conducting switch. And a mode in which an ON signal is applied to the first reverse conduction switch later.

The control method according to claim 12 is the control method according to claim 10 or 11,
An on signal is given to the seventh reverse conduction switch when the second reverse conduction switch is turned off,
A mode in which an ON signal is given to the tenth reverse conduction switch when turning off the fifth reverse conduction switch, and an eighth and ninth reverse conduction switch when turning off the third or fourth reverse conduction switch Both have a mode in which an ON signal is given.

The multi-level converter according to claim 13 is:
Connect a plurality of capacitors in series between the positive and negative electrodes of the DC power supply,
A reverse conduction switch is formed by a pair formed by connecting a controllable device and a diode in antiparallel, or by connecting a plurality of pairs in series.
A first reverse conduction switch group formed by connecting a plurality of the reverse conduction switches in series is connected between the positive electrode and the AC input / output terminal.
A second reverse conduction switch group formed by connecting a plurality of the reverse conduction switches in series between an AC input / output terminal and the negative electrode;
A plurality of reverse conduction switches constituting a third reverse conduction switch group are respectively connected between a connection point between the reverse conduction switches constituting the first reverse conduction switch group and a connection point between the capacitors,
A plurality of reverse conduction switches constituting the fourth reverse conduction switch group are respectively connected between a connection point between the reverse conduction switches constituting the second reverse conduction switch group and a connection point between the capacitors,
The potentials at the connection points of the capacitors are different from each other.

The control method according to claim 14 is the multilevel converter according to claim 13,
The third reverse conduction switch connected to the positive terminal of the reverse conduction switch when turning off the reverse conduction switch of the first reverse conduction switch group excluding the reverse conduction switch connected to the positive electrode of the DC power supply ON signal is given to the reverse conduction switch of the group,
The fourth reverse conduction switch connected to the negative terminal of the reverse conduction switch when turning off the reverse conduction switch of the second reverse conduction switch group excluding the reverse conduction switch connected to the negative electrode of the DC power supply A mode in which an ON signal is given to the reverse conduction switch of the group;
Of the reverse conduction switches belonging to the first or second reverse conduction switch group, the third and fourth reverse conduction switches connected to the reverse conduction switch when switching the reverse conduction switch connected to the AC input terminal. And a mode in which an ON signal is applied to the reverse conducting switches of the group.

  A single-phase or multi-phase multilevel converter according to claim 15 uses the multilevel converter according to any one of claims 1 to 5, 9, and 13 as a unit converter, and a plurality of the unit converters are connected in parallel. It is composed.

According to the present invention, the following effects can be obtained with respect to a conventional three-level converter or a multi-level converter exceeding three levels.
(1) A DC power supply voltage is divided into a plurality of DC potentials by a capacitor, and a clamp switch is configured by a reverse conduction switch in which a controllable device and a diode are connected in antiparallel, and these switches are set to different DC potentials. By connecting, it is possible to reduce the number of switching devices to be used under the same output capacity than before, so the size of the converter can be reduced, and the number of AC voltage levels is large, and voltage harmonics are high. A high-performance multi-level converter can be provided.
(2) At the time of switching of the reverse conduction switch connected to the AC input / output terminal, the controllable device is arranged so that the voltage applied to the reverse conduction switch is clamped to the capacitor voltage having a voltage lower than the steady voltage by the clamp switch. By controlling, overvoltage at the time of switching can be reduced.
(3) When the output voltage of the inverter is low and low frequency, there is no problem that current is concentrated only on a specific reverse conduction switch during the half-cycle of the output, and the output capacity is made larger than that of the conventional multilevel inverter. Can do. In addition, unlike the conventional three-level inverter to which the clamp switch is applied, it is not necessary to selectively control the current path in order to avoid current concentration, so that control of the controllable device can be simplified.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram of a unit converter according to a first embodiment of the present invention, and corresponds to claim 1. In FIG. 1, capacitors C1, C2, and C3 are sequentially connected in series between a positive electrode P and a negative electrode N of a DC power source. Further, IGBTs T1, T2, T3, and T4 as controllable devices are sequentially connected in series between the positive electrode P and the negative electrode N, and diodes D1, D2, D3, and D4 are connected in antiparallel to each IGBT. Has been. Here, the connection point of the IGBTs T2 and T3 is an AC input / output terminal AC.

  The IGBT T5 is connected between the connection point of the IGBTs T1 and T2 and the connection point of the capacitors C1 and C2, and the IGBT T6 is connected between the connection point of the IGBTs T3 and T4 and the connection point of the capacitors C2 and C3. In addition, diodes D5 and D6 are connected in reverse parallel to the IGBTs T5 and T6, respectively.

  Also in this embodiment, Q1 to Q6 in which the IGBT and the diode are connected in antiparallel are referred to as reverse conduction switches, and Q1 and Q4 are outside switches, Q2 and Q3 are inside switches, and Q5 and Q6 are clamp switches as necessary. Say. The diodes D5 and D6 of the clamp switches Q5 and Q6 are referred to as clamp diodes.

By configuring the unit converter as shown in FIG. 1, the potential of the direct-current power source is such that the positive potential V ++ of the positive electrode P shown in FIG. 1 and a positive potential lower than the positive potential V ++ (the potential at the connection point of the capacitors C1 and C2) V +. In addition, there is a negative potential V−− of the negative electrode N and a negative potential higher than the negative potential V−− (connection potential of the capacitors C2 and C3) V−.
Taking the case of an inverter as an example, the potential of the output terminal AC becomes V ++ when the reverse conduction switches Q1 and Q2 are turned on, and becomes V + when the reverse conduction switches Q5 and Q2 are turned on. When the switches Q6 and Q3 are turned on, V− is obtained, and when the reverse conduction switches Q4 and Q3 are turned on, V−− is obtained. That is, the inverter can output four levels of voltage.

Here, FIG. 20 shows the configuration of a conventional 4-level unit converter using a clamp diode. In this unit converter, reverse conduction switches Q1 to Q6 are sequentially connected in series between a positive electrode P and a negative electrode N of a DC power supply, and a connection point of the reverse conduction switches Q3 and Q4 is used as an AC input / output terminal, and capacitors C1, C2 are connected. And diodes D7 and D8, respectively, between the connection point of the capacitor and the connection points of the reverse conduction switches Q1 and Q2, and between the connection point of the capacitors C1 and C2 and the connection point of the reverse conduction switches Q4 and Q5, respectively. Diodes D9 and D10 are respectively connected between the connection point of the capacitors C2 and C3 and the connection point of the reverse conduction switches Q2 and Q3, and between the connection point of the capacitors C2 and C3 and the connection point of the reverse conduction switches Q5 and Q6. Connected and configured.
Comparing the unit converter of FIG. 1 and the unit converter of FIG. 20, the embodiment of FIG. 1 requires fewer diodes, and a four-level converter (inverter) is configured with a smaller number of switching devices than FIG. can do.

  However, in the embodiment of FIG. 1, the steady state maximum voltage value applied to the reverse conduction switches Q2 and Q3 is higher than the maximum voltage value applied to the other reverse conduction switches. It is desirable to reduce the voltage applied to the reverse conduction switches Q2 and Q3 by a method such as designing the voltage lower than that of the other capacitors C1 and C3.

Next, FIG. 2 is a circuit diagram of a unit converter according to the second embodiment of the present invention, and corresponds to claims 2 and 3.
In this embodiment, at least two of the reverse conduction switches Q1 to Q6 shown in FIG. 1 are constituted by two series reverse conduction switches to reduce the voltage applied to each reverse conduction switch. In the example, the inner switches Q2A and Q3A are each composed of two series reverse conducting switches.

FIGS. 7 to 10 are operation explanatory diagrams of the second embodiment, and the path of the output current when the output voltage of the inverter changes from the positive potential V ++ to the negative potential V−− is indicated by a solid line.
7 to 10, the voltages of the capacitors C1 to C3 are substantially the same value (the potential difference between V ++ and V +, the potential difference between V + and V-, and the potential difference between V- and V-- are substantially the same value). As will be described later, the reverse conduction switches Q1 to Q6 are switched so that the maximum voltage of the capacitor C1, C2 or C3 is applied in the steady state, and the forward blocking voltage of the controllable device is correspondingly applied. And the reverse blocking voltage of the diode shall be selected.
In these drawings, a solid line represents a portion where current flows, a broken line represents a portion where current does not flow, and a switching device represented by a solid line represents an IGBT to which an ON signal is given and a diode that is turned on, A switching device indicated by a broken line represents an IGBT to which an off signal is applied and a diode that is turned off.

In FIG. 7, the IGBTs of the reverse conduction switches Q1 and Q2A are on, and the output voltage is V ++. At this time, an ON signal is given to the IGBT of the reverse conduction switch Q6, and the reverse conduction switch Q4 is clamped to the voltage of the capacitor C3. The sum of the voltages of the capacitors C1 and C2 is applied to the reverse conduction switch Q3A which is a two series reverse conduction switch.
As described above, the voltages of the capacitors C1 to C3 are substantially the same, and one capacitor voltage, that is, a voltage substantially equal to the voltage of the capacitor C1 or C2, is applied to each reverse conduction switch constituting the reverse conduction switch Q3A. Therefore, there is no possibility that an excessive voltage is applied as the blocking voltage.

Next, FIG. 8 shows a state in which an off signal is given to the IGBT of the reverse conduction switch Q1 in the state of FIG. 7, and an on signal is given to the IGBT of the reverse conduction switch Q5 after a predetermined delay time elapses. .
At this time, since current flows from the reverse conduction switch Q1 to the reverse conduction switch Q5, the output voltage changes from V ++ to V +. The voltage of the reverse conducting switch Q1 that is turned off is clamped to the voltage of the capacitor C1. The reverse conduction switch Q3A is clamped to the voltage of the capacitor C2, and the reverse conduction switch Q4 is clamped to the voltage of the capacitor C3.
In the following description, for example, giving an ON signal to the IGBT of the reverse conduction switch Q1 is simply referred to as giving an ON signal to the reverse conduction switch Q1, and similarly giving an OFF signal to the IGBT of Q1 simply gives an OFF signal to Q1. Say.

  FIG. 9 shows a state in which an off signal is given to the reverse conduction switch Q2A in the state of FIG. 8, and an on signal is given to the reverse conduction switch Q3A after a predetermined delay time elapses. At this time, the current is commutated from the reverse conduction switches Q5 and Q2A to the reverse conduction switches Q6 and Q3A, and the output voltage changes from V + to V-. The voltage of the reverse conducting switch Q2A that is turned off is clamped to the voltage of the capacitor C2.

  FIG. 10 shows a state in which an off signal is given to the reverse conduction switch Q6 in the state of FIG. 9, and an on signal is given to the reverse conduction switch Q4 after a predetermined delay time elapses. At this time, the current is commutated from the reverse conduction switch Q6 to the reverse conduction switch Q4, and the output voltage changes from V− to V−−. The voltage of the reverse conducting switch Q6 that is turned off is clamped to the voltage of the capacitor C3.

As described above, the reverse conducting switch or series reverse conducting switch that is turned off is clamped to any voltage of the capacitors C1 to C3 after commutation, and stable commutation is performed.
In particular, when the two series reverse conducting switch Q2A is turned off, the switch Q2A is clamped to the voltage of the capacitor C2, so that the voltages of the individual reverse conducting switches are unbalanced as when the conventional series reverse conducting switch is turned off. Thus, there is no problem that an overvoltage is applied to a specific reverse conducting switch. This is because the voltage of the capacitor C2 is a voltage that is constantly applied to one reverse conduction switch, and when the voltage of the capacitor C2 is applied to the two series reverse conduction switch Q2A, the voltage sharing is somewhat unbalanced. This is because it will not be a problem in itself.

Here, the output voltage waveform in the embodiment of FIG. 2 is the same as that of the conventional 4-level inverter (4-level unit converter) using the clamp diode shown in FIG. Has the following problems.
That is, when the output voltage of the inverter is sufficiently lower than the rated voltage, it is desirable that the four-level inverter outputs V + and V− alternately. In the conventional four-level inverter shown in FIG. 20, when the output current _Io is a positive value, the output current _Io is applied to the reverse conduction switch Q3 regardless of whether V + is selected as the output voltage or V− is selected. When the output current _Io is a negative value, the flow is via (the diode D7 for V +, the path of reverse conduction switches Q2 and Q3, the path of the diode D9 for V-, and the reverse conduction switch Q3). Regardless of whether V + is selected as the output voltage or V− is selected, the output current flows through the reverse conduction switch Q4 (in the case of V +, the reverse conduction switch Q4, the path of the diode D8, the reverse in the case of V−. The path of the conduction switches Q4 and Q5 and the diode D10 is taken).

  For this reason, for example, when the load is operated with a low voltage and a low frequency voltage such as an electric motor load, only the loss of the reverse conduction switches Q3 and Q4 in the output half cycle of the inverter is larger than the other reverse conduction switches, There is a problem that the output capacity of the inverter must be reduced due to these losses.

On the other hand, in the 4-level inverter shown in FIG. 2, when the output current _Io is positive, when V + is selected as the output voltage, the output current flows via the reverse conduction switch Q2A, and V− is selected. Output current flows through the reverse conduction switch Q3A. Similarly, when the output current _Io is negative, the output current flows via the reverse conduction switch Q2A when V + is selected as the output voltage, and the output current is reverse conduction when V− is selected. It flows via switch Q3A.

Therefore, in the embodiment of FIG. 2, a situation in which the output capacity of the inverter has to be reduced by concentrating the current only on a specific reverse conduction switch in the output half cycle as in the conventional four-level inverter. Does not occur.
Note that the above-mentioned Non-Patent Document 1 targets only the three-level converter and is characterized by avoiding current concentration of the three-level converter by selecting and controlling the current path in addition to the output voltage control. In this embodiment, since it is not necessary to select a current path, gate control can be simplified.

Next, FIG. 3 is a circuit diagram of a unit converter according to a third embodiment of the present invention, and corresponds to claims 2 and 4.
In this embodiment, at least two of the reverse conduction switches Q1 to Q6 shown in FIG. 1 are constituted by three series reverse conduction switches so that a high voltage can be output. In the example of FIG. Q2B and Q3B are each composed of three series reverse conducting switches.
Correspondingly, the voltage of the capacitor C1 and the voltage of the capacitor C3 are made substantially equal, and the voltage of the capacitor C2 is made almost twice the voltage of the capacitor C1 or C3. As a result, the potential difference between V ++ and V + and the potential difference between V− and V−− are substantially the same value, and the potential difference between V + and V− is approximately twice the potential difference.

  In this embodiment, when the three series reverse conducting switches Q2B and Q3B are switched, these switches are clamped to the voltage of the capacitor C2 having the double voltage. Also in this embodiment, the voltage applied to the individual reverse conduction switches connected in series can be reduced as compared with the prior art, and a higher-voltage and large-capacity multilevel converter can be configured than in the embodiment of FIG. Can do.

Note that when the embodiment of FIG. 3 is compared with the three-level converter shown in FIG.
That is, when FIG. 3 is compared with FIG. 17, the number of switching devices constituting the outer switches Q1, Q4 and Q1A, Q4A and the inner switches Q2B, Q3B and Q2A, Q3A is different, but the positive electrode of the DC power supply is different. The total number of reverse conduction switches connected between P and the negative electrode N is eight.
Therefore, when the same switching device is used, the voltage of the DC power source in FIGS. 3 and 17 is designed to be almost the same voltage value, and the capacity of the inverter is almost the same in the case of FIG. 3 and FIG. It will be the same.

Considering the above premise, the following features of the present embodiment will become clear when FIG. 3 is compared with the embodiment and the prior art of FIG.
(1) Focusing on the series number of switching devices constituting the clamp switch, the number of clamp switches Q5A and Q6A in FIG. 17 is two, whereas the number of clamp switches Q5 and Q6 in FIG. 3 is one. is decreasing.
(2) In FIG. 17, since the clamp switches Q5A and Q6A are connected to the neutral point M having the same potential, the output voltage is three levels of positive value, zero value, and negative value, whereas in FIG. Since the switches Q5 and Q6 are connected to the potential point of V + and the potential point of V-, respectively, there are four voltage levels that can be output such that the positive potential is V ++, V + and the negative potential is V-, V--. Therefore, a high-performance multilevel converter with a small harmonic voltage can be configured.

  FIG. 3 shows a case where two capacitors are connected in series as the capacitor C2. This is a conceptual illustration showing that the voltage of the capacitor C2 is almost twice the voltage of the capacitor C1 or C3. However, the configuration of the capacitor is not necessarily shown. For example, the capacitor C2 may be single. This is the same in other drawings.

Next, FIG. 4 is a circuit diagram of a unit converter according to the fourth embodiment of the present invention, and corresponds to claims 2 and 5.
In this embodiment, the inner switches Q2C and Q3C are constituted by 4 series reverse conducting switches, the voltage of the capacitor C1 is made substantially equal to the voltage of the capacitor C3, and the voltage of the capacitor C2 is made approximately three times the voltage of the capacitor C1 or C3. It is a thing.

  In this embodiment, the maximum voltage value in the steady state applied to all the reverse conduction switches can be designed to be substantially equal, and a multi-level converter having a higher voltage and a larger capacity than that in the case of FIG. 3 can be configured. Further, according to this configuration, the potential difference between V + and V ++ and the potential difference between V− and V−− are substantially equal, and the potential difference between V + and V− is approximately three times the potential difference. Other configurations are the same as those in FIG.

In each of the embodiments of FIGS. 2 to 4, the inner switch is configured by an n series reverse conduction switch. However, as another embodiment of the second aspect, the configuration of the fifth embodiment shown in FIG. 5 can also be adopted.
In the embodiment of FIG. 5, the outer switches Q1A and Q4A and the clamp switches Q5A and Q6A are two series reverse conducting switches, and the inner switches Q2B and Q3B are constituted by three series reverse conducting switches. Further, the voltages of the capacitors C1 and C3 are approximately twice the voltage of the capacitor C2.

  In this case, the maximum voltage value in the steady state applied to all the reverse conduction switches can be designed to be substantially equal. In this embodiment, the potential difference between V + and V ++ and the potential difference between V− and V−− are approximately twice the potential difference between V + and V−. Other configurations are the same as those in FIG.

Next, FIG. 6 is a circuit diagram of a unit converter according to the sixth embodiment of the present invention, and corresponds to claim 9.
In the embodiment of FIG. 6, capacitors C1 to C5 are sequentially connected in series between the positive electrode P and the negative electrode N of the DC power supply, and reverse conduction switches Q1, Q2, 3 series reverse conduction switches Q3B, Q4B, reverse The conduction switches Q5 and Q6 are connected in series, and the connection point of the three series reverse conduction switches Q3B and Q4B is an AC input / output terminal AC.
Further, a reverse conduction switch Q7 is connected between the connection point of the reverse conduction switches Q1 and Q2 and the connection point of the capacitors C1 and C2, and the connection point between the reverse conduction switches Q2 and Q3B and the connection point of the capacitors C2 and C3. Two series reverse conduction switches Q8A are connected between them, and two series reverse conduction switches Q9A are connected between the connection points of the reverse conduction switches Q4B and Q5 and the connection points of the capacitors C3 and C4. A reverse conduction switch Q10 is connected between the connection point and the connection point of the capacitors C4 and C5.

  In this embodiment, the output voltage has six levels of V ++++, V ++, V +, V−, V−−, and V −−− shown in FIG. Further, when the voltages of the capacitors C1 to C5 are set to substantially equal values, it is possible to design so that the maximum voltage values in the steady state applied to all the reverse conduction switches are substantially equal.

Next, an embodiment of the control method according to the present invention will be described in detail with reference to FIG. 11 as a time chart of gate control corresponding to the above-described FIGS.
FIG. 11 is an example of a time chart when the output voltage of the inverter changes from V ++ to V−−, which is applied to the gate control of the above-described embodiments of FIGS. 1 to 5 (first to fifth embodiments). Yes, corresponding to claims 6 and 8.

In Figure 11, _{V o} is the output voltage command of the inverter indicates V ++ and V +, V + and V-, V- and V-- where potential difference is all equal 2 as a representative example. G1 to G6 indicate gate signals of the reverse conduction switches Q1 to Q6 (including the two series reverse conduction switches Q2A and Q3A in FIG. 2), respectively, and the on signal is high when it is low and the off signal when it is low. Is given to each controllable device.

In the period (1) in FIG. 11, the output voltage command _{V o} is V ++, to turn on at least the reverse conducting switch Q1, Q2A correspondingly. At the same time, an ON signal is given to the reverse conduction switch Q6, and the voltage of the reverse conduction switch Q4 is clamped to the voltage of the capacitor C3. As described above, the voltage of the reverse conduction switch Q3A is substantially equal to the voltage of the capacitor C1 or C2.

When the output voltage command V _o changes from V ++ to V +, the process proceeds to the period (2) gives off signals to the reverse-conducting switches Q1, giving an ON signal to the reverse conducting switch Q5 after a predetermined delay time Td elapses. In this state, the reverse conduction switches Q5 and Q2A are turned on, and the output voltage becomes V +.
When the output voltage command V _o changes from V + to V−, an off signal is given to the reverse conduction switch Q2A and the period (3) is started, and an on signal is given to the reverse conduction switch Q3A after a predetermined delay time Td has elapsed. Since the ON signal is given to the reverse conduction switch Q6 in advance, in this state, the reverse conduction switches Q6 and Q3A are turned on and the output voltage becomes V-.
Note that the above periods (2) and (3) correspond to FIGS. 8 and 9, respectively.

Thus, the control method in which the ON signal is given to both the reverse conduction switches Q5 and Q6 when the period (2) is shifted to the period (3), that is, when the inner switch Q2A or Q3A is switched, is provided. This corresponds to the embodiment.
As shown in FIG. 8, it is assumed that a current flows through the IGBT constituting the reverse conduction switch Q2A. At this time, when the IGBT is turned off, the impedance of the reverse conduction switch Q2A increases and the voltage of the reverse conduction switch Q2A rises. When this voltage rises above the voltage of the capacitor C2, a forward voltage is applied to the diode of the reverse conduction switch Q3A, and commutation from the reverse conduction switch Q2A to Q3A is started. At this time, since the ON signal is given to the reverse conduction switches Q5 and Q6, a commutation loop of Q2A → Q5 → C2 → Q6 → Q3A is formed even after commutation is completed from the start of commutation. The flow is done.

Further, as described above, since the two series reverse conduction switch Q2A is clamped to the voltage of the capacitor C2, even if voltage imbalance occurs in the individual reverse conduction switches constituting the reverse conduction switch Q2A at the time of turn-off, these reverse conduction It is possible to prevent the switch from being damaged by overvoltage.
When the output voltage command V _o is changed to V-- from V-, and turns off the reverse conducting switch Q6 shifts to the period (4) in FIG. 11, and turns on the reverse conducting switch Q4 after a predetermined delay time Td elapses. In this state, the output voltage becomes V−− when the reverse conduction switch Q4 is turned on.

FIG. 12 is an example of a time chart when the output voltage of the inverter changes from V−− to V ++, which is applied to the gate control of the above-described embodiments of FIGS. 1 to 5 (first to fifth embodiments). Yes, corresponding to claims 7 and 8. Similar to FIG. 11, the output voltage command _{V o} shows a case of V ++ and V +, V + and V-, all equal potential difference V- and V-- 2 as a representative example.

12 output voltage command _{V o} in the period (1) of a V-, to turn on at least the reverse conducting switch Q3A, Q4 correspondingly. At the same time, an ON signal is given to the reverse conduction switch Q5, and the voltage of the reverse conduction switch Q1 is clamped to the voltage of the capacitor C1. Similar to the case of FIG. 11, the voltage of the reverse conduction switch Q2A becomes substantially equal to the voltage of the capacitor C2 or C3.
When the output voltage command V _o is changed to V- from V-, moves to the period (2) gives off signals to the reverse-conducting switch Q4, gives an ON signal to the reverse conducting switch Q6 after a predetermined delay time Td elapses . In this state, the reverse conduction switches Q6 and Q3A are turned on and the output voltage becomes V-.

When the output voltage command changes from V− to V +, an OFF signal is given to the reverse conduction switch Q3A, the process proceeds to the period (3), and an ON signal is given to the reverse conduction switch Q2A after a predetermined delay time Td has elapsed. Since the ON signal is given to the reverse conduction switch Q5 in advance, in this state, the reverse conduction switches Q5 and Q2A are turned on and the output voltage becomes V +.
At this time, that is, when the inner switch Q2A or Q3A is switched, the control method in which the ON signal is given to the reverse conduction switches Q5 and Q6 corresponds to the embodiment of claim 8.

As shown in FIG. 9, it is assumed that a current flows through the diode constituting the reverse conduction switch Q3A immediately before the ON signal is given to the reverse conduction switch Q2A. At this time, when the reverse conduction switch Q2A is turned on, the diode of the reverse conduction switch Q3A reversely recovers, and generally a problem of voltage sharing of the Q3A which is the two series reverse conduction switch occurs. However, since the 2-series reverse conduction switch Q3A is clamped to the voltage of the capacitor C2 as described above, it is possible to prevent the individual reverse conduction switches constituting the 2-series reverse conduction switch Q3A from being damaged by overvoltage. .
When the output voltage command changes from V + to V ++, the reverse conduction switch Q5 is turned off to shift to the period (4), and the column reverse conduction switch Q1 is turned on after a predetermined delay time Td has elapsed. In this state, the output voltage becomes V ++ by turning on the reverse conduction switch Q1.

Next, the time chart of FIG. 13 will be described.
FIG. 13 is a time chart when the output voltage of the inverter changes from V ++ to V −−−, which is applied to the gate control of the embodiment (sixth embodiment) shown in FIG. Equivalent to.
In FIG. 13, G1 to G10 indicate gate signals of the reverse conduction switches Q1 to Q10 (including the three series reverse conduction switches Q3B and Q4B and the two series reverse conduction switches Q8A and Q9A in FIG. 6), respectively. Sometimes an off signal is applied to each controllable device when the on signal is low.

In the period (1) in FIG. 13, the output voltage command _{V o} is V +++, to turn on at least the reverse conducting switch Q1, Q2 and Q3B correspondingly. At the same time, an ON signal is also applied to the reverse conduction switches Q9A and Q10. The voltage of the reverse conduction switch Q6 is clamped to the capacitor C5, and the voltage of the reverse conduction switch Q5 is clamped to the voltage of the capacitor C4.
When the output voltage command changes from V ++ to V ++, an OFF signal is given to the reverse conduction switch Q1 and the period (2) is started, and an ON signal is given to the reverse conduction switch Q7 after a predetermined delay time Td has elapsed. In this state, the reverse conduction switch Q7 is turned on and the output voltage becomes V ++.

When the output voltage command V _o changes from V ++ to V +, the process proceeds to the period (3) gives off signals to the reverse-conducting switch Q2, providing an ON signal to the reverse conducting switch Q8A after a predetermined delay time Td elapses. In this state, the reverse conduction switch Q8A is turned on and the output voltage becomes V +.
When the output voltage command changes from V + to V-, an off signal is given to the reverse conduction switch Q3B and the period (4) is started, and an on signal is given to the reverse conduction switch Q4B after a predetermined delay time Td has elapsed. Since the ON signal is given in advance to the reverse conduction switch Q9A, in this state, the reverse conduction switches Q9A and Q4B are turned on and the output voltage becomes V-.

When the output voltage command V _o is changed to V-- from V-, moves to the period (5) giving off signals in the reverse conducting switch Q9A, gives an ON signal to the reverse conducting switch Q5 after a predetermined delay time Td elapses . Since the ON signal is given to the reverse conduction switch Q10 in advance, the reverse conduction switches Q10 and Q5 are turned on in this state, and the output voltage becomes V−−.
When the output voltage command V _o transitions from V-- the V ---, moves to the period (6) gives off signals to the reverse-conducting switches Q10, on signal to the reverse conducting switch Q6 after a predetermined delay time Td elapses give. In this state, the reverse conduction switch Q6 is turned on and the output voltage becomes V ---.

Next, the time chart of FIG. 14 will be described. FIG. 14 is a time chart applied to the gate control of the embodiment (sixth embodiment) shown in FIG. 6 when the output voltage of the inverter changes from V −−− to V ++. Equivalent to. Meaning of V _o and G1~G10 is similar to FIG 13.

In the period (1) in FIG. 14, the output voltage command _{V o} is V ---, is turned on at least reverse conducting switch Q4B, Q5 and Q6 correspondingly. At the same time, an ON signal is given to the reverse conduction switches Q7 and Q8A, the voltage of the reverse conduction switch Q1 is clamped to the capacitor C1, and the voltage of the reverse conduction switch Q2 is clamped to the voltage of the capacitor C2.
When the output voltage command V _o changes from V --- the V-, moves to the period (2) gives off signals to the reverse-conducting switch Q6, on signal to the reverse conducting switch Q10 after a predetermined delay time Td elapses give. In this state, the reverse conduction switch Q10 is turned on and the output voltage becomes V--.

When the output voltage command changes from V-- to V-, an off signal is given to the reverse conduction switch Q5 and the period (3) is started, and an on signal is given to the reverse conduction switch Q9A after a predetermined delay time Td has elapsed. In this state, the reverse conduction switch Q9A is turned on and the output voltage becomes V-. When the output voltage command V _o changes from V− to V +, an OFF signal is given to the reverse conduction switch Q4B and the period (4) is started, and an ON signal is given to the reverse conduction switch Q3B after a predetermined delay time Td has elapsed. Since the ON signal is given to the reverse conduction switch Q8A in advance, the reverse conduction switches Q8A and Q3B are turned on in this state, and the output voltage becomes V +.

When the output voltage command V _o changes from V + to V ++, moves to the period (5) giving off signals in the reverse conducting switch Q8A, gives an ON signal to the reverse conducting switch Q2 after a predetermined delay time Td elapses. Since the ON signal is given to the reverse conduction switch Q7 in advance, the reverse conduction switches Q7 and Q2 are turned on in this state, and the output voltage becomes V ++.
When the output voltage command V _o is transferred to the V +++ from V ++, moves to the period (6) gives off signals to the reverse-conducting switch Q7, gives an ON signal to the reverse conducting switch Q1 after a predetermined delay time Td elapses. In this state, the reverse conduction switch Q1 is turned on and the output voltage becomes V ++++.

Other characteristic features in the time charts of FIGS. 13 and 14 are as follows.
In any time chart, an ON signal is given to the reverse conduction switch Q7 when the reverse conduction switch Q2 is turned off, and an ON signal is given to the reverse conduction switch Q10 when the reverse conduction switch Q5 is turned off. When switching the reverse conduction switch Q3B or Q4B which is a switch, an ON signal is given to the reverse conduction switches Q8A and Q9A which are clamp switches. Such an idea corresponds to the twelfth aspect, whereby a commutation loop can be secured from the time of commutation to after commutation, and stable commutation and overvoltage reduction after commutation are achieved. .

  Next, when the multilevel converter according to the present invention is generalized, it can be applied to, for example, a multilevel converter exceeding six levels. This idea corresponds to claim 13. Further, a single-phase or multi-phase multi-level converter configured by connecting a plurality of unit converters of the above-described embodiments in parallel corresponds to claim 15.

An embodiment of the invention of claim 13 will be described. As shown in FIG. 15, first, a single reverse conduction switch formed by connecting a controllable device and a diode in antiparallel, or a plurality of reverse conduction switches in series. N series reverse conduction switch (all are set to the code | symbol Q) is comprised.
A plurality of capacitors C, C,... Are connected in series between the positive electrode P and the negative electrode N of the DC power source, and a plurality of reverse conduction switches Q are connected between the positive electrode P and the AC input / output terminal AC. A first reverse conduction switch group QG1 connected in series and a plurality of reverse conduction switches Q connected in series between the AC input / output terminal AC and the negative electrode N are connected to each other. Connect the group QG2.

A plurality of third reverse conduction switch groups QG3 are formed between the connection points of the reverse conduction switches Q constituting the first reverse conduction switch group QG1 and the connection points of the capacitors C, C,... Are connected between the connection points of the reverse conduction switches Q and the connection points of the capacitors C, C,... Constituting the second reverse conduction switch group QG2. A plurality of reverse conduction switches Q constituting the conduction switch group QG4 are connected to each other. Here, the potential at the connection point between the capacitors C, C,... Is different.
The present invention is applicable to all multilevel converters having the above-described configuration.

  Finally, an embodiment when the control method (gate control method) according to the present invention is generalized will be described. This control method corresponds to claim 14 and is intended for the multilevel converter shown in FIG.

That is, when turning off the reverse conduction switch of the first reverse conduction switch group QG1 excluding the reverse conduction switch connected to the positive electrode P of the DC power source, the terminal on the positive electrode P side of the reverse conduction switch (the reverse conduction switch is An ON signal is given to the reverse conduction switch of the third reverse conduction switch group QG3 connected to the collector terminal of the IGBT to be configured). For example, in FIGS. 6 and 13 described above, when the reverse conduction switch Q2 or Q3B is turned off, an ON signal is given to the reverse conduction switch Q7.
When turning off the reverse conduction switch of the second reverse conduction switch group QG2 excluding the reverse conduction switch connected to the negative electrode N of the DC power supply, the terminal on the negative electrode N side of the reverse conduction switch (the reverse conduction switch is An ON signal is given to the reverse conduction switch of the fourth reverse conduction switch group QG4 connected to the emitter terminal of the IGBT to be configured). For example, in FIGS. 6 and 14 described above, when turning off the reverse conduction switches Q5 and Q4B, an ON signal is given to the reverse conduction switch Q10.

Further, among the reverse conduction switches belonging to the first or second reverse conduction switch group QG1, QG2, when switching the reverse conduction switch connected to the AC input terminal AC, the third and the third conduction switches connected to the reverse conduction switch An ON signal is given to the reverse conduction switches of the fourth reverse conduction switch groups QG3 and QG4. For example, in FIGS. 6 and 13 described above, when the reverse conduction switches Q3B and Q4B are switched, ON signals are given to the reverse conduction switches Q8A and Q9A.
By adopting such a control method, a commutation loop is secured from commutation to after commutation, and stable commutation is performed and overvoltage is prevented from being applied to the reverse conduction switch after commutation. Can do.

1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a circuit diagram which shows 3rd Embodiment of this invention. It is a circuit diagram which shows 4th Embodiment of this invention. It is a circuit diagram which shows 5th Embodiment of this invention. It is a circuit diagram which shows 6th Embodiment of this invention. It is operation | movement explanatory drawing of 2nd Embodiment. It is operation | movement explanatory drawing of 2nd Embodiment. It is operation | movement explanatory drawing of 2nd Embodiment. It is operation | movement explanatory drawing of 2nd Embodiment. It is a time chart which shows the gate control in 1st-5th embodiment. It is a time chart which shows the gate control in 1st-5th embodiment. It is a time chart which shows the gate control in 6th Embodiment. It is a time chart which shows the gate control in 6th Embodiment. It is a block diagram of the multilevel converter which generalized this invention. It is a circuit diagram of the conventional 3 level unit converter. It is a circuit diagram of the conventional 3 level unit converter. It is a block diagram of the conventional single phase 3 level inverter. It is a block diagram of the conventional 3 phase 3 level inverter. It is a circuit diagram of the conventional 4-level unit converter.

Explanation of symbols

Q1-Q7, Q10: Reverse conduction switch Q1A, Q2A, Q2B, Q2C, Q3A, Q3B, Q3C, Q4A, Q4B, Q5A, Q6A, Q8A, Q9A: Series reverse conduction switch Q: Reverse conduction switch QG1-QG4; -4th reverse conduction switch group T1-T6: Controllable device (IGBT)
D1-D6: Diode C, C1-C5: Capacitor P: Positive electrode N: Negative electrode AC: AC input / output terminal

Claims (15)

In a multi-level converter that converts AC power and DC power to each other and generates multiple voltage levels on the AC side,
The first to third capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power supply,
A controllable device and a diode are connected in antiparallel to form a reverse conduction switch, and first to fourth reverse conduction switches are sequentially connected in series between the positive electrode and the negative electrode,
The connection point between the second reverse conduction switch and the third reverse conduction switch is an AC input / output terminal,
A fifth reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
A sixth reverse conduction switch is connected between a connection point between the third reverse conduction switch and the fourth reverse conduction switch and a connection point between the second capacitor and the third capacitor. Multi-level converter. In a multi-level converter that converts AC power and DC power to each other and generates multiple voltage levels on the AC side,
The first to third capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power supply,
A reverse conduction switch is configured by a pair of controllable devices and diodes connected in antiparallel, or by connecting a plurality of pairs in series, and the first to fourth reverse conductions between the positive electrode and the negative electrode Connect the switches in series,
At least two of the first to fourth reverse conduction switches are configured by connecting a plurality of pairs in which a controllable device and a diode are connected in antiparallel, connected in series,
The connection point between the second reverse conduction switch and the third reverse conduction switch is an AC input / output terminal,
A fifth reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
A sixth reverse conduction switch is connected between a connection point between the third reverse conduction switch and the fourth reverse conduction switch and a connection point between the second capacitor and the third capacitor. Multi-level converter. The multi-level converter according to claim 2,
The second and third reverse conducting switches are configured by connecting two pairs of controllable devices and diodes connected in antiparallel in series,
A multilevel converter characterized in that the voltages of the first to third capacitors are substantially equal. The multi-level converter according to claim 2,
The second and third reverse conducting switches are configured by connecting three pairs of controllable devices and diodes connected in antiparallel in series,
A multi-level converter, characterized in that the voltage of the first capacitor is substantially equal to the voltage of the third capacitor, and the voltage of the second capacitor is approximately twice the voltage of the first or third capacitor. The multi-level converter according to claim 2,
The second and third reverse conducting switches are configured by connecting four pairs of controllable devices and diodes connected in antiparallel in series,
A multi-level converter, characterized in that the voltage of the first capacitor is substantially equal to the voltage of the third capacitor, and the voltage of the second capacitor is approximately three times the voltage of the first or third capacitor. In the multi-level converter according to any one of claims 1 to 5,
An ON signal is given to the sixth reverse conduction switch when the first or second reverse conduction switch is in the ON state;
A mode in which an ON signal is applied to the fifth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the first reverse conduction switch;
A mode in which an ON signal is applied to the third reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the second reverse conduction switch;
A mode in which an ON signal is applied to the fourth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the sixth reverse conduction switch;
A control method for a multi-level converter, comprising: In the multi-level converter according to any one of claims 1 to 5,
An ON signal is given to the fifth reverse conduction switch when the third or fourth reverse conduction switch is in the ON state,
A mode in which an ON signal is applied to the sixth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the fourth reverse conduction switch;
A mode in which an ON signal is applied to the second reverse conducting switch after a predetermined delay time has elapsed since the OFF signal is applied to the third reverse conducting switch;
A mode in which an ON signal is applied to the first reverse conduction switch after a predetermined delay time has elapsed since an OFF signal is applied to the fifth reverse conduction switch;
A control method for a multi-level converter, comprising: In the control method of the multilevel converter according to claim 6 or 7,
A control method for a multilevel converter, wherein when the second or third reverse conducting switch is switched, an ON signal is given to both the fifth and sixth reverse conducting switches. In a multi-level converter that converts AC power and DC power to each other and generates multiple voltage levels on the AC side,
The first to fifth capacitors are sequentially connected in series between the positive electrode and the negative electrode of the DC power source,
A reverse conduction switch is formed by a pair of controllable devices and diodes connected in antiparallel or by connecting a plurality of pairs in series, and first to sixth reverse conductions between the positive electrode and the negative electrode Connect the switches in series,
The connection point between the third reverse conduction switch and the fourth reverse conduction switch is an AC input / output terminal,
A seventh reverse conduction switch is connected between a connection point between the first reverse conduction switch and the second reverse conduction switch and a connection point between the first capacitor and the second capacitor;
An eighth reverse conduction switch is connected between a connection point between the second reverse conduction switch and the third reverse conduction switch and a connection point between the second capacitor and the third capacitor;
A ninth reverse conduction switch is connected between a connection point between the fourth reverse conduction switch and the fifth reverse conduction switch and a connection point between the third capacitor and the fourth capacitor;
A tenth reverse conduction switch is connected between a connection point between the fifth reverse conduction switch and the sixth reverse conduction switch and a connection point between the fourth capacitor and the fifth capacitor. Multi-level converter. The multi-level converter according to claim 9,
An ON signal is given to the ninth and tenth reverse conduction switches when any of the first to third reverse conduction switches is in an ON state,
A mode in which an ON signal is given to the seventh reverse conduction switch after a predetermined delay time has elapsed since the OFF signal was given to the first reverse conduction switch;
A mode in which an ON signal is applied to the eighth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the second reverse conduction switch;
A mode in which an ON signal is given to the fourth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is given to the third reverse conduction switch;
A mode in which an ON signal is applied to the fifth reverse conduction switch after a predetermined delay time has elapsed since an OFF signal is applied to the ninth reverse conduction switch;
A mode in which an ON signal is applied to the sixth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the tenth reverse conduction switch;
A control method for a multi-level converter, comprising: The multi-level converter according to claim 9,
An ON signal is given to the seventh and eighth reverse conduction switches when any of the fourth to sixth reverse conduction switches is in an ON state,
A mode in which an ON signal is applied to the tenth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the sixth reverse conduction switch;
A mode in which an ON signal is applied to the ninth reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the fifth reverse conduction switch;
A mode in which an ON signal is applied to the third reverse conduction switch after a predetermined delay time has elapsed since the OFF signal is applied to the fourth reverse conduction switch;
A mode in which an ON signal is applied to the second reverse conducting switch after a predetermined delay time has elapsed since the OFF signal is applied to the eighth reverse conducting switch;
A mode in which an ON signal is applied to the first reverse conduction switch after a predetermined delay time has elapsed since an OFF signal is applied to the seventh reverse conduction switch;
A control method for a multi-level converter, comprising: In the control method of the multilevel converter according to claim 10 or 11,
An on signal is given to the seventh reverse conduction switch when the second reverse conduction switch is turned off,
A mode in which an ON signal is given to the tenth reverse conduction switch when turning off the fifth reverse conduction switch;
A mode in which an ON signal is given to both the eighth and ninth reverse conduction switches when turning off the third or fourth reverse conduction switch;
A control method for a multi-level converter, comprising: In a multi-level converter that converts AC power and DC power to each other and generates multiple voltage levels on the AC side,
Connect a plurality of capacitors in series between the positive and negative electrodes of the DC power supply,
A reverse conduction switch is formed by a pair formed by connecting a controllable device and a diode in antiparallel, or by connecting a plurality of pairs in series.
A first reverse conduction switch group formed by connecting a plurality of the reverse conduction switches in series is connected between the positive electrode and the AC input / output terminal.
A second reverse conduction switch group formed by connecting a plurality of the reverse conduction switches in series between an AC input / output terminal and the negative electrode;
A plurality of reverse conduction switches constituting a third reverse conduction switch group are respectively connected between a connection point between the reverse conduction switches constituting the first reverse conduction switch group and a connection point between the capacitors,
A plurality of reverse conduction switches constituting the fourth reverse conduction switch group are respectively connected between a connection point between the reverse conduction switches constituting the second reverse conduction switch group and a connection point between the capacitors,
A multi-level converter characterized in that the potentials of the connection points of the capacitors are all different potentials. The multi-level converter according to claim 13,
The third reverse conduction switch connected to the positive terminal of the reverse conduction switch when turning off the reverse conduction switch of the first reverse conduction switch group excluding the reverse conduction switch connected to the positive electrode of the DC power supply ON signal is given to the reverse conduction switch of the group,
The fourth reverse conduction switch connected to the negative terminal of the reverse conduction switch when turning off the reverse conduction switch of the second reverse conduction switch group excluding the reverse conduction switch connected to the negative electrode of the DC power supply A mode in which an ON signal is given to the reverse conduction switch of the group;
Of the reverse conduction switches belonging to the first or second reverse conduction switch group, the third and fourth reverse conduction switches connected to the reverse conduction switch when switching the reverse conduction switch connected to the AC input terminal. A mode in which an ON signal is given to the reverse conduction switch of the group;
A control method for a multi-level converter, comprising:   A single-phase or multi-phase multi-level, wherein the multi-level converter according to any one of claims 1 to 5, 9, and 13 is used as a unit converter and a plurality of the unit converters are connected in parallel. converter.

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