JP2006080988A - Preamplifier - Google Patents

Abstract

A transimpedance type pre-receiver that receives signals of a plurality of transmission speeds with significantly different speeds, ensures a wide dynamic range with a receiving sensitivity corresponding to the transmission speed, and secures an optimum frequency band. An amplifier is provided.
A preamplifier including an internal gain control unit and a transimpedance unit is provided with a decoder unit that outputs a transmission rate information signal. The internal gain control unit is provided by a transmission rate information signal from the decoder unit. And the transimpedance unit 14 is controlled. The internal gain control unit 13 and the transimpedance unit 14 connect switching elements in parallel or in series to a plurality of resistors connected in parallel or in series so that the resistance value is digitally controlled by turning on / off the switching elements. . In addition, at least one resistor among a plurality of resistors connected in series or in parallel is always selected so that the feedback resistance value does not become zero or infinite.
[Selection] Figure 1

Description

  The present invention relates to a preamplifier used in an optical communication system or the like, and more particularly to a transimpedance type preamplifier.

  In a receiving device using optical communication, a preamplifier circuit that converts an optical signal received by a light receiving element into a voltage signal is required to have a low noise and a wide dynamic range. A transimpedance type preamplifier is generally used to satisfy such a requirement. A typical transimpedance type amplifier circuit connects a feedback resistor between the input and output of the amplifier and changes the impedance value of the feedback resistor according to the input power to ensure a wide dynamic range. (For example, refer to Patent Document 1 and Patent Document 2).

  FIG. 6A is a schematic diagram illustrating an example of a general preamplifier. The preamplifier has a transimpedance circuit 3 connected in parallel with the amplifier circuit 2 and a light receiving element 1 such as a photodiode connected to the input side. For example, the transimpedance circuit 3 is formed by connecting a controllable variable resistance element Qf such as a field effect transistor (FET) in parallel with the feedback resistor Rf so that the impedance value can be varied by a signal from the control circuit 4. To be.

The optical signal received by the light receiving element 1 outputs a signal current Iin corresponding to the received light intensity, and this signal current is converted by the preamplifier 2 into a voltage signal of the output voltage Vout. Here, assuming that the feedback resistance is Rf, between the signal current Iin on the input side and the output voltage Vout on the amplification output side,
Vout = −Iin · Rf
It is known that there is a relationship. In this preamplifier, by increasing the feedback resistance Rf, sufficient sensitivity, that is, sufficient output voltage can be obtained even for a minute signal current.

  However, if the resistance value of the feedback resistor Rf is large, when the amplitude of the input signal current increases, the output amplitude is saturated, and the output waveform is distorted. Therefore, when the input signal current increases, the impedance value (feedback resistance value) of the transimpedance circuit 3 is equivalently reduced, and the signal current that is shunted to the transimpedance circuit 3 side is increased, thereby increasing the output amplitude. Is prevented from being saturated, and a dynamic range can be secured.

  Various transimpedance circuits 3 have been proposed so far. As a general circuit, for example, as shown in FIG. 6A, for example, an FET (Qf) that can be used in a variable resistance manner. Is connected in parallel to the feedback resistor Rf, and the output voltage Vout information is input to the gate as the gate voltage. In this case, when the current value of the input signal is less than or equal to the predetermined value, the output voltage is small and Qf is turned off, and feedback is performed only by the feedback resistor Rf based on the above relational expression. When the signal current on the input side exceeds a predetermined value, the output voltage also increases, so that the gate voltage of Qf is changed by the control circuit 4 to cause conduction between the source and the drain, and the feedback resistance value as a whole is reduced. Output saturation is avoided.

Also, when receiving and amplifying optical signals having different transmission speeds with the same receiver, the reception sensitivity varies greatly. For this reason, for example, a method is known in which a transimpedance circuit is formed by connecting a plurality of feedback resistors in series so that these feedback resistors can be selectively turned on and off (see, for example, Patent Document 3). . According to this method, it is said that the impedance value for feedback can be greatly changed, and it is possible to cope with the transmission speed.
JP-A-9-232877 JP 11-340745 A US Pat. No. 5,382,920

  In recent years, in optical communications, multiplexed optical transmission systems based on US standard SONET (Synchronous Optical NET) or international standard SDH (Synchronous Digital Hierarchy) are used. It has become. As specifications common to these SONET / SDH, for example, transmission rates are standardized at 155.52 Mbps, 622.08 Mbps, and 2.48832 Mbps. In this case, the reception sensitivity required for each transmission rate is significantly different from -34 dBm, -28 dBm, and -18 dBm, and higher sensitivity is required as the transmission rate becomes lower.

  In order to obtain a transimpedance type preamplifier capable of dealing with a plurality of transmission rates that are several times different from each other, not only can a signal be received, but also satisfy the required reception sensitivity specifications at each transmission rate. There is a need. For this purpose, it is effective to use the techniques disclosed in Patent Documents 1 to 3, and if the transimpedance circuit as shown in FIG. Good. FIG. 6B is a diagram showing the relationship between the equivalent feedback resistance of the transimpedance circuit and the gate voltage of the FET (Qf). Even when the transmission speed changes from low speed, medium speed, and high speed, the operation range is shown. This can be realized by precisely controlling by changing the value.

On the other hand, the −3 dB frequency band fc of the transimpedance type amplifier is that the internal gain of the amplifier is A, the feedback resistance value is R, the input capacitance (the junction capacitance of the light receiving element + the input capacitance of the amplifier + the stray capacitance loaded on the mounting). ) Is Cs, it can be generally expressed by the following formula.
fc = A / (2π · R · Cs)
By controlling the feedback resistor R according to the transmission speed, a predetermined operating characteristic can be obtained, but changing the feedback resistor R changes the frequency band of the amplifier. In other words, in order to obtain an optimum band according to the transmission rate, it is not sufficient to control the feedback resistance, and at the same time, it is necessary to control the internal gain of the amplifier.

However, in the above-described conventional technology, the control of the feedback resistor R and the control of the internal gain A at the same time are not taken into consideration. Further, even if the internal gain A is adjusted, it is performed separately from the adjustment of the feedback resistor R. For this reason, optimal transimpedance gain, bandwidth, and input dynamic range cannot be ensured for a plurality of transmission rates.
The present invention has been made in view of the above-described circumstances, and receives signals of a plurality of transmission rates having significantly different speeds, ensures a wide dynamic range with reception sensitivity corresponding to the transmission speed, and an optimum frequency band. It is an object of the present invention to provide a transimpedance type preamplifier capable of ensuring the above.

  A preamplifier according to the present invention is a preamplifier including an internal gain control unit and a transimpedance unit, and includes a decoder unit that outputs a transmission rate information signal, and an internal gain control unit based on the transmission rate information signal from the decoder unit. And controls the transimpedance section. The internal gain control unit and the transimpedance unit connect a switching element in parallel or in series to a plurality of resistors connected in parallel or in series so that the resistance value is digitally controlled by turning on / off the switching element. In addition, at least one resistor among a plurality of resistors connected in series or in parallel may be always selected so that the feedback resistance value does not become zero or infinite.

  In the preamplifier according to the present invention, a variable resistance element that can be controlled instead of the switching element is connected to at least one of the plurality of resistors connected in series or in parallel, and the signal level on the amplification output side The resistance value is controlled in an analog manner according to the above. In this case, a fixed resistance element may be connected in series to a variable resistance element that can be variably controlled to reduce the voltage dependency of the variable resistance element.

  According to the present invention, by changing the internal gain and transimpedance digitally according to the transmission rate information, the minimum reception sensitivity at each transmission rate can be satisfied, and a wide dynamic range is secured by analog adjustment. can do. Further, since the internal gain of the amplifier is simultaneously controlled while changing the transimpedance, a predetermined frequency band can be secured.

  The outline of the embodiment of the present invention will be described with reference to the block diagram of FIG. In the figure, 11 is a light receiving element, 12 is a transistor, 13 is an internal gain control unit, 14 is a transimpedance unit, 15 is a decoder unit, 16 is a buffer stage, and 17 is an output buffer stage.

  The preamplifier according to the present invention is a preamplifier suitable for optical communication that has a transimpedance unit 14 as a feedback resistor and performs current-voltage conversion on an optical signal received by a light receiving element 11 such as a PIN photodiode. A reception signal based on a signal current generated by light reception from the light receiving element 11 is input to the emitter-grounded transistor 12 as an amplifying element. The internal gain of the amplifier is determined by the transistor 12 which is an amplification stage and the internal gain control unit 13 which also serves as the load. The output of the amplification stage is a buffer stage 16 comprising the following emitter follower circuit or the like, and the output impedance is lowered and the output is raised. The output of the buffer stage 16 is further input to a main amplification stage (not shown) via an output buffer 17.

  The present invention is a preamplifier configured as described above, and a signal related to transmission rate information in optical transmission is simultaneously input to the internal gain control unit 13 and the transimpedance unit 14, and the internal gain and transimpedance of the amplifier are obtained by this signal. The setting value of can be changed. The transmission rate information is, for example, an information unit having a transmission rate greatly different from several times to several tens of times as defined in SONET OC-3, OC-12, and OC-48. A predetermined transmission speed can be selected from the speeds. The selected transmission rate is converted into a digital signal or the like by the decoder unit 15 and input to the internal gain control unit 13 and the transimpedance unit 14, and the set value is digitally changed.

  Although the gain also varies by adjusting the feedback resistance of the transimpedance unit 14, the amount of variation is small compared to the adjustment by the internal gain control unit 13. Therefore, by simultaneously controlling the internal gain control unit 13 based on the transmission rate information simultaneously with the control of the transimpedance unit 14, it is possible to suppress the deterioration of the minimum reception sensitivity and secure the optimum frequency band. Also, when the transmission speed of the received signal changes greatly, the minimum receiving sensitivity accompanying it changes greatly, and it becomes difficult to cope with it by controlling a single resistive element with internal gain control and transimpedance control. There is. However, the predetermined resistance value can be changed relatively easily by digitally changing it based on the transmission speed information.

  FIG. 2 is a diagram illustrating a specific configuration example of the internal gain control unit 13 or the transimpedance unit 14. As shown in the figure, the internal gain control unit 13 or the transimpedance unit 14 can be configured based on a plurality of resistance elements, and a plurality of resistors R1, R2, and R3 are connected in series between terminals A and B. Alternatively, these resistors are connected in parallel, and switching elements (for example, field effect transistors) Q1 and Q2 are connected in parallel or in series. Switching elements Q1 and Q2 are controlled to be turned on and off based on transmission rate information. Note that although FIG. 2 shows an example in which three resistance elements and two switching elements are used, a larger number can be formed.

  FIG. 2A shows an example in which R1, R2, and R3 connected in series have Q1 connected in parallel to R1 and Q2 connected in parallel to (R1 + R2). In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B becomes (R1 + R2 + R3). Next, by turning on Q1, R1 is short-circuited, and the resistance between the terminals A and B becomes (R2 + R3). When Q2 is turned on, (R1 + R2) is short-circuited, and the resistance between the terminals A and B is only R3.

  FIG. 2B shows an example in which R1, R2, and R3 connected in series have Q1 connected in parallel to R1 and Q2 connected in parallel to R2. In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B becomes (R1 + R2 + R3) as in the case of FIG. Next, by turning on Q1, R1 is short-circuited, and the resistance between the terminals A and B becomes (R2 + R3). If both Q1 and Q2 are turned on, (R1 + R2) is short-circuited, and the resistance between the terminals A and B is only R3. Further, by turning off Q1 and turning on Q2, only R2 is short-circuited, and the resistance between the terminals A and B can be (R1 + R3).

  FIG. 2C shows an example in which R1, R2, and R3 connected in parallel have Q1 connected in series to R1 and Q2 connected in series to R2. In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B becomes R3. Next, when Q1 is turned on, R1 and R3 are connected in parallel, and the resistance between the terminals A and B is (R1 · R3) / (R1 + R3). If Q1 and Q2 are both turned on, R1, R2 and R3 are connected in parallel, and the resistance between the terminals A and B is (R1 · R3 · R3) / (R1 · R3 + R1 · R2 + R2 · R3). Become. Further, when Q1 is turned off and Q2 is turned on, the resistance between the terminals A and B can be (R2 · R3) / (R2 + R3).

  As described above, the predetermined resistance value can be changed digitally by controlling on / off of Q1 and Q2 by the signal from the decoder unit. In addition, it is desirable that at least one resistor is always selected between the terminals A and B among the plurality of resistors connected in series or in parallel, regardless of whether the switching element is on or off. In FIG. 2, the resistor R3 is always selected.

  By providing this always-selected resistor, it is possible to prevent the transimpedance from becoming zero or infinite even when all the switching elements are turned on or off. Note that a transimpedance type amplifier requires a low input capacitance from the viewpoint of performance with an input of a minute current, and therefore a protective element is not usually included in the input section. Therefore, when there is no feedback resistance, the input impedance becomes a very large value in the power off state, the electrostatic withstand voltage is remarkably reduced and electrostatic breakdown occurs, but by providing a resistance that is always selected, This can be avoided.

  FIG. 3 is a diagram for explaining another embodiment. In the figure, 13 'is an internal gain control unit, 14' is a transimpedance unit, 18 is a signal level detection unit, and the other reference numerals are the same as those used in FIG. In this embodiment, the internal gain control unit 13 ′ and the transimpedance unit 14 ′ are digitally controlled by a signal based on transmission speed information, and are also controlled in an analog manner by a signal level on the amplification output side. .

  The preamplifier shown in FIG. 3 also has a transimpedance unit 14 ′ as a negative feedback resistor, as described in FIG. 1, and converts an optical signal received by the light receiving element 11 such as a PIN photodiode into current-voltage conversion. This is a preamplifier suitable for optical communication. A reception signal based on a signal current generated by light reception from the light receiving element 11 is input to a transistor 12 having a common emitter as an amplifying element. The internal gain of the amplifier is determined by the transistor 12 that is an amplification stage and the internal gain control unit 13 ′ that also serves as the load. Further, the output voltage of the amplification stage is lowered by lowering the output impedance in the buffer stage 16 composed of the next emitter follower circuit or the like. The output of the buffer stage 16 is further input to a main amplification stage (not shown) via an output buffer stage 17.

  The internal gain control unit 13 ′ and the transimpedance unit 14 ′ are simultaneously input with signals related to the transmission rate information of the optical communication from the decoder unit 15 so that the set values of the internal gain and transimpedance of the amplifier can be greatly changed by this signal. I have to. In addition to the signal from the decoder unit 15, the signal level detection unit 18 is provided. For example, the output signal of the output buffer stage 17 is detected, and the signal level is input to the internal gain control unit 13 ′ and the transimpedance unit 14 ′. To be made. The signal level may be an average value of the output signal or a peak value.

  The signal detected by the signal level detection unit 18 is simultaneously input to the internal gain control unit 13 ′ and the transimpedance unit 14 ′, and the internal gain and transimpedance are analogized according to the signal level of the output signal on the amplification output side. Be controlled. In this embodiment, the set values of the internal gain control unit 13 ′ and the transimpedance unit 14 ′ are greatly changed digitally by the signal from the decoder unit 15 and are also controlled by the signal level detection unit 18 in an analog manner. . As a result, even when the transmission rates are greatly different, it is possible to ensure an optimum internal gain, frequency band, and wide dynamic range for each transmission rate.

  FIG. 4 is a diagram illustrating a specific configuration example of the internal gain control unit 13 ′ or the transimpedance unit 14 ′ corresponding to FIG. 3. The internal gain control unit 13 ′ or the transimpedance unit 14 ′ can be configured based on a plurality of resistance elements, and a plurality of resistors R1, R2, R3, R4 are connected in series between terminals A and B. These resistors are connected in parallel, and switching elements (for example, field effect transistors) Q1 and Q2 and controllable variable resistance elements (for example, field effect transistors) Qr are connected in parallel or in series. The switching elements Q1 and Q2 are controlled to be turned on and off based on the transmission speed information, and the variable resistance element Qr is controlled by the signal level on the amplification output side.

  In FIG. 4A, for R1, R2 and R3 connected in series, Q1 is connected in parallel to R1, Q2 is connected in parallel to (R1 + R2), and Qr is connected in parallel to (R1 + R2 + R3). In addition, R4 is connected in series with Qr. In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B is in a state where (Qr + R4) is connected in parallel to (R1 + R2 + R3). Next, when Q1 is turned on, R1 is short-circuited, and the resistance between terminals A and B is in a state where (Qr + R4) is connected in parallel to (R2 + R3). When Q2 is turned on, (R1 + R2) is short-circuited, and the resistance between terminals A and B is in a state where (Qr + R4) is connected in parallel to R3. In each state, Qr is controlled independently, and the resistance between the terminals A and B is adjusted in an analog manner by Qr.

  In FIG. 4B, Q1 is connected in parallel to R1, Q2 is connected in parallel to R2, and Qr is connected in parallel to (R1 + R2 + R3) with respect to R1, R2, and R3 connected in series. This is an example in which R4 is connected in series. In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B is in a state where (Qr + R4) is connected in parallel to (R1 + R2 + R3). Next, when Q1 is turned on, R1 is short-circuited, and the resistance between terminals A and B is in a state where (Qr + R4) is connected in parallel to (R2 + R3). If both Q1 and Q2 are turned on, R1 and R2 are short-circuited, and the resistance between the terminals AB is in a state where (Qr + R4) is connected in parallel to R3. Further, by turning off Q1 and turning on Q2, only R2 is short-circuited, and the resistance between the terminals A and B can be in a state in which (Qr + R4) is connected in parallel to (R1 + R3). In each state, Qr is controlled independently, and the resistance between the terminals A and B is adjusted in an analog manner by Qr.

  FIG. 4C shows an example in which R1, R2, R3, and R4 connected in parallel have Q1 connected in series to R1, Q2 connected in series to R2, and Qr connected in series to R4. is there. In this configuration, for example, if both Q1 and Q2 are turned off, the resistance between the terminals A and B is in a state where R3 and (Qr + R4) are connected in parallel. Next, when Q1 is turned on, R1, R3 and (Qr + R4) are connected in parallel. If Q1 and Q2 are both turned on, R1, R2, R3 and (Qr + R4) are connected in parallel. Further, when Q1 is turned off and Q2 is turned on, the resistance between the terminals A and B is in a state where R2, R3, and (Qr + R4) are connected in parallel. Also in this case, Qr is controlled independently in each state, and the resistance between the terminals A and B is adjusted in an analog manner by Qr.

  As described above, the predetermined resistance value can be changed digitally by controlling on / off of Q1 and Q2 by the signal from the decoder unit. In addition, a variable resistance element Qr that can be controlled by at least one of the plurality of resistors connected in series or in parallel is connected in parallel. The signal level from the signal level detector is added to Qr, and the resistance value is adjusted in an analog manner. As a result, the resistance value set digitally due to the different transmission speeds can be further finely adjusted in an analog manner.

  When a field effect transistor is used for the variable resistance element Qr, the resistance element R4 can be connected in series in order to reduce the gate voltage dependency. This also allows the resistance element R4 to be connected in series so that the resistance value at (Qr + R4) does not become zero. As a result, even if all the switching elements Q1 and Q2 are all turned on or off and the variable resistance element Qr is in a short circuit state with a resistance value of zero, it is possible to avoid the transimpedance from becoming zero.

  FIG. 5 is a diagram simulating the operation state of the configuration example shown in FIG. 4A using a field effect transistor for the variable resistance element Qr. The vertical axis represents the combined resistance between the terminals A and B, and the horizontal axis represents The gate voltage of Qr is shown. As shown in this figure, in the configuration of FIG. 4A, if both Q1 and Q2 are turned off and the gate voltage of Qr is small and no conduction occurs, the resistance between the terminals A and B is ( R1 + R2 + R3) is the maximum and constant. Next, when the gate voltage of Qr becomes a predetermined value or more, conduction occurs between the source and the drain, and the conduction amount gradually increases (resistance value decreases), so that the combined resistance between the terminals A and B is It becomes smaller and attenuates along the curve S. When Qr finally becomes a short-circuited state, R3 and R4 are in a parallel state, and the minimum resistance value is obtained.

  Next, when Q1 is turned on, R1 is short-circuited, and the resistance between the terminals A and B is (R2 + R3) as a maximum value, and the resistance value is constant until Qr starts to conduct. Next, when the gate voltage of Qr becomes equal to or higher than a predetermined value, conduction occurs between the source and the drain, and the resistance value gradually decreases, so that the combined resistance between the terminals A and B decreases. And when it attenuate | damps in the form along the curve S similarly to the above, and Qr finally becomes a short circuit state, it will be in the parallel state of R3 and R4. The same is true when both Q1 and Q2 are on, and the resistance between the terminals AB is constant until Rr is the maximum value and Qr starts to conduct. Next, when the gate voltage of Qr becomes equal to or higher than a predetermined value, conduction occurs between the source and the drain, and the resistance value gradually decreases, so that the combined resistance between the terminals A and B decreases, and R3 and R4 It becomes a parallel state.

It is a block diagram explaining the outline of embodiment of this invention. It is a figure which shows the structural example of an internal gain control part or a transimpedance part. It is a block diagram explaining the outline of other embodiment of this invention. It is a figure which shows the structural example of the internal gain control part or transimpedance part in embodiment of FIG. It is a figure explaining the operation state in the example of a structure of FIG. It is a figure explaining the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Light receiving element, 12 ... Transistor, 13, 13 '... Internal gain control part, 14, 14' ... Transimpedance part, 15 ... Decoder part, 16 ... Buffer stage, 17 ... Output buffer stage, 18 ... Signal level detection part Q1, Q2 ... switching elements, Qr ... variable resistance elements, R1-R4 ... resistors.

Claims (5)

  A preamplifier having an internal gain control unit and a transimpedance unit, comprising a decoder unit for outputting a transmission rate information signal, and the internal gain control unit and the transimpedance unit according to the transmission rate information signal from the decoder unit A preamplifier characterized in that the configuration is controlled.   The internal gain control unit and the transimpedance unit have switching elements connected in parallel or in series to a plurality of resistors connected in parallel or in series, and the resistance value is digitally controlled by turning on / off the switching elements. The preamplifier according to claim 1, wherein the preamplifier is configured.   The preamplifier according to claim 2, wherein at least one resistor among the plurality of resistors connected in series or in parallel is always selected.   A variable resistance element that can be controlled instead of a switching element is connected to at least one of the plurality of resistors connected in series or in parallel, and the resistance value is controlled in an analog manner according to the signal level on the amplification output side. The preamplifier according to claim 2, wherein the preamplifier is configured as follows.   5. The preamplifier according to claim 4, wherein a fixed resistance element is connected in series to the controllable variable resistance element.

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