JP2006060320A - Circuit and method for differential signal driving - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a decrease in output amplitude due to variance of a terminating resistance for a small-amplitude differential signal even when the terminating resistance is incorporated in a receiver side, to eliminate the need to make large the size of a MOS transistor for current-direction changeover switch even when the transistor operates with a low source voltage, to eliminate the need for one extra output port to generate a control signal for a current source, and to eliminate variance of characteristics due to variance of an MOSFET and variance of the terminating resistance RT1. <P>SOLUTION: Disclosed is a small-amplitude differential signal circuit applicable to large variance in terminating resistance value by controlling the current source of an output stage by providing a selecting circuit which selects an output voltage of the differential output signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a differential signal driving circuit and a differential signal driving method for controlling an output stage current source by selecting an output voltage of a small amplitude differential output signal, and in particular, a termination resistor is built in a chip on the receiver side. The present invention relates to a differential signal driving circuit and a differential signal driving method which are configured so as not to cause a problem of variations in termination resistance values generated in the case, and to increase an operation margin when driving a plurality of receivers.

  Conventionally, when image data generated by an image sensor in a mobile phone or a digital camera is transferred to another signal processing chip at a high speed, or in a thin display such as a notebook personal computer or PDA (personal digital assistant), a large amount of image data. Is transferred to a display panel, a small amplitude differential signal interface represented by LVDS (Low Voltage Differential Signal) is used. By reducing the number of digital signals that make up the bus, the system can be reduced in size and weight, and unnecessary radiation (EMI) that affects image quality can be greatly reduced. .

  In the following, focusing on the method for controlling the output amplitude of the differential signal driving circuit and the differential signal driving method of the present invention, the prior art will be broadly classified into three.

  FIGS. 16A and 16B show an outline of the technique disclosed in Patent Document 1 of the conventional small amplitude differential signal driving circuit and the small amplitude differential signal driving method. In FIG. 16A, in a small amplitude differential signal driving circuit (hereinafter referred to as a driver) 1, a predetermined current is applied to an external resistor (hereinafter referred to as REXT) to apply a reference current (hereinafter referred to as a driver). (Referred to as IREF), and a current mirror circuit or the like is used to flow N times the reference current to the current source in the output stage of the driver 1. For example, a terminal current (hereinafter referred to as IOUT) = N · IREF = 3.5 mA flows between the output terminal (hereinafter referred to as DOUT) and the inverting output terminal (hereinafter referred to as XDOUT) of the driver 1. . CMOS level serial data (hereinafter referred to as SD) is input to the driver 1, and when SD is at a high level, a current flows from DOUT to XDOUT through a termination resistor (hereinafter referred to as RT1). Is low level, a current flows from XDOUT to DOUT through RT1. When the value of RT1 of the small amplitude differential signal is 100Ω, an output voltage of 3.5 mA × 100Ω = 350 mV and an average voltage of 1.25 V is generated between DOUT and XDOUT as shown in FIG. To do. The receiver 3 is configured to return a differential signal between DOUT and XDOUT to a CMOS level SD by a differential amplifier or the like.

  FIG. 17 shows a specific circuit diagram of the above-described conventional small amplitude differential signal driver 1. The reference voltage generation circuit 4 generates a constant voltage (hereinafter referred to as VBGR) by a band gap regulator circuit (hereinafter referred to as BGR) or the like. Further, VBGR is multiplied by (R01 + R02) / R01 (R01, 02 are resistors connected to the current source in the reference voltage generating circuit), or the power supply voltage is divided by resistance, for example, a common half of the power supply voltage. A voltage (hereinafter referred to as VCOM) is generated.

  The reference current generating circuit 5 connects an external resistor REXT and a current mirror circuit 6 controlled by an operational amplifier, and applies, for example, the voltage VBGR supplied from the reference voltage generating circuit 4 so that the reference current IREF = VBGR / REXT is generated. A current having the same value as the reference current flows through the NMOS transistor MNC1, and the NMOS transistor MNC1 and the NMOS transistor MNS2 constitute a current mirror circuit 6 having a common gate voltage (hereinafter referred to as VSINK), and the current source on the GND side A current of N · IREF flows through the NMOS transistor MNS1. The NMOS transistor MNC1 and the NMOS transistor MNC2 constitute a current mirror circuit 6a having a common gate voltage VSINK. The NMOS transistor MNC2 has a current (1−α) · IREF slightly smaller than the reference current by adjusting the transistor size. Flows. The current (1-α) · IREF flowing in the NMOS transistor MNC2 is turned back by the PMOS transistor MPC2.

  The PMOS transistor MPC2 and the PMOS transistor MPS3 constitute a current mirror circuit 7 having a common gate voltage (hereinafter referred to as VSOURCE). The current source PMOS transistor MPS3 on the VDD side is slightly smaller than the current flowing through the NMOS transistor MNS1. A current of N · (1-α) · IREF flows. The current source on the VDD side is provided with another PMOS transistor MPS5 for current source using the output of the operational amplifier 8 (hereinafter referred to as VCONT) as a gate voltage in order to control the output voltage near VDD / 2. Yes.

The output stage of the driver 1 is configured by a ground-side NMOS transistor MNS1 for the GND side, two current-source PMOS transistors MPS3 and MPS5 on the VDD side, and switching elements SW1, SW2, SW3, and SW4 that determine the direction of the output current. Has been.
A CMOS level SD is input to the pre-buffer 9. Actually, a synchronization clock signal (hereinafter referred to as CK) and a driver activation / deactivation control signal (hereinafter referred to as OEN) are also input. To do. A signal for controlling ON / OFF of the switching elements SW1, SW2, SW3, and SW4 is output from the pre-buffer 9. Normally, when SD is at a high level, the switching elements SW1 = OFF, SW2 = ON, SW3 = When ON, SW4 = OFF, current flows from DOUT to XDOUT through the termination resistor RT1, and when SD is at a low level, the switching element SW1 = ON, SW2 = OFF, SW3 = OFF, SW4 = ON and the termination resistor A current flows from XDOUT to DOUT through RT1.

  The resistors R1 and R2 generate an intermediate voltage between DOUT and XDOUT (hereinafter referred to as AVE), and the operational amplifier 8 controls the common level of DOUT and XDOUT to a predetermined AVE. The gate voltage of the PMOS transistor MPS5 of the current source on the VDD side is controlled so that the voltages match.

  According to the small-amplitude differential signal driver 1 having the above-described configuration, in a portable information terminal device such as a mobile phone, in order to reduce cost and reduce the size and weight, and to transmit a high-frequency signal, It is beginning to be required to incorporate RT1 in the chip on the receiver side. When the LVDS RT1 is built in the chip on the receiver side, the variation in RT1 (termination resistor) becomes large, and it is necessary to be able to cope with it.

  According to the technique described in Patent Document 1, the current source in the output stage uses a reference current as a current mirror, the output current is determined by REXT that generates the reference current, and the output current is the value of RT1. Regardless of the output voltage, the output voltage is equal to the output current x termination resistance. When RT1 is built in the receiver 3, the RT1 value varies, and when the RT1 value varies, the input amplitude (driver output amplitude) of the receiver 3 also varies. Although the input signal is received by the differential amplifier, the operation speed of the CMOS differential amplifier greatly depends on the input amplitude, and the operation speed becomes slow when the input amplitude becomes small. For this reason, the subject which becomes unable to transmit at high speed has arisen.

  FIG. 18 shows an outline of the technique disclosed in Patent Document 2 of a conventional small amplitude differential signal circuit and a small amplitude differential signal driving method. In FIG. 18, in the driver 1 for a small amplitude differential signal, a lower reference voltage (hereinafter referred to as VOLR) and an upper reference voltage (hereinafter referred to as VOHR) generated in the imitation circuit 10 of the output stage. By controlling the operating voltage of the output stage so as to match, a predetermined output voltage, for example, 350 mV is generated between DOUT and XDOUT of the driver 1. Alternatively, the VSINK of the GND side current source and the VSOURCE of the VDD side current source generated in the mimic circuit 10 are supplied to the current source of the output stage of the driver 1 so that a predetermined output is generated between DOUT and XDOUT of the driver 1. A voltage, for example 350 mV, is generated.

  FIG. 19 shows a specific circuit diagram of the above-described conventional small amplitude differential signal driver 1. The reference current reference voltage generation circuits 4 and 5 are configured by a BGR circuit, an external resistor, a current mirror circuit, an operational amplifier, and the like, and generate IREF. Further, the output stage of the driver 1 that generates VCOM, for example, half of the power supply voltage by multiplying VBGR by (R01 + R02) / R01 or by dividing the power supply voltage by resistance is connected to the NMOS transistor MNS1 of the GND-side current source. It is composed of a PMOS transistor MPS3 as a current source on the VDD side, NMOS transistors MN1 and MN2, and PMOS transistors MP3 and MP4 as switches for determining the direction of output current.

  A CMOS level SD is input to the pre-buffer 9, and in fact, a synchronization CK and a driver activation / deactivation OEN are also input. A signal for controlling ON / OFF of NMOS transistors MN1 and MN2 and PMOS transistors MP3 and MP4 constituting the switch is output from the pre-buffer 9. Normally, when SD is at a high level, MN1 = OFF, MN2 = ON, MP3 = ON, MP4 = OFF, current flows from DOUT to XDOUT through RT1, and when SD is at low level, MN1 = ON, MN2 = OFF, MP3 = OFF, MP4 = ON and RT1 Current flows from XDOUT to DOUT.

  The VCOML for control is output from the common source terminal of the NMOS transistors MN1 and MN2 for low output. A control common signal VCOMH is output from a common source terminal of the high output PMOS transistors MP3 and MP4. If the ON resistances of the NMOS transistors MN1, MN2, and the PMOS transistors MP3, MP4 are sufficiently small as compared with RT1, the voltage of VCOML is almost equal to the voltage on the low level side of the output amplitude, and the voltage of VCOMH is the high level of the output amplitude. It is almost equal to the voltage on the side.

  The imitation circuit 10 includes a transistor having a size of, for example, 1 / N in the output stage and a resistance element having a value N / 2 times that of RT1, and a current 1 / N of the output current flows. The NMOS transistor MNS0 is a dummy of the NMOS transistor MNS1, and the NMOS transistor MND2 is a dummy of the NMOS transistor MN2. Similarly, the PMOS transistor MPD3 is a dummy of the PMOS transistor MP3. The PMOS transistor MPS0 is a dummy of the PMOS transistor MPS3. Resistors RD1 and RD2 are dummy RT1, and RD1 = RD2 = N · RT1 / 2.

  A reference current IREF flows through the PMOS transistor MPC1, and the PMOS transistor MPC1 and the PMOS transistor MPS0 constitute a current mirror circuit 11, and a current of IREF flows through the PMOS transistor MPS0. Resistors RD1 and RD2 generate an intermediate voltage of the mimic circuit 10 (hereinafter referred to as DAVE). The operational amplifier 12 compares DAVE and VCOM, and controls the gate voltage of the NMOS transistor MNS0 of the GND-side current source so that the two voltages match. A lower reference voltage (hereinafter referred to as VOLR) is output from a connection point between the NMOS transistor MNS0 and the NMOS transistor MND2. An upper reference voltage (hereinafter referred to as VOHR) is output from the connection point between the PMOS transistor MPS0 and the PMOS transistor MPD3. The voltage of VOLR is substantially equal to the voltage on the low level side of the output amplitude standard, and the voltage of VOHR is substantially equal to the voltage on the high level side of the output amplitude standard.

  The operational amplifier 13 compares VOLR and VCOML and controls the gate voltage VSINK of the NMOS transistor MNS1 of the GND-side current source so that the two voltages match. The operational amplifier 8 compares VOHR and VCOMH and controls the gate voltage VSOURCE of the PMOS transistor MPS3 of the current source on the VDD side so that the two voltages match. If the value of RT1 is a predetermined value, a current of N · IREF flows through the NMOS transistor MNS1 of the GND-side current source and the PMOS transistor MPS3 of the VDD-side current source.

  In the technique disclosed in Patent Document 1, there is a problem that the output amplitude varies because the output current is controlled to be constant, but according to the technique disclosed in Patent Document 2 described above, Since the reference voltage and the control common signal are controlled by comparing with an operational amplifier, the value of RT1 is not necessarily a constant value, and the ON resistances of the NMOS transistors MN1 and MN2 and PMOS transistors MP3 and MP4 of the switch Is controlled so that the output amplitude becomes a constant voltage even if the value of RT1 varies somewhat. However, since it is necessary to design in consideration of the variation in the process of the MOS transistor of the switch means in addition to the variation of the termination resistor RT1, the transistor sizes of the NMOS transistors MN1, MN2, PMOS transistors MP3, MP4 of the switch means are increased. Therefore, the ON resistance is reduced. Further, in applications of portable devices such as mobile phones, it is required to operate with a power supply voltage as low as twice the threshold value Vth like a sub LVDS circuit for reducing power consumption. In order to make the ON resistances of the NMOS transistors MN1 and MN2 and the PMOS transistors MP3 and MP4 of the switch means small enough to be ignored with a low power supply voltage, a very large transistor is required. When such a very large transistor is used, there arises a problem that reflection tends to occur when the process varies and the driving capability of the MOS transistor increases.

  FIG. 20 shows an outline of the technique disclosed in Patent Document 3 of the conventional small amplitude differential signal driving circuit and the small amplitude differential signal driving method. 20, a driver 1a, a driver 1b,... Driver 1n are provided on the driver circuit 1 side. On the receiver circuit 3 side, a receiver 3a, a receiver 3b,..., A receiver 3n are provided. Terminal resistors RT0, RT1,..., RTn are provided between the differential outputs of the transmission lines 2 of the drivers 1a, 1b,.

  The receiver circuit 3 is not connected to the output of the driver 1a, the input terminals of SD1 to SDn of the driver 1a are fixed to High, and the entire driver 1a operates as the imitation circuit 10. A voltage VOH with an output amplitude of High is output to DOUT0 of the driver 1a, and a voltage VOL with an output amplitude of Low is output to the other XDOUT0. The driver 1a outputs VSINK of the GND-side current source and VSOURCE of the VDD-side current source, and the GND-side current source and the VDD-side current source of the other drivers 1b, 1c,. It is used for control.

  FIG. 21 shows a specific circuit diagram of the above-described conventional small-amplitude differential signal driver 1. The circuit diagram shown in FIG. 21 corresponds to the driver 1a. The difference from the conventional small-amplitude differential signal driver 1 shown in FIG. 19 is that SD is fixed at a high level, MN1 = OFF, MN2 = ON, MP3 = ON, MP4 = OFF, and passes through RT1 to DOUT. A current flows from XDOUT to DD0 of the driver 1a, and a high-side voltage VOH of the output amplitude is always output to the DOUT0 of the driver 1a, and a low-side voltage VOL of the output amplitude is output to the inverting output terminal XDOUT0. In the mimic circuit 10, VOL is output from the connection point between the NMOS transistor MND2 and the resistor RD1, and VOHD is output from the connection point between the PMOS transistor MPD3 and the resistor RD2.

  The operational amplifier 13 controls the gate voltage VSINK of the NMOS transistor MNS1 of the GND-side current source so that the voltages on the VOL and the low-side voltage VOL output to XDOUT0 are equal to each other, and the operational amplifier 8 is the upper VOHD. And the high-side voltage VOH output to DOUT0 are compared, and the gate voltage VSOURCE of the PMOS transistor MPS3 of the VDD-side current source is controlled so that the two voltages coincide with each other.

  FIG. 22 shows a specific circuit diagram of drivers 1b,..., Driver 1n other than driver 1a of driver circuit 1 described in FIG. In FIG. 22, the drivers 1b,..., 1n receive the GND side current source VSINK and the VDD side current source VSOURCE from the driver 1a shown in FIG. The NMOS transistor MNS1 and the PMOS transistor MPS6 of the current source on the VDD side are controlled. The size of the PMOS transistor MPS6 is designed to be slightly smaller than the size of the PMOS transistor MP3 in FIG. 22, and the output voltage VCONT of the operational amplifier 8 is gated to the current source on the VDD side in order to control the output voltage near VDD / 2. Another current source PMOS transistor MPS5 is provided as a voltage.

  In Patent Document 2, control is performed on the terminal resistor RT1 including the ON resistance of the switching transistor. However, according to the configuration of Patent Document 3 described above, the reference voltage and the actual small amplitude differential are controlled. Since the output voltage of the signal itself is controlled by comparing with an operational amplifier, even if the termination resistor RT1 of the small amplitude differential signal varies, it can be controlled so that the voltage at both ends thereof becomes a predetermined voltage. This is a suitable method when a termination resistor is built in the receiver circuit 3 side. However, since an extra output port is required to generate a control signal for the current source, an output port for a small amplitude differential signal. However, there is a problem that it is very wasteful to apply this method to a system with several output ports.

  FIG. 23 shows an outline of the technique disclosed in Patent Document 4 of the conventional small amplitude differential signal driving circuit and the small amplitude differential signal driving method. In FIG. 23, in a system in which signal transmission between CMOS and LSI is performed by a current drive method using a differential signal, the amount of fluctuation of the output differential current signal is reduced, and the amplitude of the transmitted signal is made constant. In order to achieve this, a current source transistor controlled by a non-inverted output D (analog signal) of a differential output and a current source transistor controlled by an inverted output / D (analog signal) are connected in parallel and directly in an analog manner. In addition, a semiconductor integrated circuit is disclosed in which the high level of the differential output is controlled so as not to increase excessively.

  FIG. 23 shows a specific circuit diagram of the above-described conventional small amplitude differential signal driver 1. In FIG. 23, parts corresponding to those of the above-described conventional example are denoted by the same reference numerals and redundant description is omitted, but a semiconductor integrated circuit having an output circuit for outputting a signal with a differential current to the outside from a pair of output terminals. The output circuit includes a pair of differential transistors Q1 and Q2 each having a drain connected to a pair of output terminals and a source connected to each other, and a source and a drain connected to each other in common. And a pair of constant current transistors Q3, Q4 having a common drain connected to a common source of the differential transistors Q1, Q2, and the drain voltages of the pair of differential transistors Q1, Q2 are respectively a pair of constant current transistors Q3. , A semiconductor integrated circuit fed back to the control terminal of Q4 is disclosed. Q5 is a MOSFET for switching.

  Since the driver circuit shown in FIG. 23 is a control method that does not use a reference signal, it is obvious that the characteristics vary to some extent due to variations in MOSFETs and variations in termination resistor RT1 even if the variations are reduced. In particular, at a low power supply voltage, control is performed so that the high level does not rise too much, but since the amplitude is not strictly controlled, there is a problem that the amplitude becomes very small. In the case of feedback through an amplifier, according to FIG. 23, there is provided a differential input differential output type amplifier in which a non-inverted output D and an inverted output / D of differential outputs are input to positive and negative input terminals. Thus, the current source transistor controlled by the non-inverted output of the differential input differential output type amplifier and the current source transistor controlled by the inverted output of the differential input differential output type amplifier are connected in parallel. When the feedback amplifier is designed with realistic current consumption, there is a delay until the output of the feedback amplifier changes after the non-inverted output D and the inverted output / D of the differential output change. If an attempt is made to transmit a signal having a high frequency from MHz to several hundreds of MHz, it takes time for the output voltage to fluctuate and stabilize when the differential output changes, making it difficult to perform the intended operation.

As described above, in the conventional small amplitude differential signal driving circuit described in Patent Document 1, when the termination resistor RT1 of the small amplitude differential signal is built in the receiver 3, the output is caused by the variation of the termination resistor RT1. There is a problem that the operation speed of the differential amplifier on the receiver 3 side becomes slow because the amplitude becomes small. In the conventional small amplitude differential signal driving circuit disclosed in Patent Document 2, the output amplitude is constant at a low power supply voltage. In order to achieve this, there is a problem that the size of the MOS transistor for switching becomes very large. In the conventional small amplitude differential signal driving circuit described in Patent Document 3, the control signal of the current source In the small-amplitude differential signal driving circuit described in Patent Document 4, there is a problem that one extra output port is required to generate Somewhat characteristic resistance RT1 variations will problem arises that vary.
Japanese Patent Laid-Open No. 9-214314 JP 2000-41072 A JP 2000-134082 A JP-A-4-260225

The present invention has been made to solve the above-mentioned problems. The problem to be solved by the present invention is that even if a termination resistor for a small amplitude differential signal is incorporated on the receiver side, the output amplitude is small due to variations in the termination resistance. There is no need to increase the size of the MOS transistor for the current direction changeover switch even when operated with a low power supply voltage, and one extra output port is not required to generate a control signal for the current source. Therefore, an object of the present invention is to provide a differential signal driving circuit and a differential signal driving method in which characteristics do not vary due to variations in MOSFETs and variations in termination resistance RT1.

  According to a first aspect of the present invention, there is provided a selection circuit that selects an output voltage of a differential output signal, a control differential amplifier that uses at least one differential input signal as an output of the selection circuit, and an output of the differential amplifier. A differential signal drive circuit having a small amplitude differential signal source provided with at least one variable current source to be controlled in a current source of an output stage, and a selection circuit for selecting an output voltage is adapted to change a serial data input signal. Of the differential output lines of the two small-amplitude differential signal drive circuits that constantly change, the output line corresponding to the low level of the time signal is serial data to the small-amplitude differential signal drive circuit. The control differential amplifier uses the output of the selection circuit of the output line corresponding to the low level as one of the differential input signals, and the reference voltage on the low level side as well as the differential input signal. And one of Is obtained by the differential signal driver circuit is characterized by providing at least one in the ground side current source in the output stage of the variable current sources controlled by the output of the differential amplifier.

  According to a second aspect of the present invention, a selection circuit that selects an output voltage of a differential output signal, a control differential amplifier that outputs at least one of the differential input signals as an output of the selection circuit, and control by the output of the differential amplifier A low-amplitude differential signal drive circuit having at least one variable current source provided in the output stage current source, and a selection circuit for selecting an output voltage is provided in accordance with a change in the serial data signal. Serial data input to the low-amplitude differential signal drive circuit from among the two differential output lines of the differential-amplifier driver that continues to change, the output line corresponding to the high level from time to time The control differential amplifier uses the output of the selection circuit of the output line corresponding to the high level as one of the differential input signals, and sets the reference voltage on the high level side as the differential input signal. The difference is made with the other one Is obtained by the differential signal driver circuit is characterized by providing at least one in the positive power supply side current source in the output stage of the variable current sources controlled by the output of the amplifier.

  According to a third aspect of the present invention, the output voltage of the differential output signal is selected by the selection circuit, and the selected output is set as at least one of the differential input signals of the differential amplifier, and is controlled by the output of the differential amplifier. A low-amplitude differential signal driving method in which at least one variable current source is provided in the output stage current source, and the selection method for selecting the output voltage always changes as the serial data input signal changes. From among the differential output lines of the two low-amplitude differential signal driving circuits that continue to operate, the output line corresponding to the low level is selected according to the serial data input signal to the small-amplitude differential signal driving circuit. The control differential amplifier uses the output of the output line selected at the low level as one of the differential input signals, and the reference voltage on the low level side as the other of the differential input signals. Dynamic amplifier output Is obtained by the differential signal driver method is characterized by providing at least one variable current source controlled in a ground side current source in the output stage by.

  In the fourth aspect of the present invention, the output voltage of the differential output signal is selected by the selection circuit, and the selected output is set as at least one of the differential input signals of the differential amplifier, and is controlled by the output of the differential amplifier. A low-amplitude differential signal driving method in which at least one variable current source is provided in the output stage current source, and the selection method for selecting the output voltage always changes as the serial data input signal changes. Out of the two differential output lines of the small-amplitude differential signal driving circuit, the output line corresponding to the high level is timed according to the serial data input signal to the small-amplitude differential signal driving circuit. The control differential amplifier uses the output of the output line selected at the high level as one of the differential input signals, and the reference voltage on the high level side as the other one of the differential input signals. Output of the differential amplifier Is obtained by the differential signal driver method is characterized by providing at least one variable current source controlled in a positive power supply side current source in the output stage by.

  According to the differential signal driving circuit and the differential signal driving method of the first to fourth aspects of the present invention, the selection circuit for selecting the output voltage is provided, and a signal very close to the differential output signal itself is extracted and used as the reference voltage. Thus, even if RT1 which is a termination resistor for a small amplitude differential signal is built in the receiver side, the output amplitude does not become small due to variations in termination resistor RT1, and even if it is operated at a low power supply voltage There is no need to increase the size of the MOS transistor for the direction changeover switch, and no extra output port is required to generate a control signal for the current source. In addition, a sufficient operating margin can be obtained even when a plurality of receivers are driven or when various termination methods are mixed. Also, even when operating at a high bit rate close to the limit, the output amplitude does not decrease, that is, not only the high level does not rise too much at a low power supply voltage, but also the amplitude control is strictly As a result, a small-amplitude differential signal drive circuit can be realized in which the amplitude does not become very small.

  A small amplitude differential signal driving circuit and an actuation signal driving method according to the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram (I) of a small amplitude differential signal driving circuit showing an embodiment of the present invention, and FIG. 2 is a principle diagram of an output voltage selection circuit used in the small amplitude differential signal driving circuit of the present invention. FIG. 3 is a circuit diagram and logic table showing an embodiment of an output voltage selection circuit used in the differential signal driving circuit with a small amplitude of the present invention, and FIG. 4 is another embodiment of the present invention. FIG. 5 is a principle diagram, waveform diagram and logic table of an output voltage selection circuit used in the small amplitude differential signal driving circuit of the present invention. FIG. FIG. 7 is a circuit diagram and a logic table showing an example of an output voltage selection circuit used in a differential signal driving circuit with a small amplitude of the invention, and FIG. 7 shows still another example of a differential signal driving circuit with a small amplitude of the invention. Circuit diagrams (III) and 8 are circuit diagrams (IV) showing still another embodiment of the small-amplitude differential signal driving circuit of the present invention. FIG. 9 is a circuit diagram (I) showing an application example of the small amplitude differential signal driving circuit of the present invention, and FIG. 10 is a circuit diagram showing still another embodiment of the small amplitude differential signal driving circuit of the present invention. (V), FIG. 11 is a circuit diagram of a selection circuit used in FIG. 10, FIG. 12 is a circuit diagram (II) showing an application example of a small amplitude differential signal driving circuit of the present invention, and FIG. 13 is a small amplitude of the present invention. FIG. 14 is a circuit diagram (III) showing still another embodiment of the output voltage selection circuit used in the differential signal driving circuit of FIG. 14, and FIG. 14 is a circuit diagram (III) showing an application example of the small amplitude differential signal driving circuit of the present invention. FIG. 15 is an output voltage waveform diagram used in the small amplitude differential signal driving circuit of the present invention. In the following description, parts corresponding to those in FIGS. 16 to 23 are denoted by the same reference numerals.

  FIG. 1 shows an example of a small amplitude differential signal driving circuit 1 according to the present invention. In FIG. 1, the reference voltage generation circuit 4 generates a common voltage VCOM that is half the power supply voltage by, for example, dividing the power supply voltage by resistance. Further, VCOM is further divided by resistance to generate a lower reference voltage VREFL. Control is performed based on VCOM and the lower reference voltage VREFL. (If the BGR circuit is used, a highly accurate reference voltage can be generated, but a voltage of about 3 × VF is required as the power supply voltage, so it is not suitable for lowering the voltage.) VCOM from the output of this reference voltage generating circuit 4 Is supplied to the inverting input terminal of the operational amplifier 8 and the VREFL output is supplied to the inverting input terminal of the operational amplifier 13.

  An intermediate voltage AVE between DOUT and XDOUT is supplied to the non-inverting input terminal of the operational amplifier 8, and the low-side voltage VMONL of the differential output signal from the output voltage selection circuit 15 is input to the non-inverting input terminal of the operational amplifier 13. The control voltage VSOURCE from the output of the operational amplifier 8 controls the IS3 of the variable current source on the VDD side, and the control voltage VSINK from the output of the operational amplifier 13 controls the IS1 of the variable current source on the GND side.

  The output stage of the driver is composed of GND-side current sources IS1,..., IS2 and VDD-side current sources IS3,..., IS4 and switching elements SW1, SW2, SW3, SW4 that determine the direction of the output current. ing. IS1 and IS3 are variable current sources for controlling the output amplitude to a predetermined voltage. IS2 and IS4 are current sources having a small startup current capability. One end of IS3 and IS4 is connected to VDD, and the other end. Are connected to SW3 and SW4, respectively, and the other end of SW3 is connected to one end of DOUT and dividing resistor R2 and one end of SW1. The other end of SW4 is connected to the other end of resistor R1 connected in series with XDOUT and resistor R2, and one end of SW2. The other ends of SW1 and SW2 are respectively connected to one ends of IS1 and IS2, and the other ends of IS1 and IS2 are respectively connected to the ground potential GND. The other ends of SW1 and SW2 are connected to each other, and the other ends of SW3 and SW4 are connected to each other. The intermediate voltage AVE extracted from the connection middle point of the resistors R2 and R1 is supplied to the non-inverting input terminal of the operational amplifier 8, and the output voltages of DOUT and XDOUT are supplied to the input terminal of the output voltage selection circuit 15.

  The pre-buffer 9 receives CMOS level serial data SD, and actually receives a clock signal CK for synchronization and a control signal OEN for driver activation / deactivation. A signal for controlling ON / OFF of SW1, SW2, SW3, SW4 is output from the pre-buffer 9, and normally, when SD is at a high level, SW1 = OFF, SW2 = ON, SW3 = ON, SW4 = OFF, current flows from DOUT to XDOUT through the termination resistor RT1, and when SD is at a low level, the switching element SW1 = ON, SW2 = OFF, SW3 = OFF, SW4 = ON and the termination resistor RT1. Current flows from XDOUT to DOUT. The pre-buffer 9 also supplies a signal for controlling ON / OFF of SW11 and SW12, which will be described later, generated from SD or SD to the output voltage selection circuit 15.

  The output voltage selection circuit 15 reduces the output line corresponding to the low level from time to time among the differential output lines of the two small-amplitude differential signal driving circuits that constantly change as the serial data signal SD changes. This is a circuit that selects in accordance with the serial data input signal SD to the amplitude differential signal drive circuit, and outputs the low-side voltage VMONL of the differential output signal. The operational amplifier 13 compares the output voltage VMMONL of the output voltage selection circuit 15 with the reference voltage VREFL, and controls the GND-side variable current source IS1 with the control voltage VSINK from the output of the operational amplifier 13 so that the two voltages match. To do.

  The resistors R1 and R2 generate an intermediate voltage AVE between DOUT and XDOUT, and the operational amplifier 8 controls the common voltage VCOM by comparing the intermediate voltage AVE and the common voltage VCOM in order to control the common level of DOUT and XDOUT to a predetermined intermediate voltage. The variable current source IS3 on the VDD side is controlled by the control voltage VSOURCE so that the voltages match.

  2A, 2B, and 2C show a first embodiment of the output voltage selection circuit 15 of the present invention. As shown in FIG. 2A, the output voltage selection circuit 15 includes at least a switch element SW11 provided between the output signal DOUT of the small amplitude differential signal drive circuit (driver) 1 and the output voltage VMONL on the low side. The switching element SW12 is provided between the inverted output signal XDOUT of the driver 1 and the low-side output voltage VMONL. As shown in the logic table of FIG. 2C and the waveform diagram of FIG. 2B, the switch elements SW11 and SW12 are controlled by the serial data input signal SD of the driver 1 for small amplitude differential signal, and serial From among the two differential output lines DOUT and XDOUT of the driver for the small amplitude differential signal that constantly changes in accordance with the change of the data signal SD, the output line corresponding to the low level is selected at the low time and the Low side Output voltage VMONL.

  3A and 3B show specific circuit configurations of the output voltage selection circuit of the present invention. As shown in FIG. 3A, the output voltage selection circuit 15 includes at least an NMOS constituting a switch element provided between the output signal DOUT of the driver 1 for small amplitude differential signal and the output voltage VMONL on the low side. A transistor MN11, a PMOS transistor MP11, and an NMOS transistor MN12 and a PMOS transistor MP12 that constitute a switch element provided between the inverted output signal XDOUT of the driver 1 for small amplitude differential signal and the low-side output voltage VMMONL. ing. The NMOS transistor MN11 and the PMOS transistor MP11 and the NMOS transistor MN12 and the PMOS transistor MP12 are connected in parallel to each other, and a signal for controlling ON / OFF of the switch element generated from the SD is supplied to each gate.

  The NMOS transistor MN11, the PMOS transistor MP11, the NMOS transistor MN12, and the PMOS transistor MP12 constituting the switch elements SW11, XSW11, SW12, and XSW12 are controlled by the serial data input signal SD of the driver 1 for small amplitude differential signals, and serially controlled. From among the two differential output lines DOUT and XDOUT of the driver 1 for small-amplitude differential signals that constantly change with the change of the data signal SD, an output line corresponding to the low level is selected and timed. The output voltage VMONL is output as shown in the logic table of FIG. Since the output level is selected by using the digital signal on the input side and the low level is extracted, it is possible to transmit signals of several tens to several hundreds of MHz, and the ON / OFF of the switch element is controlled. It is possible to cope with a case where a signal exceeding 1 GHz is transmitted by adjusting the timing of the signal. Further, DC power consumption like an analog circuit is not required.

  Resistors R11 and R12 provided between the differential output lines DOUT and XDOUT and the switch are provided as a resistor for the electrostatic discharge protection and for the low-pass filter, and the output voltage VMONL on the switch and the low side is provided. A π-type resistor R13 and capacitors C11 and C12 provided between the resistors R11 and R12 form a low-pass filter (LPF) including the resistors R11 and R12, and output VMONL with a smooth waveform.

  FIG. 4 shows a second embodiment of a differential signal driving circuit having a small amplitude according to the present invention. 4 is different from the first embodiment shown in FIG. 1 in that the control method is reversed upside down with respect to the power supply voltages VDD and GND. The reference voltage generation circuit 4 generates an upper reference voltage VREFH, and performs control based on the common voltage VCOM and the upper reference voltage VREFH. The output voltage selection circuit 15 outputs a high-side voltage VMONH of the differential output signal.

  Since the operational amplifier 13 controls the common level of DOUT and XDOUT to a predetermined intermediate voltage, the intermediate voltage AVE and the common voltage VCOM are compared, and the variable current source on the GND side is controlled by the control voltage VSINK so that the two voltages coincide with each other. The operational amplifier 8 compares the output voltage VMONH of the output selection circuit 15 with the reference voltage VREFH, and controls the variable current source IS3 on the VDD side with the control voltage VSOURCE so that the two voltages match. Since the other points are the same as in FIG.

  5A, 5B, and 5C show a second embodiment of the output voltage selection circuit 15 of the present invention. As shown in FIG. 5A, the output voltage selection circuit 15 includes at least a switch element SW11 provided between the output signal DOUT of the driver 1 for small amplitude differential signal and the output voltage VMONH on the high side. The switching element SW12 is provided between the inverted output signal XDOUT of the driver for the amplitude differential signal and the output voltage VMONH on the High side.

  As shown in the logic table of FIG. 5C and the waveform diagram of FIG. 5B, the switch elements SW11 and SW12 are controlled by the serial data input signal SD of the driver 1 for small amplitude differential signals, From among the two differential output lines DOUT and XDOUT of the driver 1 for small amplitude differential signals that constantly change with the change of the serial data signal SD, an output line corresponding to the high level is selected. And output as a high-side output voltage VMONH.

  6A and 6B show a second circuit configuration example of the output voltage selection circuit 15 of the present invention. The output voltage selection circuit 15 includes at least an NMOS transistor MN11 and a PMOS transistor MP11 that constitute switch elements SW11 and XSW11 provided between the output signal DOUT of the driver 1 for a small amplitude differential signal and the output voltage VMONH on the High side. And an NMOS transistor MN12 and a PMOS transistor MP12 constituting switch elements SW12 and XSW12 provided between the inverted output signal XDOUT of the driver for the small amplitude differential signal and the output voltage VMONH on the High side. The NMOS transistor MN11 and the PMOS transistor MP11 and the NMOS transistor MN12 and the PMOS transistor MP12 are connected in parallel to each other, and a signal for controlling ON / OFF of the switch element generated from the SD is supplied to each gate.

  The NMOS transistor MN11, the PMOS transistor MP11 and the NMOS transistor MN12, and the PMOS transistor MP12 constituting the switch elements SW11, XSW11, SW12XSW12 are controlled by the serial data input signal SD of the driver 1 for small amplitude differential signal, and the serial data signal From among the two differential output lines DOUT and XDOUT of the driver 1 for small-amplitude differential signals that constantly change with the change of SD, the output line corresponding to the high level is selected at the high time and the High side The output voltage VMONH is output as shown in the logic table of FIG. Since the output line is selected using the digital signal on the input side and a high level is extracted, it can be used when transmitting signals of several tens to several hundreds of MHz, and the switch elements are controlled on / off. It is possible to cope with the case of transmitting a signal exceeding 1 GHz by adjusting the timing of the signal to be transmitted. Further, DC power consumption like an analog circuit is not required.

  Resistors R11 and R12 provided between the differential output lines DOUT, XDOUT and the switch elements SW11, XSW11, SW12, XSW12 are provided for electrostatic breakdown protection and as resistors for the low-pass filter, Each of the switch elements SW11 and XSW11, SW12 and XSW12, and the π-type resistor R13 and capacitors C11 and C12 provided between the high-side output voltage VMONH constitute a low-pass filter (LPF) including the resistors R11 and R12. A smooth waveform is output to the operational amplifier 8.

  FIG. 7 shows another third embodiment of the small amplitude differential signal driving circuit of the present invention. 7 differs from the first and second embodiments shown in FIG. 1 and FIG. 2 in that a reference voltage generating circuit 4 generates a lower reference voltage VREFL and an upper reference voltage VREFH. This is the point of control. The output voltage selection circuit 15 is provided with both the circuits shown in FIGS. 3 and 6, for example, and outputs both the low-side voltage VMONL and the high-side voltage VMONH of the differential output signal. It is made to supply to.

  The operational amplifier 13 compares the low-side output voltage VMONL of the output selection circuit 15 with the reference voltage VREFL, and controls the GND-side variable current source IS1 with the control voltage VSINK so that the two voltages coincide with each other. Compares the output voltage VMONH on the High side of the output selection circuit 15 with the reference voltage VREFH and controls the IS3 of the variable current source on the VDD side with the control voltage VSOURCE so that the two voltages coincide with each other.

  The first, second, and third embodiments of the small amplitude differential signal driver 1 of the present invention described above are completely different from the conventional small amplitude differential signal driver in that the output voltage selection circuit 15 is The signals VMONL and VMONH that are provided and are very close to the differential output signal itself are taken out and compared with the reference voltage as indicated by the phantom lines in FIGS. 2B and 5B.

  FIG. 8 shows a fourth embodiment of the small amplitude differential signal driving circuit provided with the output voltage selection circuit of the present invention. In FIG. 8, the reference voltage generation circuit 4 generates a common voltage VCOM that is half the power supply voltage VDD by, for example, dividing the power supply voltage by resistance, and further divides the VCOM by resistance to obtain a lower reference. A voltage VREFL is generated, and the operational amplifiers 8 and 13 are controlled based on the common voltage VCOM and the lower reference voltage VREFL.

  The output stage of the driver 1 includes NMOS transistors MNS1 and MNS2 as GND-side current sources, PMOS transistors MPS3 and MPS4 as VDD-side current sources, and NMOS transistors MN1 and MN2 and PMOS transistors MP3 and MP4 as switches that determine the direction of output current. It is constituted by. The NMOS transistor MN1 and the PMOS transistor MP3 are variable current sources for controlling the output amplitude to a predetermined voltage, and the NMOS transistor MN2 and the PMOS transistor MP4 are current sources having a small startup current capability.

  The pre-buffer 9 receives CMOS level serial data SD, and actually receives a clock signal CK for synchronization and a control signal OEN for driver activation / deactivation. Signals that control ON / OFF of MN1, MN2, and PMOS transistors MP3, MP4 are output. Normally, when SD is at a high level, MN1 = OFF, MN2 = ON, MP3 = ON, MP4 = OFF When a current flows from DOUT to XDOUT through the termination resistor RT1 and SD is at a low level, MN1 = ON, MN2 = OFF, MP3 = OFF, MP4 = ON, and the termination resistor RT1 passes through the termination resistor RT1 to XDOUT. Current flows.

  A differential output is provided between the connection point DO of the PMOS transistor MP3 and the NMOS transistor MN1 and the output terminal DOUT and between the connection point XDO of the PMOS transistor MP4 and the NMOS transistor MN2 and the inverted output terminal XDOUT for electrostatic breakdown protection. In order to limit current when the lines are short-circuited, resistors RE2 and RE1 each having a value that is a fraction of the termination resistor RT1 are provided to reduce reflection when used at a relatively high power supply voltage VDD.

  The output voltage monitor circuit applies the differential output signals of the two small-amplitude differential signal drivers 1 that constantly change as the serial data signal changes through the connection points DO and XDO, and corresponds to the low level from time to time. The output line to be selected is selected according to the serial data input signal SD to the small amplitude differential signal circuit, and outputs the low-side voltage VMMONL of the differential output signal.

  The operational amplifier 13 compares the output voltage VMONL of the output voltage drive circuit 15 with the reference voltage VREFL, and sets the variable current source MNS1 on the GND side with the control voltage VSINK through the low-pass filter LPF1 so that both voltages match. Control. A capacitor C1 connected between the LPF1 and the gate of the current source MNS2 is a phase compensation capacitor for stabilizing the feedback loop. The capacitor C1 is connected in series with the NMOS transistor MN2, and one end of the MNS2 is grounded to GND. Yes. Similarly, the NMOS transistor MNS1 and the NMOS transistor MNI are connected in series, and one end of the MNS1 is grounded to GND.

  The dividing resistors R1 and R2 generate an intermediate voltage AVE between DOUT and XDOUT, and are supplied to the non-inverting input terminal of the operational amplifier 8 through the low pass filter LPF2. The operational amplifier 8 controls the common level of the connection points DO and XDO to a predetermined intermediate voltage. Therefore, the operational voltage 8 compares the intermediate voltage AVE and the common voltage VCOM so that the two voltages coincide with each other. Thus, the MPS 3 of the variable current source on the VDD side is controlled. The presence of the resistor R3 and the capacitor C3 constitutes a lag lead filter. A capacitor C2 connected between the lag lead filter and the gate of the current source MPS4 is a phase compensation capacitor for stabilizing the feedback loop, and is connected in series with the PMOS transistor MP4. One end of the MPS4 is set to VDD. It is connected. Similarly, the PMOS transistor MPS3 and the PMOS transistor MP3 are connected in series, and one end of the MPS3 is connected to VDD. The gates of MPS 4 and MNS 2 are connected.

  FIG. 9 shows a first application example of the small amplitude differential signal driving circuit of the present invention. The small-amplitude differential signal driver 1 provided with the output voltage selection circuit 15 of the present invention drives N receivers 3a, 3b,..., 3n of the same type having built-in termination resistors via the transmission line 2. . Both the driver 1 and the receiver 3 are designed for a specific system, and the resistance element in the reference voltage generation circuit 4 of the driver 1 and the termination resistors RT1, RT2,..., RTn built in the receiver 3 have the same characteristics. It is assumed that it is formed of a resistance element.

  In this example, the voltages at the connection points DO and XDO shown in FIG. 8 are selected without directly selecting the voltages at the output terminal DOUT and the inverted output terminal XDOUT. If the number of receivers 3 that must be driven in advance is known to be N, and there is no need to consider variations in the values of the termination resistors RT1, RT2,..., RTn, the values of the resistors RE1 and RE2 are set. If the reference voltage VREFL corresponding to the added (RT1 / N + RE1 + RE2) is generated, there is no problem. Even if such control is performed, control is performed in a form including the ON resistance of the current changeover switch in the supply capability of the current source. Therefore, there is an advantage that the transistor size of the current changeover switch does not need to be very large even in a low power supply voltage application.

  FIG. 10 shows a fifth embodiment of the small amplitude differential signal drive circuit (driver 1) provided with the output voltage selection circuit 15 of the present invention. In FIG. 10, the voltage of the output terminal DOUT and the inverted output terminal XDOUT is directly selected. Thereby, even if the termination resistor RT1 is built in the receiver side and the resistance value varies, a predetermined output amplitude can be obtained.

  In this example, a selection circuit 16a and a selection circuit 16b are provided to make the current supply capacity variable so that it can cope with a case where a plurality of receivers are driven or various termination methods are mixed. Which of the plurality of NMOS transistors MNS10, MNS11, MNS12,... Of the current source provided on the side and the plurality of NMOS transistors MPS30, MPS31, MPS32,. By setting whether to activate, the current supply capability can be selected by the selection circuits 16a and 16b. The output VSN2 of the selection circuit 16a is directly supplied to the gate of the NMS12 on the GND side, and controls the gate of the MNS2 through the capacitor C4. or. The output VSP2 of the selection circuit 16b is directly supplied to the gate of the NMP 32 on the GND side, and controls the gate of the MPS 4 via the capacitor C5. The MNS 10 and the MPS 30 are supplied with VSINK and VSOURCE from the operational amplifiers 13 and 8. This control signal is also supplied to the inputs of the selection circuits 16a and 16b. The input method to the operational amplifiers 13 and 8 is the same as that in FIG. 1, and the configuration of the output unit is the same as that in FIG. 8 except that there are a plurality of current source configurations.

  Specific circuit configurations of the above-described selection circuits 16a and 16b are shown in FIGS. 11A, the selection circuits 16a and 16b have MP31 and MN31, MP32 and MN32, MP41 and MN41, and MP42 and MN42 as switch elements similar to those described in FIGS. .

  Control signals XSL1 and SL1 are supplied to the gates of MP31 and MN31 connected in parallel in the selection circuit 16a, and VSNK is supplied to one end of MP31 and MN31 connected in parallel, and the control signal VSN1 is output from the other end. It is given to the gate of the MNS 11 shown in FIG.

  Similarly, control signals XSL2 and SL2 are supplied to the gates of MP32 and MN32 connected in parallel in the selection circuit 16a, and VSNK is supplied to one end of MP32 and MN32 connected in parallel, and the control signal VSN2 is output from the other end. And supplied to the gate of the MNS 12 shown in FIG.

The above-described selection gate control signals SL1, XSL1, SL2, and XSL2 obtain control signals XSL1 and XSL2 that are inverted by the selection signals SEL1 and SEL2 supplied to the inverters INV1 and INV3 as shown in FIG. The control signals XSL1 and XSL2 are supplied to the inverters INV2 and INV4, and selection gate control signals SL1 and SL2 are obtained from the inverters INV2 and INV4.

  Control signals XSL1 and SL1 are supplied to the gates of MP41 and MN41 connected in parallel in the selection circuit 16b, VSOURCE is supplied to one end of MP41 and MN41 connected in parallel, and the control signal VSP1 is output from the other end. This is given to the gate of the MPS 31 for the current source on the VDD side.

  Similarly, control signals XSL2 and SL2 are supplied to the gates of MP42 and MN42 connected in parallel in the selection circuit 16b, and VSOURCE is supplied to one end of MP42 and MN42 connected in parallel, and the control signal VSP2 is output from the other end. And supplied to the gate of the current source MPS 32 on the VDD side.

  The above-described selection gate control signals SL1, XSL1, SL2, and XSL2 obtain control signals XSL1 and XSL2 that are inverted by the selection signals SEL1 and SEL2 supplied to the inverters INV1 and INV3. The control signals XSL1 and XSL2 are supplied to the inverters INV2 and INV4, and selection gate control signals SL1 and SL2 are obtained from the inverters INV2 and INV4.

  FIG. 12 shows a second application example of the small amplitude differential signal driving circuit of the present invention. The signal of the small-amplitude differential signal driver 1 provided with the output voltage selection circuit 15 of the present invention is transmitted to the receiver circuit 3 via the transmission line 2, and the receiver circuit 3 has a termination resistor RT 1 as an external receiver. 3a, a certain type of receiver 3b using a MOSFET incorporating termination resistors RTia and RTib as a resistor,..., For example, a receiver 3n incorporating termination resistors RTna and RTn are driven. Since the length of the transmission line 2 is relatively long, termination resistors RT1, RTia, RTib, RTna, RTnb are provided to prevent reflection on the driver 1 side.

  If an optimum current supply capability is set in advance and driven by the driver 1 provided with the output voltage selection circuit 15, the receiver circuit 3 having a plurality of receivers 3a to 3n is driven and various termination methods are mixed. Even in this case, a sufficient operation margin can be obtained.

  FIG. 13 shows a sixth embodiment of a small amplitude differential signal drive circuit provided with the output voltage selection circuit of the present invention. 13 differs from the conventional small amplitude differential signal driving circuit shown in FIG. 22 in that the present invention is provided with an output voltage selection circuit 15 to fix the serial input data of the driver 1 high. Absent. That is, the voltages DOUT and XDOUT are input to the output voltage selection circuit 15 and the output VMONL is supplied to the non-inverting input terminal of the operational amplifier 13.

  FIG. 14 shows a third application example of the small amplitude differential signal driving circuit of the present invention. The driver 1 and the receiver 3 have a plurality of ports for small amplitude differential signals. A driver 1a, a driver 1b,..., A driver 1n are provided on the driver circuit 1 side. On the receiver circuit 3 side, a receiver 3a, a receiver 3b,..., A receiver 3n are provided. Terminating resistors RT0, RT1,..., RTn are provided between the differential outputs of the drivers 3a to 3n.

  From the driver 1a to which the clock CLK is input, the control voltage VSINK of the GND-side current source and the control voltage VSOURCE of the VDD-side current source are output, and the GND of the other driver 1b, driver 1c,. Is used to control the current source on the side and the current source on the VDD side. The difference from the conventional small-amplitude differential signal driving circuit shown in FIG. 20 is that it is not necessary to use the entire driver as a mimic circuit. Not requiring extra power consumption is important in fields where power consumption is a problem, such as portable devices. In addition, the generation of a control voltage using the driver 1a to which the clock CLK that is constantly changing every half cycle or every cycle is input means that the width of 1 bit in the continuous “0” data at other driver outputs. This means that the control is performed so that a differential output signal such as “1” data which is easily crushed also has a proper output amplitude.

  FIG. 15A shows an output waveform of the differential signal driving circuit with a small amplitude of the present invention, and FIG. 15B shows a comparison of output waveforms of the conventional differential signal driving circuit with a small amplitude. FIGS. 15A and 15B show the case where the left side is a low bit rate and the right side is a high bit rate.

  In the case of a low bit rate, both the small amplitude differential signal driving circuit of the present invention and the conventional small amplitude differential signal driving circuit can obtain output amplitudes close to the reference voltages VOHD and VOLD. Considering that, since the conventional low-amplitude differential signal driving control circuit does not use the output voltages DOUT and XDOUT itself for control, when the bit rate becomes very high, the waveform on the right side of FIG. The output amplitude gradually decreases, and there arises a problem that it becomes difficult to normally operate the receiver circuit 3 side.

  However, in the differential signal driving circuit of the small amplitude of the present invention, the output voltages DOUT and XDOUT themselves are used for control, and the average value of the waveform below VCOM is the waveform of the waveform above the lower control signals VMONL and VCOM. Since the control is performed by outputting the average value as the upper control signal VMONH from the output voltage selection circuit, the output amplitude gradually increases in order to maintain the effective amplitude even when the bit rate is very high. The operation on the receiver circuit 3 side is not as difficult as the conventional small amplitude differential signal driving circuit. Therefore, the present invention is a very effective means in the field where data must be transferred at a low power supply voltage and a high bit rate.

In the present invention, a constantly changing signal called a differential output signal is used for control, and it is desirable to use an LPF in order to stably use the signal as shown in FIG. In addition, by using the present invention, it becomes easy to realize a small amplitude differential signal driving circuit that operates even with a low power supply voltage. However, when operated with a low power supply voltage, a BGR circuit or a current mirror circuit that regulates the power supply voltage. Therefore, it is difficult to use the reference voltage generator, and the control using the reference voltage generation circuit of the resistance division and the differential amplifier is performed. If the power consumption is reduced by reducing the DC current of the control differential amplifier, it is necessary to accurately perform AC feedback with a phase compensation capacitor. For this reason, a process having a high-capacitance element option is selected, or a control voltage generation circuit as shown in FIG. 14 has a plurality of drivers required for only one of a plurality of output ports. It is preferably applied to a differential signal driving circuit. Also, since LPF is inserted when feedback from the output, it takes more time than the prior art to stabilize after power-on, so it can be applied to systems with transmission line length up to about several tens of centimeters. preferable.
If the high-level selection circuit shown in FIG. 5 is applied to the conventional small amplitude differential signal driving circuit shown in FIG. 23 by applying the concept of the present invention, the output voltage control for Q3 and Q4 is performed. It is possible to obtain stable operating characteristics even at a high frequency by using only the constant current transistor Q3 and supplying the output voltage of the selection circuit on the high level side to the gate of Q3. In the description of the present invention, the transmission circuit in the case where the driver and the receiver are separate chips has been described. However, it goes without saying that the present invention can also be applied to a bidirectional transmission circuit in which the driver and the receiver are provided in each chip. There is no.

  According to the present invention, a termination resistor for a small-amplitude differential signal is built in the receiver side by providing a selection circuit for the output voltage, extracting a signal very close to the differential output signal itself, and performing comparison control with the reference voltage. Even if it is operated with a low power supply voltage, it is not necessary to increase the size of the MOS transistor for the current direction changeover switch, and a control signal for the current source is generated. Therefore, a small amplitude differential signal circuit that does not require one extra output port can be realized. In addition, a sufficient operating margin can be obtained even when a plurality of receivers are driven or when various termination methods are mixed. Furthermore, there can be obtained a differential signal driving circuit and a differential signal driving method in which the output amplitude does not become small even when operated at a high bit rate close to the limit.

  In the above description, the driver circuit 1 on the transmission side and the receiver circuit 3 on the reception side are separately provided. However, the present invention can also be applied to an input / output device in which both the driver circuit 1 and the receiver circuit 3 for small amplitude differential signals are provided. The present invention can also be applied to a driver for driving a termination resistor RT1 formed of a transistor having a bias voltage input to the gate.

1 is a circuit diagram (I) of a small amplitude differential signal driving circuit showing one embodiment of the present invention. It is a principle diagram, a waveform diagram, and a logic table of an output voltage selection circuit used in the differential signal drive circuit with a small amplitude of the present invention. 2 is a circuit diagram and a logic table showing an example of an output voltage selection circuit used in a differential signal driving circuit with a small amplitude according to the present invention. FIG. It is a differential signal drive circuit diagram (II) of the small amplitude which shows another one example of this invention. It is a principle diagram, a waveform diagram, and a logic table of an output voltage selection circuit used in the differential signal drive circuit with a small amplitude of the present invention. 2 is a circuit diagram and a logic table showing an example of an output voltage selection circuit used in a differential signal driving circuit with a small amplitude according to the present invention. FIG. It is a circuit diagram (III) which shows further another example of the differential signal drive circuit of the small amplitude of this invention. FIG. 14 is a circuit diagram (IV) showing still another embodiment of the small amplitude differential signal driving circuit of the present invention. FIG. 5 is a circuit diagram (I) showing an application example of the differential signal drive circuit with small amplitude according to the present invention. FIG. 10 is a circuit diagram (V) showing still another embodiment of the differential signal driving circuit with small amplitude according to the present invention. It is a circuit diagram of the selection circuit of the output current capability used for FIG. It is a circuit diagram (II) which shows the application example of the differential signal drive circuit of the small amplitude of this invention. It is a circuit diagram (VI) which shows further another example of the output voltage selection circuit used for the differential signal drive circuit of the small amplitude of this invention. It is a circuit diagram (III) which shows the application example of the differential signal drive circuit of the small amplitude of this invention. (A) is an output voltage waveform diagram used in the differential signal drive circuit with a small amplitude of the present invention, and (B) is an output voltage waveform diagram used in a conventional differential signal drive circuit with a small amplitude. It is a systematic diagram which shows an example of the system of the conventional differential signal drive circuit of a small amplitude. It is a circuit diagram which shows an example of the conventional differential signal drive circuit of a small amplitude. It is a systematic diagram which shows the other example of the system which used the imitation circuit for the conventional differential signal drive circuit of the small amplitude. It is a circuit diagram which shows the other example of the conventional differential signal drive circuit of a small amplitude. It is a systematic diagram (I) which shows another example of the system of the conventional differential signal drive circuit of a small amplitude. It is a circuit diagram which shows the further another example of the conventional differential signal drive circuit of a small amplitude. It is a circuit diagram which shows the other structure of the output part of a driver. It is a systematic diagram (II) which shows an example of the system of the conventional differential signal drive circuit of a small amplitude.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Driver circuit, 2 ... Transmission line, 3 ... Receiver circuit, 4 ... Reference voltage generation circuit, 5 ... Reference current generation circuit, 6, 6a, 7 ... Current Mirror circuit, 8, 13... Operational amplifier, 9... Prebuffer, 15... Output voltage selection circuit, 16a, 16b... Output current capability selection circuit, IS1 to IS4. ~ SW4 ... switch element, RT1 ..., termination resistor

Claims (9)

A selection circuit for selecting an output voltage of the differential output signal;
A differential amplifier for control in which the output of the selection circuit is at least one of differential input signals;
A small-amplitude differential signal drive circuit provided with at least one variable current source controlled by the output of the differential amplifier in the current source of the output stage;
The selection circuit for selecting the output voltage corresponds to the low level from time to time among the differential output lines of the two small-amplitude differential signal driving circuits that constantly change as the serial data input signal changes. The output line to be selected is selected according to the serial data input signal to the small amplitude differential signal circuit,
The control differential amplifier includes a differential amplifier in which the output of the selection circuit for the output line corresponding to the low level is one of the differential input signals, and the reference voltage on the low level side is the other differential input signal. A differential signal driving circuit, wherein at least one of the variable current sources controlled by the output of the differential amplifier is provided in a current source on the ground side of the output stage. A selection circuit for selecting an output voltage of the differential output signal;
A differential amplifier for control in which the output of the selection circuit is at least one of differential input signals;
A small-amplitude differential signal drive circuit provided with at least one variable current source controlled by the output of the differential amplifier in the current source of the output stage;
The selection circuit for selecting the output voltage corresponds to the high level from time to time among the differential output lines of the two small-amplitude differential signal drivers that constantly change as the serial data signal changes. It is a circuit that selects the output line according to the serial data input signal to the small amplitude differential signal circuit,
The differential amplifier for control has a differential circuit in which the output of the selection circuit for the output line corresponding to the high level is one of the differential input signals, and the reference voltage on the high level side is the other one of the differential input signals. A differential signal driving circuit, characterized in that at least one variable current source that is an amplifier and is controlled by the output of the differential amplifier is provided in a current source on the positive power source side of the output stage. The output voltage selection circuit selects an output line corresponding to a low level from time to time among the differential output lines of the two small amplitude differential signal driving circuits that constantly change with the change of the serial data signal. A selection circuit on the low level side that is selected according to the serial data input signal to the small amplitude differential signal driving circuit, and an output line that corresponds to the high level at the time is selected according to the serial data input signal to the small amplitude differential signal driving circuit A selection circuit on the high level side,
The differential amplifier for control has a first low-level side that uses the output of the selection circuit of the output line corresponding to the low level as one of the differential input signals and the reference voltage on the low-level side as the other differential input signal. The second differential amplifier and the output of the selection circuit for the output line corresponding to the high level are one of the differential input signals, and the reference voltage on the high level side is the other one of the differential input signals. Differential amplifier, and
At least one of the variable current sources controlled by the output of the large differential amplifier on the low level side is provided in the current source on the GND side of the output stage, and the second differential amplifier of the high level side is provided. 3. The differential signal driving circuit according to claim 1, wherein at least one variable current source controlled by an output is provided in a current source on a VDD side of an output stage. The output voltage selection circuit selects the output line corresponding to the low level from time to time among the differential output lines of the two differential signal driving circuits that constantly change with the change of the serial data signal. A circuit that selects according to a serial data input signal to the dynamic signal drive circuit;
The differential amplifier for control uses the output of the selection circuit of the output line corresponding to the low level as one of the differential input signals, and the reference voltage on the low level side as the other differential input signal. And
A plurality of variable current sources controlled by the output of the differential amplifier are provided in the GND-side current source of the output stage, and these current sources can be activated / deactivated by a selection circuit. The differential signal driving circuit according to claim 1. The output voltage selection circuit selects the output line corresponding to the high level from time to time among the differential output lines of the two small amplitude differential signal driving circuits that constantly change as the serial data signal changes. A circuit for selecting according to a serial data input signal to the small amplitude differential signal driving circuit;
In the differential amplifier for control, the output of the selection circuit for the output line corresponding to the high level is one of the differential input signals, and the differential voltage having the reference voltage on the high level side as the other one of the differential input signals. An amplifier,
A plurality of variable current sources controlled by the output of the differential amplifier are provided in the current source on the VDD side of the output stage, and these current sources can be activated / deactivated by a selection circuit. The differential signal driving circuit according to claim 2, wherein: The output voltage selection circuit reduces the output line corresponding to the low level from time to time among the differential output lines of the two small-amplitude differential signal driving circuits that constantly change as the serial data signal changes. A selection circuit on the low level side that is selected according to a serial data input signal to the amplitude differential drive circuit;
A selection circuit on the high level side that selects an output line corresponding to the high level in time and time according to a serial data input signal to the small amplitude differential signal driving circuit;
The differential amplifier for control has a low-level first output in which the output of the selection circuit of the output line corresponding to the low level is one of the differential input signals and the reference voltage on the low level side is the other one of the differential input signals. 1 differential amplifier;
A high-level differential amplifier in which the output of the selection circuit corresponding to the high level is one of the differential input signals and the high-level reference voltage is the other differential input signal. ,
At least one variable current source controlled by the output of the first differential amplifier on the low level side is provided in the current source on the GND side of the output stage, and the second differential amplifier on the high level side A plurality of the variable current sources controlled by the output of the output stage are provided in the current source on the VDD side of the output stage, and these current sources can be activated / deactivated by the selection circuit. 4. The differential signal driving circuit according to claim 3, wherein: A driver for small amplitude differential signals with multiple differential output ports.
The driver of at least one port among them includes a selection circuit for an output voltage of the differential output signal, a control differential amplifier having the selection circuit output as at least one of the differential input signals,
A differential signal driving circuit in which at least one variable current source controlled by the output of the differential amplifier is provided in a current source of an output stage;
The driver of the other port does not have an output voltage monitor circuit, and at least one variable current source controlled by diverting the output of the differential amplifier for controlling the port is included in the current source of the output stage. 4. The differential signal drive circuit according to claim 1, wherein the differential signal drive circuit is a small amplitude differential signal drive circuit provided. The output voltage of the differential output signal is selected by the selection circuit, the selected output is set as at least one of the differential input signals of the differential amplifier, and the variable current source controlled by the output of the differential amplifier is set to the output stage. A driving method for a differential signal having a small amplitude provided in at least one current source,
The selection method for selecting the output voltage corresponds to the low level from time to time among the differential output lines of the two small-amplitude differential signal driving circuits that constantly change as the serial data input signal changes. The output line to be selected is selected according to the serial data input signal to the small-amplitude differential signal drive circuit, and the control differential amplifier outputs the output of the output line selected at the low level as the differential input signal. One low-level reference voltage is used as another differential input signal, and at least one variable current source controlled by the output of the differential amplifier is provided in the ground-side current source of the output stage. A differential signal driving method characterized by the above. The output voltage of the differential output signal is selected by the selection circuit, the selected output is set as at least one of the differential input signals of the differential amplifier, and the variable current source controlled by the output of the differential amplifier is set to the output stage. A driving method for a differential signal having a small amplitude provided in at least one current source,
The selection method for selecting the output voltage is to change the differential output line of the two small-amplitude differential signal driving circuits constantly changing with the change of the serial data input signal to the high level from time to time. This circuit selects the corresponding output line according to the serial data input signal to the small-amplitude differential signal drive circuit, and the above-mentioned differential amplifier for control differentially inputs the output of the output line selected to the high level. One of the signals, the reference voltage on the high level side becomes the other one of the differential input signals, and the variable current source controlled by the output of the differential amplifier is included in the current source on the positive power source side of the output stage A differential signal driving method comprising at least one differential signal.

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