JP2005340431A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a thin semiconductor device. <P>SOLUTION: In a state that a tape 3a with a ring 3b stuck to its outer periphery is stuck to the main surface of a semiconductor wafer 1W, the rear face of the semiconductor wafer 1W is cut and ground to thin the semiconductor wafer 1W. Then the semiconductor wafer 1W is carried to a dicing apparatus in the state that the tape 3a with the ring 3b is stuck to the main surface of the semiconductor wafer 1W without peeling off the tape 3a, dicing processing is applied to the semiconductor wafer 1W from the rear side to divide the semiconductor wafer 1W into semiconductor chips. During the cutting processing of dicing processing or in cutting processing, a grindstone unit 9 is brought into contact with the cutting part of a dicing blade 8 to grind the cutting part of the dicing blade 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a blade dicing technique in a manufacturing process of a thin semiconductor device.

  In the blade dicing process in the manufacturing process of a semiconductor device, after a semiconductor wafer is affixed to a dicing tape, the semiconductor wafer is cut while pressing a blade that rotates at high speed along the cutting area of the main surface of the semiconductor wafer. This is a process of dividing into chips. In the dicing process, the abrasive grains constituting the blade fall off naturally while cutting the semiconductor wafer, and new abrasive grains appear as the cutting process progresses, so-called self-generated blades that maintain good cutting performance. Cutting processing is performed. If the blade becomes worn due to dicing and becomes unsuitable for cutting, replace it with a new blade. When the blade is replaced, it is necessary to perform a so-called dressing process called so-called dressing that makes the surface of the blade suitable for cutting. The blade sharpening process is performed not only when the blade is replaced, but also whenever the blade surface becomes unsuitable for cutting during cutting. The sharpening of the blade is performed, for example, by installing a dummy semiconductor wafer instead of the semiconductor wafer next to the dicing area and cutting the dummy semiconductor wafer with the blade.

  For example, Japanese Patent Application Laid-Open No. 7-307313 discloses a technique related to the sharpening of the dicing blade. For the purpose of shortening the time required for the dressing operation during the processing and reducing the cost of the dummy member, the wafer is prepared prior to the dicing process. The structure which contains the dress material for sharpening the grindstone blade of a dicing apparatus in the bonded adhesive sheet for dicing apparatuses is disclosed (refer patent document 1).

Further, for example, Japanese Patent Laid-Open No. 10-275786 discloses a cutting surface of a dicing blade for the purpose of preventing crushing of a blade used in dicing due to changes in the structure and material of the wafer and eliminating sharpening work. A technique is disclosed in which a dressboard is permanently installed to synchronize the cutting of the workpiece and the dress (see Patent Document 2).
JP-A-7-307313 JP-A-10-275786

  In recent years, semiconductor devices have been used in small electronic devices such as mobile phones and digital cameras, and have been incorporated into thinner electronic devices such as memory cards and integrated circuit (IC) cards. Thinning is demanded more and more because it is attached to various products and used for quality control, or incorporated in securities such as banknotes and used for preventing counterfeiting. Further, in a semiconductor device called SIP (System In Package), since a system is configured by stacking a plurality of semiconductor chips in multiple stages, there is an increasing demand for thinner semiconductor chips.

  By the way, with the thinning of such a semiconductor device, an ultrathin semiconductor wafer thinned to, for example, a thickness of 100 μm or less has been used as a substrate material at the time of manufacturing the semiconductor device. However, the present inventors have found that the following new problems occur during the dicing process as the semiconductor wafer becomes thinner.

  In other words, when the thickness of the semiconductor wafer is about 200 μm or thicker, the semiconductor substrate is sufficiently thick so that the blades are spontaneously generated during dicing, but the thickness of the semiconductor wafer is 100 μm or If it becomes thinner than that, the semiconductor substrate is very thin so that it is difficult for self-generated blades to occur, and due to this, clogging between the abrasive grains of the blade due to dicing tape chips etc. is likely to occur. In addition, there is a problem that chipping (chipping) rapidly increases on the edge of the cutting line of the semiconductor wafer, particularly on the back surface side of the semiconductor wafer in contact with the dicing tape. With the thinning of the semiconductor chip, even small chipping, which has not been noticed until now, leads to a decrease in the bending strength of the semiconductor chip and a decrease in the yield and reliability of the semiconductor device. In the blade dicing process using an ultra-thin semiconductor wafer of 100 μm or less, the blade sharpening process is indispensable, and how to perform the blade sharpening process at an optimal frequency and timing is an important issue.

  An object of the present invention is to provide a technique capable of improving the reliability of a thin semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the yield of thin semiconductor wafers.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, the semiconductor wafer is ground and polished on the back surface of the semiconductor wafer with the tape having the frame portion attached to the main surface of the semiconductor wafer, and then the semiconductor wafer is attached to the dicing apparatus with the tape attached. It has the process of sharpening the said dicing blade by the sharpening means provided in the said dicing apparatus between the cutting process which cut | disconnects with a dicing blade and divides | segments into a semiconductor chip, or a cutting process.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, after grinding and polishing the back surface of the semiconductor wafer with a tape having a frame body attached to the main surface of the semiconductor wafer, the semiconductor wafer is cut with a dicing blade of a dicing apparatus with the tape attached. Optimal even for thin semiconductor wafers where dicing blades are difficult to generate spontaneously by cutting the dicing blades with cutting means provided in the dicing device during cutting processing or cutting processing for dividing into semiconductor chips. Can be sharpened. For this reason, clogging of the dicing blade can be reduced or prevented, and good dicing properties can be secured, so that the reliability of the thin semiconductor device can be improved.

  In addition, clogging of the dicing blade can be reduced or prevented, and good dicing properties can be ensured, so that the problem of chipping can be suppressed even with an extremely thin semiconductor wafer, so that the yield of thin semiconductor devices can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIGS.

  First, in the pre-process 100, for example, a planar substantially circular semiconductor wafer (hereinafter simply referred to as a wafer) having a diameter of about 300 mm is prepared, and a plurality of semiconductor chips (hereinafter simply referred to as chips) are formed on the main surface. The pre-process 100 is also referred to as a wafer process, a diffusion process, or wafer fabrication, and is a process until a chip (element or circuit) is formed on the main surface of the wafer and an electrical test can be performed using a probe or the like. The pre-process includes a film formation process, an impurity introduction (diffusion or ion implantation) process, a photolithography process, an etching process, a metallization process, a cleaning process, and an inspection process between the processes. 2 is an overall plan view of the main surface of the wafer 1W after the pre-process 100, and FIG. 3 is a cross-sectional view taken along line X1-X1 of FIG. On the main surface of the wafer 1W, for example, a plurality of planar rectangular chips 1C are arranged around each of them via a cutting region CR. A semiconductor substrate (hereinafter simply referred to as a substrate) 1S of the wafer 1W is made of, for example, silicon (Si) single crystal, and an element and a wiring layer 1L are formed on its main surface. The thickness of the wafer 1W at this stage (the sum of the thickness of the substrate 1S and the thickness of the wiring layer 1L) is, for example, about 775 μm. The symbol N indicates a notch.

4 is an enlarged plan view of a main part of an example of the wafer 1W in FIG. 2, and FIG. 5 is a sectional view taken along line X2-X2 in FIG. In the wiring layer 1L, an interlayer insulating film 1Li, wirings 1L1 and 1L2, bonding pads (external terminals; hereinafter simply referred to as pads) 1LB, test pads 1LBt, and a protective film 1LP are formed. The interlayer insulating film 1Li is formed of an inorganic insulating film such as silicon oxide (SiO ₂ or the like). The wirings 1L1 and 1L2 and the pads 1LB and 1LBt are formed of a metal film such as aluminum. The protective film 1LP covering the uppermost wiring 1L2 and the pads 1LB and 1LBt is composed of a laminated film of an inorganic insulating film such as silicon oxide and an organic insulating film such as polyimide resin. The organic insulating film of the protective film 1LP is deposited so as to be exposed on the uppermost surface of the main surface of the wafer 1W. An opening 2 is formed in a part of the protective film 1LP, and parts of the pads 1LB and 1LBt are exposed therefrom. The pads 1LB are arranged side by side along the outer periphery of the chip 1C. The test pad 1LBt is arranged in the cutting region CR of the chip 1C.

  6 is an enlarged plan view of a main part of another example of the wafer 1W in FIG. 2, and FIG. 7 is a sectional view taken along line X3-X3 in FIG. In this example, the bump electrode BMP is formed on the pad 1LB via the base metal UBM. The bump electrode BMP is made of a solder material such as lead (Pb) -tin (Sn) or gold (Au). The bump electrode may be made of a solder material having a lead-free (Sn—Ag (silver) —Cu (copper)) composition.

  Next, in the test process 101 of FIG. 1, various electrical characteristic tests are performed by applying probes to the pads 1LB of each chip 1C of the wafer 1W and the test pads 1LBt of the cutting region CR. This test process is also called a G / W (Good chip / Wafer) check process, and is a test process for electrically determining the quality of each chip 1C formed on the wafer 1W.

  A subsequent process 102 in FIG. 1 is a process after the test process 101 until the chip 1C is housed in a sealing body (package) and completed. The back surface processing process 102A, the chip dividing process 102B, It has an assembly process 102C.

  First, in the back surface processing step 102A, a tape is attached to the main surface (chip forming surface) of the wafer 1W (step 102A1). 8 is an overall plan view of the jig 3 to which the wafer 1W is attached, FIG. 9 is a sectional view taken along line X4-X4 in FIG. 8, and FIG. 10 is a sectional view taken along line X4-X4 in another example of FIG. Each is shown. In FIG. 8, the chip 1C on the main surface of the wafer 1W is indicated by a broken line. The jig 3 includes a tape 3a and a ring (frame body) 3b. The tape base 3a1 of the tape 3a is made of, for example, a flexible plastic material, and an adhesive layer 3a2 is formed on the main surface thereof. The tape 3a is firmly attached to the main surface of the wafer 1W by the adhesive layer 3a2. If the thickness of the tape 3a (the sum of the thickness of the tape base 3a1 and the thickness of the adhesive layer 3a2) is too thick, handling in the subsequent steps and peeling of the tape 3a become difficult. For example, the tape 3a is as thin as about 130 to 210 μm. Is used. As this tape 3a, it is also preferable to use, for example, a UV tape. The UV tape is an adhesive tape in which an ultraviolet (UV) curable resin is used as a material for the adhesive layer 3a2, and has a property that the adhesive strength of the adhesive layer 3a2 is rapidly weakened when irradiated with ultraviolet rays while having a strong adhesive force. have.

  In the first embodiment, a rigid ring 3b is attached to the outer periphery of the tape 3a. The ring 3b is a reinforcing member having a function of supporting the tape 3a so as not to bend. From the viewpoint of reinforcement, the ring 3b is preferably formed of a metal such as stainless steel, but may be formed of a plastic material whose thickness is set so as to have the same degree of hardness as the metal. Notches 3b1 and 3b2 are formed on the outer periphery of the ring 3b. The notches 3b1 and 3b2 are used when the jig 3 is handled or when the jig 3 is aligned with the manufacturing apparatus on which the jig 3 is placed, and when the jig 3 is fixed to the manufacturing apparatus. Used as part. In the first embodiment, since the jig 3 is used also during dicing as will be described later, the size and shape of each part of the jig 3 (including the notches 3b1 and 3b2) are shared by the back surface processing and dicing. It is set as possible. FIG. 9 shows a case where the ring 3b is attached to the main surface (wafer attaching surface) of the tape 3a. In FIG. 10, the ring 3b is attached to the back surface (the surface opposite to the wafer attaching surface) of the tape 3a. The case where it is being shown is shown. The ring 3b may be attached before the wafer 1W is attached to the tape 3a, or may be attached after the wafer 1W is attached to the tape 3a.

  Subsequently, the thickness of the wafer 1W is measured in a state where the ring 3b is attached to the tape 3a and the support strength is improved (step 102A2). FIG. 11 is a cross-sectional view showing an example of the thickness measurement of the wafer 1W, and FIG. 12 is an enlarged plan view of a main part when the thickness of the wafer 1W in FIG. 11 is measured. Here, the jig 3 holding the wafer 1W is placed on the suction stage 4 of the back surface processing apparatus and fixed by vacuum suction, and an infrared (Infra red: hereinafter referred to as IR camera) camera 5a is used to form the wafer 1W. The height H1 of the back surface and the height H2 of the main surface of the tape 3a are measured. As a result, the actual thickness of the wafer 1W and the variation in thickness of the tape 3a (about ± 7 to 8 μm) can be measured, and an accurate grinding amount and polishing amount can be determined.

  Thereafter, as shown in FIG. 13, the grinding and polishing tool 6 and the suction stage 4 are rotated, and the grinding process and the polishing process are sequentially performed on the back surface of the wafer 1W based on the grinding amount and the polishing amount (steps 102A3 and 102A3). 102A4). Thereby, as shown in FIG. 14, the thickness of the wafer 1W is made extremely thin, for example, 100 μm or less (here, for example, about 90 μm). In this polishing process, when the thickness of the chip is reduced to 100 μm or less, the die bending strength of the chip is lowered due to damage or stress generated on the back surface of the wafer 1W by the grinding process, and the chip is mounted. Since the problem that the chip is broken due to the pressure of time is likely to occur, it is an important process for eliminating damage and stress on the back surface of the wafer 1W so that such a problem does not occur. As the polishing treatment, for example, an etching method using nitric acid and hydrofluoric acid may be used in addition to a polishing method using a polishing pad and silica or a chemical mechanical polishing (CMP) method.

  After the back surface processing step as described above, the vacuum suction state of the suction stage 4 is released, and the jig 3 holding the extremely thin wafer 1W is taken out from the back surface processing apparatus. At this time, in the first embodiment, since the tape 3a can be firmly supported by the ring 3b even if the wafer 1W is extremely thin, handling and conveyance of the extremely thin wafer 1W can be facilitated. . Further, it is possible to prevent the wafer 1W from being cracked or warped during the handling or transfer. Therefore, the quality of the wafer 1W can be ensured. For this reason, in the first embodiment, the ultra-thin wafer 1W is transported and shipped to another manufacturing factory (for example, an assembly fab) while being held by the jig 3 at the stage after the back surface processing. Later dicing and assembly may be requested.

  Next, the process proceeds to the chip dividing step 102B. Here, first, the jig 3 holding the ultra-thin wafer 1W is transferred to the dicing apparatus as it is and placed on the suction stage 7 of the dicing apparatus as shown in FIG. That is, usually, a process of peeling off the tape attached to the main surface of the wafer 1W during back surface processing and attaching a dicing tape to the back surface of the wafer 1W (wafer mounting) is required. Then, since the wafer mounting process can be reduced, the manufacturing process of the semiconductor device can be simplified. Therefore, the manufacturing time of the semiconductor device can be shortened. In addition, since the dicing tape can be omitted, the material cost can be reduced and the cost of the semiconductor device can be reduced.

  Subsequently, in the first embodiment, since dicing is performed with the tape 3a attached to the main surface of the wafer 1W, the main surface of the wafer 1W is pulled from the back surface of the wafer 1W by the IR camera 5b while the jig 3 is vacuum-sucked. (The metal pattern of the chip 1C and the cutting region CR) is recognized (step 102B1). At this time, in the first embodiment, since the wafer 1W is extremely thin, the pattern of the main surface of the wafer 1W can be sufficiently observed. Thereafter, the dicing line (cutting region CR) is aligned (position correction) based on the pattern information obtained by the IR camera 5b, and blade dicing is performed (step 102B2).

  16 shows the state of the wafer 1W during dicing, FIG. 17 shows the state of the dicing blade (dicing blade: hereinafter simply referred to as the blade) 8 of FIG. 16, and FIG. 18 shows the state of the wafer 1W after dicing. ing. An arrow A in FIG. 16 indicates the moving direction of the blade 8, and an arrow B indicates the rotating direction of the blade 8. In the dicing process, as shown in FIG. 16, the blade 8 rotating at a high speed is pressed against the cutting region CR from the back surface of the wafer 1W to cut the wafer 1W, and divided into individual chips 1C as shown in FIG. Here, in the first embodiment, a sharpening grindstone unit is installed in a movable state as indicated by an arrow C on the side of the grinding surface of the blade 8 of the dicing apparatus, and the wafer 1W is cut. During the processing or during the cutting process, the sharpening unit 9 can be brought into contact with the grinding surface of the blade 8 to perform the sharpening process. As a result, even if the wafer 1W is as thin as 100 μm or less, the grinding surface of the blade 8 can be appropriately sharpened, so that the self-generated blade can be promoted and the clogging of the blade 8 is reduced or reduced. Can be prevented. For this reason, it is possible to maintain good machinability, so that the occurrence of the above chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented. Therefore, since the bending strength of the thin chip 1C can be improved, the yield and reliability of the semiconductor device having the thin chip 1C can be improved. Further, when the wafer 1W becomes thin, frequent sharpening is necessary to make the surface of the blade 8 suitable for cutting. Therefore, a dummy wafer is placed beside the dicing area, and the dummy wafer is cut by the blade. Thus, in the method of sharpening the blade, the sharpening process takes time and the dicing process time becomes long. On the other hand, in the first embodiment, since the sharpening can be performed by the sharpening grindstone unit 9 during or between the cutting processes, the shortening of the sharpening process time can be greatly shortened. Therefore, since the dicing time can be shortened, the manufacturing time of the semiconductor device can be shortened.

  The sharpening of the blade 8 during the cutting process of the wafer 1W may be performed continuously during the cutting process, or may be performed intermittently at an appropriate time during the cutting process. Thereby, the blade 8 can be appropriately sharpened and the life of the blade 8 can be improved. Further, as the sharpening process of the blade 8 performed during the cutting process of the wafer 1W, the sharpening grindstone unit 9 is attached to the blade 8 immediately before or immediately after the cutting process, or both, that is, at the start point, the end point, or both of each cutting line. For example, the sharpening process of the blade 8 is performed in contact with the grinding surface. Further, the number of times of sharpening (time) may be changed according to the length of each cutting line. For example, the number of sharpening processes with relatively long cutting lines may be larger than the number of sharpening processes with relatively short cutting lines. Thereby, the blade 8 can be appropriately sharpened and the life of the blade 8 can be improved. As described above, in the first embodiment, the sharpening grindstone unit 9 is installed in the dicing apparatus, and its operation (that is, sharpening processing) can be controlled, so that the sharpening processing of the blade 8 is performed according to various situations. Is possible.

  The grinding part (cutting edge) of the sharpening grindstone unit 9 is composed of a grindstone in which a large number of abrasive grains are bonded with a binder. The grinding part of the sharpening grindstone unit 9 may be composed of, for example, single crystal silicon (Si) or polycrystalline silicon that has not been subjected to impurity introduction treatment, in addition to the grindstone. By making the material of the grinding part of the sharpening grindstone unit 9 the same as that of the wafer 1W, the problem of impurities can be avoided. Further, the running cost can be reduced by using polycrystalline silicon which is cheaper than single crystal silicon.

The blade 8 is formed by, for example, fixing diamond and nickel by an electrodeposition method. The blade 8 may be formed by embedding diamond particles in a disc-shaped base substrate made of an organic material. The thickness of the blade 8 is, for example, about 30 to 35 μm. The blade 8 rotates at, for example, tens of thousands of revolutions / min, and cuts the wafer 1W at a speed of, for example, 40 to 200 mm / second. The cutting speed of the wafer 1W is determined in consideration of the thickness of the wafer 1W and the cutting quality. During the cutting process of the wafer 1W by the blade 8 or between the cutting processes, the grinding part of the blade 8 is used for the purpose of removing the residue generated during dicing or cooling the heat when the blade 8 cuts the wafer 1W. High-pressure jet of ultrapure water. In this ultrapure water, it is important to set the specific resistance value to an appropriate value so that the circuit formed on the wafer 1W is not destroyed by static electricity or the like. ₂ ) is included.

  Here, in the first embodiment, a plurality of ultra-thin chips 1C are held in the jig 3 at the stage after dicing as described above, and are shipped to another manufacturing factory (for example, an assembly fab). In addition, assembly after the dicing process may be requested.

  Next, the process proceeds to the assembly process 102C. Here, the jig 3 holding the plurality of chips 1C is conveyed to the pickup device. Here, as shown in FIG. 19, first, with the jig 3 placed on the mounting table 10, the ring 3 b is pushed down in the direction indicated by the arrow E, and the tape 3 a is extended in the direction indicated by the arrow F, and the chips adjacent to each other. Increase the interval of 1C. FIG. 20 shows an enlarged cross-sectional view of main parts of the jig 3 and the wafer 1W of the pickup device at this stage. On the back side of the tape 3a, a push-up pin 11 is installed so as to be movable up and down. Further, the collet 12 is installed above the back surface of the chip 1C so as to be movable up and down and left and right. Although a flat collet is used as the collet 12, a pyramid collet may be used. In this pick-up process, as shown in FIG. 21, the chip 1C is pushed up from the back surface of the tape 3a by the push-up pin 11 while the back surface of the tape 3a is vacuum-sucked. At this time, when the UV tape is used as the tape 3a, the adhesive layer 3a2 of the tape 3a is irradiated with ultraviolet rays to cure the adhesive layer 3a2 and weaken the adhesive force. In this state, the semiconductor chip 1C is vacuum-sucked by the collet 12, thereby picking up the chip 1C as shown in FIG. 22 (step 102C1).

  However, if the chip 1C becomes thin, even if a UV tape is used, the chip 1C may be cracked or cause a pickup error due to the pressing force of the push-up pin 11. In such a case, it may be as follows. FIG. 23 shows an enlarged cross-sectional view of a main part of the jig 3 placed on the pickup device. Here, the multi-projection suction piece 13 is installed on the back side of the tape 3a. In this case, as shown in FIG. 24, the contact state between the main surface of the chip 1C and the main surface of the tape 3a is brought into surface contact by vacuum suction of the tape 3a from the back surface side through the suction holes of the multi-projection suction piece 13. To point contact. Thereby, the contact area of the chip 1C and the tape 3a can be reduced. In this state, as shown in FIG. 25, the chip 1C is picked up by the collet 12 (step 102C1). As a result, even an extremely thin chip 1C can be picked up without causing cracks or the like. In this case, the chip 1C can be easily picked up without using a UV tape as the tape 3a. However, by using the UV tape, the adhesive layer 3a2 of the tape 3a is irradiated with ultraviolet rays at the time of picking up to further reduce the adhesiveness. The chip 1C can be easily picked up.

  Subsequently, after the chip 1C picked up as described above is reversed by the existing reversing unit so that the main surface of the chip 1C faces upward, as shown in FIG. To the chip mounting area. For example, an adhesive 16 such as silver (Ag) paste or the like is applied to the chip mounting region of the printed wiring board 15 in a matrix. The chip 1C may be mounted on the die pad (chip mounting portion) of the lead frame instead of the printed wiring board 15. Alternatively, the picked-up chip 1C may be accommodated in a transport tray, transported and shipped to another manufacturing factory (for example, an assembly fab), and assembly after this process may be requested (process 103A). Subsequently, as shown in FIG. 27, the chip 1C is placed on the chip mounting area with the back surface of the chip 1C facing the chip mounting area of the printed wiring board 15, and is scrubbed in an appropriate direction. To spread the adhesive 16 over the entire back surface of the chip 1C. Thereafter, the adhesive 16 is cured to fix the chip 1C on the printed wiring board 15 (step 102C2). Thereafter, as shown in FIG. 28, the pad 1LB on the main surface of the chip 1C and the electrode of the printed wiring board 15 are connected by a bonding wire (hereinafter simply referred to as a wire) 17 (step 102C3). Thereafter, the chip 1C is sealed with a sealing body made of a plastic material such as an epoxy resin using a transfer mold method (step 102C4). When the chip 1C has the bump electrode BMP as shown in FIG. 6 and FIG. 7, the chip 1C is transferred to the chip mounting area of the printed wiring board 15 with its main surface facing down in the pickup process 102C1. Then, after temporarily fixing the bump electrode BMP of the chip 1C and the electrode of the chip mounting area using a paste material, the bump electrode BMP of the chip 1C and the electrode of the printed wiring board 15 are subjected to reflow treatment (thermosetting treatment). Is fixed (flip chip bonding). Thereafter, an underfill is filled between the opposing surfaces of the chip 1C and the printed wiring board 15, and then the chip 1C is sealed in the same manner as described above (step 102C4).

  FIG. 29 shows an example of a cross-sectional view of the semiconductor device 20 manufactured by the method for manufacturing the semiconductor device of the first embodiment. The semiconductor device 20 has a SIP (System In Package) configuration in which a system having a desired function is built in one package. A plurality of bump electrodes 21 are arranged in a matrix on the back surface of the printed wiring board 15 constituting the semiconductor device 20. A plurality of thin chips 1C1, 1C2 (1C) are stacked on the main surface of the printed wiring board 15. The lowermost chip 1C1 is mounted on the main surface of the printed wiring board 15 via the bump electrodes BMP on the main surface. On the main surface of the chip 1C1, a memory circuit such as an SRAM (Static Random Access Memory), an SDRAM (Synchronous Dynamic Random Access Memory), or a flash memory is formed. For example, a non-conductive film NCF is interposed between the main surface of the chip 1C1 and the main surface of the printed wiring board 15. A chip 1C2 is mounted on the back surface of the chip 1C1 via a die attach film 22. The chip 1C2 is mounted with its main surface facing up. On the main surface of the chip 1C2, a logic circuit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor) is formed. The pads 1LB on the main surface of the chip 1C2 are electrically connected to the electrodes on the main surface of the printed wiring board 15 through the wires 17. Such chips 1C1 and 1C2 and the wire 17 are sealed by a sealing body 24 made of, for example, an epoxy resin. According to the manufacturing method of the semiconductor device of the first embodiment described above, a multi-layer stack such as the chips 1C1 and 1C2 as shown in FIG. 29 can be performed, and the semiconductor device 20 having the SIP configuration can be thinned. . In addition, the reliability of the semiconductor device 20 having the SIP configuration can be improved.

(Embodiment 2)
In the second embodiment, an example will be described in which dicing processing is performed after a sharpening grindstone is attached to a dicing tape.

  FIG. 30 is an overall plan view of the jig 3 in a state in which the wafer 1W is accommodated in the second embodiment, and shows a plan view of a dicing area during the dicing process. The wafer 1W is accommodated in the jig 3 in a state where the main surface of the wafer 1W is attached to the tape 3a of the jig 3 as in the first embodiment. A flat band-shaped sharpening grindstone 27 is attached between the outer surface of the wafer 1W and the inner periphery of the ring 3b on the main surface of the tape 3a to which the wafer 1W is attached. In the dicing process, the blade 8 can be sharpened by bringing the blade 8 into contact with the sharpening grindstone 27 immediately before or immediately after the cutting process of the wafer 1W by the blade 8. Accordingly, as in the first embodiment, even if the wafer 1W is thin with a thickness of 100 μm or less, the ground surface of the blade 8 can be appropriately sharpened. 8 clogging can be reduced or prevented. For this reason, good machinability can be maintained, and the occurrence of chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented, so that the bending strength of the thin chip 1C can be improved, and the thin The yield and reliability of the semiconductor device having the chip 1C can be improved. In the case of the second embodiment, it is not necessary to change the dicing apparatus, and the conventional dicing apparatus can be used as it is. That is, it is possible to eliminate the time required for new investment and device change, and therefore, it is possible to cope with dicing processing of the thin wafer 1W in a short period of time at a relatively low cost.

  Further, in the second embodiment, as shown in FIG. 30, the sharpening grindstone 27 is attached before the dicing step 102B2 of FIG. 1, but if it is attached before the back surface processing step 102A, the back surface processing ( Since it may interfere with the back surface grinding step 102A3 and the back surface grinding step 102A4), it is preferably pasted after the back surface grinding step 102A4 in FIG. Reference sign CL indicates a cutting line by the blade 8.

(Embodiment 3)
In the third embodiment, a modification of the second embodiment will be described.

  FIG. 31 is an overall plan view of the jig 3 in a state in which the wafer 1W is accommodated in the third embodiment, and shows a plan view of a dicing area in the dicing process. In the third embodiment, the sharpening grindstone 27 is formed in a planar ring shape so as to surround the outer periphery of the wafer 1W.

  In the third embodiment, by adjusting the moving length of the blade 8, the blade 8 can be either one of the start point and the end point of the cutting line CL (immediately before or immediately after the cutting process) or both (immediately before and immediately after the cutting process). The sharpening process is possible. Further, since the distance from the outer periphery of the wafer 1W to the sharpening grindstone 27 is almost equal at any location on the outer periphery of the wafer 1W, the length of the cutting line CL located outside the wafer 1W (the total length of the cutting line CL) is implemented. It can be made shorter than in the case of Form 2. For this reason, the moving distance of the blade 8 when cutting the cutting line CL located outside the wafer 1W can be made shorter than in the case of the second embodiment. Moreover, since there is one sharpening grindstone 27, it can be easily attached to the tape 3a.

(Embodiment 4)
In the fourth embodiment, an example in which dicing processing is performed after attaching a sharpening member to the back surface of the wafer after processing the back surface of the wafer will be described.

  In the fourth embodiment, as shown in FIG. 32, after attaching the dummy wafer 28 to the back surface of the wafer 1W after the back surface processing step 102A, as shown in FIG. The first wafer 1W and the dummy wafer 28 are cut while being stacked. In other words, the grinding surface of the blade 8 is appropriately sharpened by cutting the dummy wafer 28 during the dicing process. Thereby, even if the wafer 1W is as thin as 100 μm or less, by cutting the dummy wafer 1W, the blade 8 can be encouraged to spontaneously generate blades, and clogging of the blade 8 can be reduced or prevented. Therefore, the occurrence of chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented. For this reason, the bending strength of the thin chip 1C can be improved, and the yield and reliability of the semiconductor device having the thin chip 1C can be improved. Also, in the case of the fourth embodiment, since the dicing apparatus need not be changed and the conventional dicing apparatus can be used as it is, it is possible to eliminate the time required for new investment and apparatus change, which is relatively low. It is possible to cope with dicing processing of the thin wafer 1W within a short period of time due to cost.

  The dummy wafer 28 is made of, for example, single crystal silicon (Si) that has not been subjected to impurity introduction processing. By making the material of the dummy wafer 28 the same as that of the wafer 1W, the problem of impurities can be avoided. The thickness of the dummy wafer 28 is preferably set so that the total thickness of the dummy wafer 28 and the product wafer 1W is about 200 μm or thicker from the standpoint of sharpening the blade 8. In the fourth embodiment, since the thickness of the wafer 1W is about 90 μm, the thickness of the dummy wafer 28 is larger than the thickness of the wafer 1W, for example, about 110 μm or more. However, if the thickness of the dummy wafer 28 is too thick, the life of the blade 8 may be shortened. Therefore, the dummy wafer 28 may change depending on the material of the dummy wafer 28. It is preferable to set the thickness of the dummy wafer 28 so that the total thickness with the product wafer 1W is about 280 to 300 μm or less.

  The dummy wafer 28 may be made of polycrystalline silicon, which is cheaper than single crystal silicon, instead of single crystal silicon. Thereby, running cost can be reduced. Further, instead of the dummy wafer 28, a glass substrate such as quartz may be used. The substrate portion of the dummy wafer 28 attached to the back surface of the chip 1C after the dicing process is peeled off before the die bonding step 102C2.

(Embodiment 5)
In the fifth embodiment, a dicing process when a die attach film is attached to the back surface of a wafer will be described. 34 to 36 are sectional views of the wafer 1W during the manufacturing process of the semiconductor device of the fifth embodiment.

  First, as shown in FIG. 34, the die attach film 22 is attached to the back surface of the wafer 1W after the back surface processing step 102A of the wafer 1W. The die attach film 22 is made of a resin material such as an epoxy resin or a polyimide resin having an adhesive function and filled with a conductive filler, and is an adhesive for fixing the chip to a lead frame or a wiring board. In the fifth embodiment, the die attach film 22 includes a plurality of fine dressing particles made of, for example, white alundum or green carbonate dispersed therein. The die attach film 22 includes a dress layer formed by collecting a plurality of the above-described fine particles, and a resin material layer (including a conductive filler) formed above and below the dress layer so as to sandwich the dress layer. A three-layer structure may be used. Further, a plurality of fine dressing particles may be dispersed in the tape 3b.

  Subsequently, as shown in FIG. 35, the wafer 1W is cut by a dicing process using the blade 8 as in the first embodiment, and is divided into individual chips 1C as shown in FIG. In this dicing process, in the fifth embodiment, when the wafer 1W is cut by the blade 8 rotating at high speed, the die attach film 22 is cut at the same time, so that the ground surface of the blade 8 is changed to the dress in the die attach film 22. It is possible to make it stand out with fine particles. Further, since a part of the main surface of the tape 3a is cut by the blade 8, the blade 8 ground surface can be conspicuous by the fine particles for dressing in the tape 3a. As a result, even if the wafer 1W is as thin as 100 μm or less, the fine particles for dressing can prompt the blade 8 to be self-generated, and clogging of the blade 8 can be reduced or prevented. The machinability can be maintained, and the occurrence of the above chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented. For this reason, the bending strength of the thin chip 1C can be improved, and the yield and reliability of the semiconductor device having the thin chip 1C can be improved.

  Thus, the chip 1C having the die attach film 22 attached to the back surface is prepared.

(Embodiment 6)
In the sixth embodiment, an example in which the blade is sharpened with ultrapure water sprayed onto the blade during the dicing process will be described.

  FIG. 37 is a side view of the blade 8 and the blade cooler piping 30, and FIG. 38 is a front view of main parts of the blade 8 and the blade cooler piping 30 when viewed from the direction of arrow G in FIG. 37. An arrow H indicated by a broken line in FIG. 37 indicates a flowing direction of the ultrapure water in the blade cooler pipe 30. An arrow J in FIG. 38 indicates the injection direction of the ultrapure water WA from the blade cooler pipe 30 to the grinding portion of the blade 8. The blade cooler wiring 30 is arranged at a desired distance from the side surface of the blade 8 so as to sandwich the lower portions (grinding portions) on both side surfaces of the blade 8.

  During or during the cutting process of the wafer 1W by the blade 8, as described in the first embodiment, the heat generated when the blade 8 cuts the wafer 1W is removed in order to remove residues generated during dicing. For the purpose of cooling or the like, ultrapure water (first water) is sprayed from the blade cooler pipe 30 to the grinding portion of the blade 8 under a first condition (pressure, flow velocity, flow rate, etc.).

Further, in the sixth embodiment, during or during the cutting process of the wafer 1W by the blade 8, for the purpose of sharpening the grinding part of the blade 8, the blade cooler pipe 30 is used. Ultrapure water (second water) is sprayed to the grinding part of the blade 8 under the second condition (pressure, flow velocity, flow rate, etc.). That is, the sharpening process of the grinding part of the blade 8 is performed by adjusting the injection conditions (pressure, flow velocity, flow rate, etc.) of the ultrapure water injected from the blade cooler pipe 30 to the blade 8. In this case, values such as pressure, flow velocity, and flow rate under the second condition are set larger than values such as pressure, flow velocity, and flow rate under the first condition. In the ultrapure water, it is important to set the specific resistance value to an appropriate value so that the circuit formed on the wafer 1W is not destroyed by static electricity or the like, as in the first embodiment. A trace amount of carbon dioxide (CO ₂ ) is contained in water.

  According to the sixth embodiment as described above, even when the wafer 1W is as thin as 100 μm or less, it is possible to prompt the blade 8 to self-generate by the injection of the ultra pure water, and the blade 8 is clogged. Since it can be reduced or prevented, good machinability can be maintained, and the occurrence of chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented. For this reason, the bending strength of the thin chip 1C can be improved, and the yield and reliability of the semiconductor device having the thin chip 1C can be improved. In the sixth embodiment, the grindstone replacement work can be reduced. Moreover, running cost can be reduced.

(Embodiment 7)
In the seventh embodiment, a modification of the sixth embodiment will be described.

  In the seventh embodiment, during the cutting process of the wafer 1W by the blade 8 or during the cutting process, for the purpose of removing the residue generated at the time of dicing or cooling the heat when the blade 8 cuts the wafer 1W. 37. In addition to the first water that injects ultrapure water from the blade cooler pipe 30 of FIG. 37 into the grinding part of the blade 8 under the first conditions (pressure, flow velocity, flow rate, etc.), the sharpening process of the grinding part of the blade 8 For this purpose, ultrapure water (second water) having a carbon dioxide concentration higher than the carbon dioxide concentration of ultrapure water (first water) under the first condition is ground from the blade cooler pipe 30 to the blade 8. Inject into the part. That is, the sharpening process of the grinding part of the blade 8 is performed by adjusting the carbon dioxide concentration of the ultrapure water sprayed from the blade cooler pipe 30 to the blade 8. As a result, even if the wafer 1W is as thin as 100 μm or less, the above-described ultrapure water can prompt the blade 8 to be self-generated, and clogging of the blade 8 can be reduced or prevented. Therefore, the occurrence of the above chipping at the edge of the cut surface of the wafer 1W can be reduced or prevented. For this reason, the bending strength of the thin chip 1C can be improved, and the yield and reliability of the semiconductor device having the thin chip 1C can be improved. Also in the seventh embodiment, the replacement work of the grindstone can be reduced, and the running cost can be reduced. Instead of carbon dioxide, a chemical solution may be included in ultrapure water for the sharpening process. In the case of the seventh embodiment, since the main surface of the wafer 1W is covered and protected by the tape 3a in the dicing process as in the first embodiment, ultrapure water containing high-concentration carbon dioxide or a chemical solution is used. Even if is used, it is possible to prevent the main surface of the wafer 1W from being affected. However, when the influence on the wafer 1W is increased or there is a concern, it is preferable to perform the sharpening process on the outer periphery of the wafer 1W away from the wafer 1W. That is, it is preferable to perform a sharpening process between the cutting processes. For example, after the blade 8 is sharpened with ultrapure water containing high-concentration carbon dioxide or a chemical solution in the outer peripheral region of the wafer 1W, the blade 8 is washed with ultrapure water. Subsequently, the wafer 1W is cut along one cutting line. After the cutting of one cutting line is completed, the blade 8 is sharpened similarly to the above in the outer peripheral region of the wafer 1W, the cleaning process is performed, and the wafer 1W is cut along another cutting line. Such a process is repeated for each cutting line.

(Embodiment 8)
FIG. 39 shows a side view of the blade 8 and the blade cooler piping 30 of the eighth embodiment. The main part viewed from the arrow K in FIG. 39 is the same as in FIG.

  In the eighth embodiment, a dedicated pipe 31 for supplying ultrapure water for sharpening the grinding part of the blade 8 is provided in the dicing apparatus. That is, in the eighth embodiment, during the cutting process of the wafer 1W by the blade 8 or during the cutting process, the residue generated during dicing is removed, or the heat when the blade 8 cuts the wafer 1W is cooled. In addition to injecting ultrapure water from the blade cooler pipe 30 of FIG. 37 into the grinding part of the blade 8 under the first conditions (pressure, flow velocity, flow rate, etc.), the purpose of the sharpening process of the grinding part of the blade 8 is As described above, ultrapure water is jetted from the dedicated pipe 31 to the grinding portion of the blade 8 under the third condition (pressure, flow velocity, flow rate, etc.). The method of sharpening the blade 8 is the same as that of the blades 8 of the sixth and seventh embodiments except that the ultrapure water for the sharpening treatment (ultra pure water containing high-concentration carbon dioxide and chemicals) is injected from the dedicated pipe 31. It is the same as the sharpening method.

(Embodiment 9)
In the ninth embodiment, a modification of the sharpening grindstone unit of the first embodiment will be described. 40 and 41 are explanatory views of the sharpening grindstone unit 9 according to the ninth embodiment. FIG. 40 shows the sharpening grindstone unit 9 used for sharpening the bevel-type blade 8, and FIG. 41 shows the sharpening grindstone unit 9 used for sharpening the step-type blade 8. In any case, the grindstone 9a of the sharpening grindstone unit 9 is divided into two. In the sharpening process, the sharpening process is performed by sandwiching the grinding portion of the blade 8 by moving the two grindstones 9a in the direction indicated by the arrow M.

  According to the ninth embodiment, by preparing the grindstone 9a in accordance with the shape of the grinding part of the blade 8, an appropriate sharpening process can be performed on the blade 8.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to the method of manufacturing a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways. The present invention can also be applied to a liquid crystal device manufacturing method (particularly a glass substrate cutting method) and a micromachine manufacturing method.

  The present invention can be applied to the semiconductor device manufacturing industry.

It is a flowchart of the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is an overall plan view of the main surface of the semiconductor wafer after the pre-process of FIG. 1. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 3 is an enlarged plan view of a main part of an example of the semiconductor wafer of FIG. 2. It is sectional drawing of the X2-X2 line | wire of FIG. FIG. 10 is an enlarged plan view of a main part of another example of the semiconductor wafer of FIG. 2. It is sectional drawing of the X3-X3 line | wire of FIG. It is a whole top view of the jig | tool with which the semiconductor wafer was affixed. It is sectional drawing of the X4-X4 line | wire of FIG. It is sectional drawing of the X4-X4 line of the other example of FIG. It is sectional drawing which shows the mode of an example of the thickness measurement of a semiconductor wafer. FIG. 12 is an enlarged plan view of a main part when the thickness of the semiconductor wafer of FIG. 11 is measured. It is explanatory drawing of the back surface process of a semiconductor wafer. It is explanatory drawing of the back surface process of a semiconductor wafer following FIG. It is explanatory drawing of the pattern recognition process of the main surface of a semiconductor wafer. It is explanatory drawing of the dicing process of a semiconductor wafer. It is explanatory drawing which shows a mode that the dicing blade of FIG. 16 was seen from the top. It is sectional drawing of the semiconductor chip after the dicing process of FIG. It is explanatory drawing of the pick-up process of a semiconductor chip. FIG. 20 is an explanatory diagram of a pickup process in which a main part of the semiconductor chip in the stage of FIG. 19 is enlarged. FIG. 21 is an explanatory diagram of the semiconductor chip pickup process following FIG. 20. FIG. 22 is an explanatory diagram of the semiconductor chip pickup process following FIG. 21. It is explanatory drawing of the other example of the pick-up process of a semiconductor chip. FIG. 24 is an explanatory diagram of the semiconductor chip pickup process following FIG. 23. FIG. 25 is an explanatory diagram of the semiconductor chip pickup process following FIG. 24. It is explanatory drawing of the die-bonding process of a semiconductor chip. FIG. 27 is an explanatory diagram of the semiconductor chip die bonding process following FIG. 26; It is explanatory drawing of the wire bonding process following the die bonding process of FIG. It is sectional drawing of an example of the semiconductor device manufactured with the manufacturing method of the semiconductor device which is one embodiment of this invention. It is a top view of the dicing area at the time of the dicing process of the semiconductor device which is other embodiments of the present invention. It is a top view of the dicing area at the time of the dicing process of the semiconductor device which is other embodiments of the present invention. It is sectional drawing of the semiconductor wafer before the dicing process of the semiconductor device which is other embodiment of this invention. FIG. 33 is a cross-sectional view of the semiconductor wafer during the dicing process of the semiconductor device following FIG. 32; It is sectional drawing of the semiconductor wafer before the dicing process of the semiconductor device which is other embodiment of this invention. FIG. 35 is a cross-sectional view of the semiconductor wafer during the dicing process of the semiconductor device continued from FIG. 34. FIG. 36 is a cross-sectional view of the semiconductor chip after the dicing process of the semiconductor device continued from FIG. 35; It is a side view of a dicing blade and blade cooler piping. It is the principal part front view of a dicing blade and blade cooler piping seen from the direction of arrow G of FIG. It is a side view of the other example of a dicing blade and blade cooler piping. It is explanatory drawing of the sharpening means used by the dicing process of the semiconductor device which is other embodiment of this invention. It is explanatory drawing of the other example of the sharpening means used by the dicing process of the semiconductor device which is other embodiment of this invention.

Explanation of symbols

1W Semiconductor wafer 1C Semiconductor chip 1S Semiconductor substrate 1L Wiring layer 1Li Interlayer insulating film 1L1, 1L2 Wiring 1LB Bonding pad 1LBt Bonding pad 1LP for test 2 Opening 3 Jig 3a Tape 3a1 Tape base 3a2 Adhesive layer 3b Ring (frame) body)
3b1, 3b2 Notch 4 Suction stage 5a, 5b Infrared camera 6 Grinding / polishing tool 7 Suction stage 8 Dicing blade (dicing blade)
9 Grinding wheel unit for sharpening (shaping means)
9a Grinding wheel 10 Mounting table 11 Push-up pin 12 Collet 13 Multi-projection adsorption piece 15 Printed wiring board 16 Adhesive material 17 Bonding wire 20 Semiconductor device 21 Bump electrode 22 Die attach film 24 Sealing body 27 Grinding wheel for sharpening (shaping member)
28 Dummy wafer (shaping member)
30 Blade cooler piping 31 Dedicated piping N Notch UBM Underlying metal BMP Bump electrode NCF Non-conductive film CL Cutting line

Claims (16)

(A) preparing a semiconductor wafer having a main surface and a back surface opposite to the main surface;
(B) forming a semiconductor chip having a semiconductor element on the main surface of the semiconductor wafer;
(C) a step of attaching a tape having a frame provided on the outer periphery to the main surface of the semiconductor wafer;
(D) A step of polishing after grinding the back surface of the semiconductor wafer with the tape attached to the main surface of the semiconductor wafer;
(E) recognizing a pattern in a cutting region of the main surface of the semiconductor wafer;
(F) With the tape attached to the main surface of the semiconductor wafer, after the step (e), the dicing blade rotating a dicing device is applied to the cutting area from the back surface of the semiconductor wafer to attach the semiconductor wafer. Cutting and dividing into the semiconductor chips,
(G) having a step of taking out the semiconductor chip after the step (f),
Manufacturing of a semiconductor device, wherein the dicing blade is sharpened by bringing the dicing blade into contact with a sharpening means provided in the dicing apparatus during or during the cutting process in the step (f). Method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the sharpening means is provided on a side portion of the dicing blade, and the semiconductor wafer is cut while the sharpening process of the dicing blade is performed. . 2. The method of manufacturing a semiconductor device according to claim 1, further before the step (f), is a surface of the tape to which the semiconductor wafer is attached, outside the semiconductor wafer, and the frame body. Attach a sharpening member for sharpening the dicing blade to the passing area of the dicing blade on the inner side,
In the step (f), the sharpening process of the dicing blade is performed by bringing the dicing blade into contact with the sharpening member.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the sharpening member is attached after the step (d).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the semiconductor wafer after the step (d) is 100 [mu] m or less than 100 [mu] m. (A) preparing a semiconductor wafer having a main surface and a back surface opposite to the main surface;
(B) forming a semiconductor chip having a semiconductor element on the main surface of the semiconductor wafer;
(C) a step of attaching a tape having a frame provided on the outer periphery to the main surface of the semiconductor wafer;
(D) A step of polishing after grinding the back surface of the semiconductor wafer with the tape attached to the main surface of the semiconductor wafer;
(E) recognizing a pattern in a cutting region of the main surface of the semiconductor wafer;
(F) With the tape attached to the main surface of the semiconductor wafer, after the step (e), the dicing blade rotating a dicing device is applied to the cutting region from the back surface of the semiconductor wafer to attach the semiconductor wafer. Cutting and dividing into the semiconductor chips,
(G) having a step of taking out the semiconductor chip after the step (f),
After the step (e), before the step (f), a sharpening member for sharpening the dicing blade is attached to the back surface of the semiconductor wafer,
A method for manufacturing a semiconductor device, wherein the dicing blade is sharpened by cutting the sharpening member with the dicing blade during the semiconductor wafer cutting process in the step (f).   7. The method of manufacturing a semiconductor device according to claim 6, wherein a thickness of the sharpening member is larger than a thickness of the semiconductor wafer after the step (d).   8. The method of manufacturing a semiconductor device according to claim 7, wherein the sharpening member is a semiconductor wafer.   7. The method of manufacturing a semiconductor device according to claim 6, wherein a thickness of the semiconductor wafer after the step (d) is 100 μm or less than 100 μm.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the sharpening member is a die attach film.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the die attach film contains abrasive grains. (A) preparing a semiconductor wafer having a main surface and a back surface opposite to the main surface;
(B) forming a semiconductor chip having a semiconductor element on the main surface of the semiconductor wafer;
(C) a step of attaching a tape having a frame provided on the outer periphery to the main surface of the semiconductor wafer;
(D) A step of polishing after grinding the back surface of the semiconductor wafer with the tape attached to the main surface of the semiconductor wafer;
(E) recognizing a pattern in a cutting region of the main surface of the semiconductor wafer;
(F) With the tape attached to the main surface of the semiconductor wafer, after the step (e), the dicing blade rotating a dicing device is applied to the cutting region from the back surface of the semiconductor wafer to attach the semiconductor wafer. Cutting and dividing into the semiconductor chips,
(G) having a step of taking out the semiconductor chip after the step (f),
During the cutting process or during the cutting process in the step (f), the first water for cooling the generated heat of the dicing blade and the second water for performing the sharpening process of the dicing blade are sprayed to the dicing blade, respectively. A method for manufacturing a semiconductor device.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the pressure of the second water is higher than the pressure of the first water.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the second water contains a chemical solution.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the thickness of the semiconductor wafer after the step (d) is 100 [mu] m or less than 100 [mu] m.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the carbon dioxide concentration of the second water is higher than the carbon dioxide concentration of the first water.

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