JP2005277433A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can restrain the price low, by using a semiconductor device single layer wiring plate to simplify a structure. <P>SOLUTION: The semiconductor device is provided with a resin substrate 300, which has a first surface and a second surface on the opposite side of the first surface and in which a through-hole passing through the first surface and the second surface is provided, metal wirings 304 and 308 formed on the first surface of the resin substrate so that a portion thereof covers the through-hole, and a plurality of bump electrodes 344 and 348 connected to the metal wiring. Furthermore, semiconductor device comprises a semiconductor chip 350 which is mounted on a region, corresponding to the through-hole of the first surface of the resin substrate, an insulation sheet 341 which covers the metal wiring, excluding a region connected to the bump electrode, and solder balls 334 and 338 which are formed in the second surface side of the resin substrate and are connected to the metal wirings exposed inside the through-hole. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an LSI package, and more particularly, to a semiconductor device having substantially the same size as an LSI chip.

  Conventionally, this type of package is called by various names such as μ-BGA, chip size package, and CSP, and various types of chip size packages have been developed.

  Such a second chip size package has been described in Non-Patent Document 1, for example.

  FIG. 11 is an overall cross-sectional view in which such a conventional chip size package is mounted on a ceramic substrate, and FIG. 12 is an enlarged cross-sectional view of part A in FIG.

  As shown in these drawings, an Au stud bump 3 is formed on an aluminum electrode 2 of an LSI chip 1 and is flip-chip bonded to a ceramic substrate 5 having a two-layer wiring.

  The upper wiring layer 7 and the lower wiring layer 8 of the ceramic substrate 5 are connected by a via hole 6. The ceramic substrate 5 and the stud bump 3 are electrically connected by an AgPd paste 4, and the AgPd paste 4 is electrically connected to the via hole 6 of the ceramic substrate 5. The LSI chip 1 and the ceramic substrate 5 are fixed with a sealing resin 9 injected therebetween. A land 8A is formed on the back surface of the ceramic substrate 5 and is electrically connected to the via hole 6. The land 8A is further connected to an external wiring.

Further, after wire bonding the LSI to the two-layer printed circuit board, the LSI mounting side is molded, and solder bumps are formed on the back surface of the package in the form of an area (for mounting, the solder bumps are directly soldered to the board).
Practical course "VLSI packaging technology (below)", published by Nikkei BP, May 31, 1993, page 174

  However, the conventional structure described above is expensive because a two-layer ceramic substrate is used to mount the LSI on the wiring board. Further, in order to remove the influence of the expansion coefficient and the like of the ceramic, the thickness of the ceramic needs to be 0.4 mm or less, and it is too thin as a ceramic for stable operation.

  Moreover, it has the following problems.

  (1) The adhesion between the printed board (epoxy resin in the above document) and the mold resin is poor, and peeling often occurs from the joint surface between the two.

  (2) Due to the difference in thermal expansion coefficient between the printed circuit board and the mold material, the package is warped during reflow, and reliable mounting becomes impossible.

  (3) Since the two-layer printed board is mounted on the wiring board, the price is high.

  (4) A mold for molding is required, and a mold release agent needs to be added to the molding material (adhesion between the mold resin and the substrate, wiring metal, etc. becomes worse).

  (5) The heat dissipation is not good.

  (6) Since a printed board (epoxy resin in the literature) is used, it is not used for applications exceeding the heat resistance of the printed board.

  There are a number of problems such as these, and while it is called a technology that follows the unachieved field of fine pitch QFP, its general practical use is still in danger.

  An object of the present invention is to provide a semiconductor device that eliminates the above-described problems, uses a single-layer wiring board, has a simplified structure, and can keep the price low.

In order to achieve the above object, the present invention provides
[1] A semiconductor device includes a first surface and a second surface opposite to the first surface, and a through-hole penetrating the first surface and the second surface is provided. The resin substrate, a metal wiring formed on the first surface of the resin substrate so as to partially cover the through hole, and a plurality of bump electrodes connected to the metal wiring. A semiconductor chip mounted on a region corresponding to the through hole on the first surface, an insulating sheet covering the metal wiring excluding a region connected to the bump electrode, and the second of the resin substrate And a solder ball connected to the metal wiring exposed in the through hole.

  [2] In the semiconductor device according to [1], a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.

  [3] In the semiconductor device according to [1], a portion of the metal wiring connected to the bump electrode is disposed in the vicinity of the periphery of the resin substrate.

  [4] The semiconductor device according to [1], wherein the resin substrate has substantially the same shape as the semiconductor chip.

  [5] In the semiconductor device, the first surface and a second surface opposite to the first surface are provided, and a through-hole penetrating the first surface and the second surface is provided. And a metal wiring formed on the first surface of the resin substrate and bent so that a part protrudes to the second surface side of the resin substrate through the through hole. A semiconductor device comprising: a plurality of bump electrodes connected to the metal wiring on the first surface; and a semiconductor chip mounted on the first surface side of the resin substrate.

  [6] The semiconductor device according to [5], wherein a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.

  [7] The semiconductor device according to [6], wherein a portion of the metal wiring connected to the bump electrode is disposed in the vicinity of the periphery of the resin substrate.

  [8] In the semiconductor device, the first surface and a second surface opposite to the first surface are provided, and a through-hole penetrating the first surface and the second surface is provided. A resin substrate, a metal wiring formed on the first surface of the resin substrate so as to partially cover the through-hole, and an insulation provided on a region corresponding to the through-hole of the metal wiring A sheet, a semiconductor chip mounted on a region corresponding to the through hole of the insulating sheet, and having a plurality of electrodes electrically connected to a portion of the metal wiring exposed from the insulating sheet; and the resin substrate A sealing resin for sealing the semiconductor chip so as to expose a part of the first surface, and the metal wiring formed on the second surface side of the resin substrate and exposed in the through hole And connected solder balls.

  [9] The semiconductor device according to [8], wherein the resin substrate is a single layer substrate.

  [10] The semiconductor device according to [8] or [9], wherein the resin substrate is a glass epoxy substrate.

  [11] The semiconductor device according to [8] or [9], wherein the resin substrate is a polyimide film.

  [12] The semiconductor device according to any one of [9] to [11], wherein the electrode of the semiconductor chip is connected to the metal wiring through a wire.

  According to the present invention, the following effects can be achieved.

  (1) A package can be manufactured without forming bumps on an LSI, and a single-layer wiring board is used, so that the price can be kept low.

  In addition, since the LSI is mounted on the single-layer wiring board and the package is manufactured, the size can be reduced and the price can be kept low.

  (2) Since the terminals are formed in the periphery of the LSI, in addition to the configuration of (1), a sufficient space can be secured between the terminals to ensure reliable connection.

  (3) Since the bumps formed on the single-layer wiring board are arranged within the area of the LSI, in addition to the configuration of (1), the degree of integration can be increased and the size can be reduced.

  (4) Since the LSI is mounted on the single-layer wiring board having a substantially LSI area and the package is manufactured, the size can be reduced and the price can be kept low.

  (5) Since the electrode part in which the tip or middle part of the metal wiring board protrudes from the opening of the single-layer wiring board is formed, the degree of integration can be increased and a low-cost chip size package can be obtained.

  Further, since no solder ball is used, the connection portion is hardly damaged. It is convenient for device evaluation before mounting.

  (6) Many small packages can be manufactured at a low cost by a simple process.

  (7) A small package (BGA) can be obtained without using a conventional printed circuit board.

  (8) Since a printed circuit board is not used, there is no worry about peeling between the epoxy resin and the circuit board. Since a so-called mold is not used, it is not necessary to add a release agent to the epoxy resin, and a coupling agent that improves the adhesion between the metal and the epoxy resin can be sufficiently used.

  Therefore, the connection between the resin and the metal and the resin and the LSI can be ensured, and a highly reliable small package can be obtained.

  Since the signal passing through the wire from the LSI pad reaches the solder ball for direct connection, the connection distance can be shortened and a small package with good electrical characteristics can be obtained.

  Since the number of man-hours is small and the materials are small, a low-priced package can be obtained.

  Less initial investment because no mold is required.

  Furthermore, since the metal piece has already been formed when the resin is cured, the occurrence of stress due to the difference in thermal expansion coefficient between the resin and the metal is extremely small.

  The semiconductor device of the present invention has a first surface and a second surface opposite to the first surface, and a through-hole penetrating the first surface and the second surface is provided. The resin substrate, a metal wiring formed on the first surface of the resin substrate so as to partially cover the through hole, and a plurality of bump electrodes connected to the metal wiring. A semiconductor chip mounted on a region corresponding to the through hole on the first surface, an insulating sheet covering the metal wiring excluding a region connected to the bump electrode, and the second of the resin substrate And a solder ball connected to the metal wiring exposed in the through hole.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a plan view of a single-layer resin substrate for mounting an LSI according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA 'of FIG. 1, and FIG. 3 is a small package having the resin substrate. FIG.

  Here, in order to mount the LSI, for example, a single-layer resin substrate is used. Although not necessarily limited to resin, resin substrates are currently inexpensive and desirable.

  In FIG. 1, reference numeral 100 denotes a resin substrate that supports a wiring layer, and a polyimide film or a glass epoxy substrate is used. In the case of a polyimide film, a thickness of about 50 μm is common. In the case of a glass epoxy substrate, a normal printed circuit board can be used.

  101, 102, 103,..., 108 are copper wiring boards electrically connected to the respective LSI electrodes by wire bonding (not necessarily copper), and a thickness of about 35 μm is often used. . 101 is connected to the land 111, 102 is connected to the land 112, and 103 is connected to the land 113. Others are the same.

  121 indicated by a dotted line in the land 111 is a hole formed in the resin portion of the resin substrate 100 (therefore, the copper land 111 is exposed on the back surface of the resin substrate 100).

  The holes 122, 123,..., 128 are the same, and are exposed on the back surface of the resin substrate 100. 130 corresponds to a die pad in the lead frame. As described above, the copper wiring boards 101, 102, 103,..., 108, the lands 111, 112, 113,..., 118, the die pad 130, and the die pad 130 are formed with openings 131 and the like.

  In order to better understand the resin substrate used in this embodiment, as shown in FIG. 2, the resin is also removed just below the die pad (metal plate, for example, copper plate) 130 to form an opening 131. The formation of the hole 131 is not always necessary in the present invention.

  As shown in FIG. 3, LSI 140 is die-bonded to die pad 130 of resin substrate 100 prepared in this way, and further, wire bonding is performed from each electrode of LSI 140 to copper wiring boards 101, 102, 103,. Do. Next, in order to protect the LSI 140, the wires 141, 142, etc., molding is performed with a molding resin 143.

  Finally, the solder balls 152 and 153 are placed on the exposed surfaces of the holes 121, 122, 123, 124,. When this LSI requires heat dissipation, a die pad (metal) 151 such as solder can be installed on the back surface of the die pad 130 and thermally connected to the wiring board to increase the heat dissipation effect.

  In FIG. 3, the molding resin 143 is used for molding, but in that case, molding may be performed on the entire surface. It is also possible to only pot a so-called potting agent. 141 is a wire bonded to the copper wiring board 104 from the electrode of the LSI 140, and 142 is a wire bonded to the copper wiring board 108 from the electrode of the LSI 140.

  The solder ball 152 is connected to the land 114, and the solder ball 153 is connected to the land 118.

  4 is a plan view of a single-layer resin substrate for mounting an LSI according to a second embodiment of the present invention, and FIG. 5 is a cross-sectional view of a small package in which the LSI is mounted on the resin substrate (BB ′ in FIG. 4). FIG. 6 is a cross-sectional view corresponding to a line. Hereinafter, the description of the same part as the first embodiment is omitted.

  In the first embodiment, the solder balls 152 and 153 for connecting to the wiring board exist around the LSI 140. However, in order to further reduce the package size, in the second embodiment, most of the solder balls are placed directly under the LSI.

  As shown in these drawings, the lands 211, 214, and 218 at the tip of the copper wiring board 201 exist directly under the LSI 240. 221, 224, and 228 are holes formed in the resin in the land 211 (similar to the first embodiment). The copper wiring board 202 is not directly under the LSI 240 in this embodiment. A land 214 connected to the copper wiring board 204 exists immediately below. The same applies hereinafter. A dashed line 231 in FIG. 4 is an insulating sheet applied on the copper wiring boards 201, 203, 204, 205, 207 and 208.

  After the LSI 240 is die-bonded to the insulating sheet 231 of this substrate, and then wire bond and mold resin 243 are attached, solder balls are inserted into the holes 228 and 224 from the resin side of the resin substrate 200 (described as the back surface in the present invention). 238 and 234 are arranged. In FIG. 5, reference numerals 241 and 242 denote wires.

  FIG. 6 is a plan view of a single-layer resin substrate for mounting an LSI according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view of a small package in which the LSI is mounted on the resin substrate (CC ′ in FIG. FIG.

  In this embodiment, bumps are formed on an LSI to be mounted, and are first mounted on a substrate by a flip chip method to form a chip size package, and then the chip size package is mounted on a circuit board.

  In FIG. 6, reference numeral 300 denotes a resin substrate as described above. For example, a metal plate is attached to an insulating layer, and this metal plate is processed and formed into a desired shape by etching or the like. An LSI 350 is mounted in a portion surrounded by a dotted line. Reference numerals 301, 302, 303, 304,... 308 are formed metal wiring boards made of copper or the like, and wires are bonded from these electrodes of the LSI 350 to this portion.

  .., 318 are lands electrically connected to the metal wiring boards 301, 302, 303, 304,... 308, respectively, and are installed inside the dotted line 350. ... 328 are holes formed only in the insulating layers in the lands 311, 312, 313, 314,... 318, and a copper plate is exposed on the side where the LSI is not mounted.

  A one-dot broken line 341 is an insulating sheet bonded to the substrate, and is installed so as to exist inside the lands 311, 312, 313, 314,.

  FIG. 7 shows a state in which the LSI 350 is flip-chip mounted on such a substrate, and is a cross-sectional view taken along the line CC ′ of FIG. In the figure, reference numerals 344 and 348 denote solder balls formed on the LSI 350, and solder balls 334 and 338 are installed in the holes 324 and 328. Resin mold if necessary.

  Next, a fourth embodiment of the present invention will be described.

  In the fourth embodiment, a method will be described in which a solder ball or the like is not used for electrical connection between the chip size package of the present invention and an external circuit, and a part of the wiring board of the package is processed to form a connection terminal.

  8 is a plan view of a single-layer resin substrate for mounting an LSI according to a fourth embodiment of the present invention, FIG. 9 is a sectional view taken along the line DD 'of FIG. 8, and FIG. 10 is a small package having the resin substrate. FIG.

  As shown in these figures, reference numeral 400 denotes an insulating substrate that supports the wiring board, and the LSI is connected to the wiring boards 401, 402, 403,. Reference numerals 421, 422, 423, 424,... 428 are holes formed in the insulating plate. Reference numeral 411 denotes a terminal connected to the wiring board 401 and connected to an external circuit. Reference numeral 414 is a terminal connected to the external board connected to the wiring board 404. Similarly, reference numeral 418 is a terminal connected to the external circuit connected to the wiring board 408.

  The terminal 411 floats in the air at the hole 421. The terminal 414 floats in the air at the hole 424. The terminal 418 is suspended in the hole 428. Others are the same. Such a structure can be easily produced by ordinary techniques. For example, a metal plate may be attached to an insulating substrate in which holes are formed in advance and etched from the surface.

  Next, these terminals floating in the air are processed. This processing can also be easily realized by ordinary means. The terminals 414 and 418 are modified so as to be easily connected to an external circuit.

  FIG. 10 shows a state where the LSI is connected, but in order to clarify the main part, the insulating sheet and the mold resin are not shown and are omitted.

  Reference numerals 454 and 458 denote bumps formed on the LSI 450 and are connected to the wiring boards 404 and 408.

  Furthermore, the following usage forms can be taken.

  (1) In the above embodiment, an example in which one LSI is mounted on a (resin) substrate has been described for ease of explanation. However, it is possible to mount a plurality of LSIs, and it is also possible to mount chip parts and the like at the same time. It is.

  (2) After mounting a plurality of LSI and chip component groups on a substrate, each may be cut off during or at the end of the process.

  (3) When the solder balls are installed, the description of the solder resist is not performed, but it is because the insulating layer portion of the substrate also serves as the resist layer, and the solder resist layer may be applied again. .

  (4) In the second embodiment, an insulating sheet was used. This insulating sheet can be substituted with an adhesive for die bonding LSI.

  (5) In the third embodiment, bumps are used, but the bumps may be gold, copper or the like, or lead-tin solder. In addition, the insulating sheet has a role of a solder dam that prevents the bump from melting and flowing out at the time of connection, and was not particularly necessary when gold, copper, or the like was used.

  (6) In the fourth embodiment, the LSI is flip-chip mounted, but is not limited to this mounting method, and may be another mounting method such as wire bond mounting. Further, the connection place with the external circuit does not always have to be directly under the LSI.

  Furthermore, although the explanation has been made that the tip portion of the wiring of the single-layer wiring board is processed into the connection terminal, it is not always necessary to be at the tip, and the middle portion is floated on the opening (through hole) and processed. It may be.

  Next, a fifth embodiment of the present invention will be described.

  FIGS. 13 to 18 are block diagrams showing a fifth embodiment of the present invention. FIG. 13 is a perspective view showing an LSI mounting board according to the fifth embodiment of the present invention. FIG. FIG. 15 is a plan view of the LSI mounting substrate, and FIG. 16 is a sectional view of a manufacturing process of a small package showing a fifth embodiment of the present invention.

In FIG. 13, reference numeral 500 denotes a metal substrate such as a Kovar plate or a copper plate, and has a thickness of 30 to 100 μm. LSIs 511, 512, 513, 514, 515, 516,... Are regularly die-bonded to the metal substrate 500. For example, the interval L ₁ between the LSI 511 and the LSI 512 and the interval L ₂ between the LSI 511 and the LSI 514 are known. The angle between each other is also known. Reference numerals 501, 502,... Are reference holes for bonding. The positional relationship between the reference holes 501, 502,... And each LSI is known.

  In addition, 521, 522, 523,..., 531, 536 are wires stretched from the respective pads (electrodes) of the LSI 511 to the metal substrate 500. These are due to ordinary wire bonds. Similarly, 541, 542, 543,..., 556 are wires that connect each pad of the LSI 512 and the metal substrate 500, and 561,... 563, ..., 571 are wires bonded from the LSI 514 to the metal substrate 500.

  A circular portion 610 indicated by a dotted line indicates a position on the metal substrate 500, and a wire 521 is connected to the circular portion 610. Similarly, a wire 522 is connected to the circular part 611, and a wire 523 is connected to the circular part 612. A wire 563 is connected to the circular portion 631, and a wire 571 is connected to the circular portion 632. Each circle has a known position.

  As described above, after the LSI was die-bonded and wire-bonded to the metal substrate 500, a resin (here, epoxy resin) was deposited on the entire surface. In FIG. 14, reference numeral 650 denotes a resin, and the resin 650 is heated and cured while being pressed.

  In this step, the metal substrate 500 was set in a hot press and pressed from the surface (this step is not shown because it is easy to understand).

  In addition, since a mold is not used this time, a coupling agent for improving the adhesion between the resin 650 and the metal substrate 500, and the resin 650 and the LSIs 511, 512, 513,. . Further, no release agent was added to the resin 650.

  Depending on the type of metal, particularly its thermal expansion coefficient, thickness, and dimensions, stress may occur between the resin and the allowable value, which may lead to undesirable conditions. A method of cutting the metal substrate 500 in advance and allowing the resin to shrink is also effective.

  A thin epoxy sheet was inserted between the hot press and the resin 650. When the sheet was bonded to the resin 650, the sheet was left as it was, and no peeling operation was performed.

During the pressing, a spacer was inserted between the metal substrate 500 and the pressing plate, and cured at a pressure of 15 kg / cm ² and a temperature of 80 ° C. for a pressing time of 1 hour. The thickness of the resin can be controlled by the dimensions of the spacers, and surface unevenness due to the presence of LSI or the like was not generated by pressure curing.

  Next, an attempt was made to etch the metal substrate 500 into a desired shape. Since the metal substrate 500 uses a normal metal, an existing technique can be used for the etching process. For example, a dry film is deposited on the surface of the metal substrate 500, and after development using a mask, unnecessary portions are removed with an etching solution. Reference holes 501, 502, etc. were used for alignment. In the case where the metal substrate 500 is copper, a good etching solution using iron chloride, tin chloride or the like has been developed. The same applies to other metals such as Kovar.

  FIG. 15 shows the metal substrate after etching. Reference numeral 511A denotes a portion where the LSI 511 of FIG. 1 is mounted on the back surface thereof, which corresponds to a die pad of the lead frame. In FIG. 13, the position is indicated by a dotted line around the LSI 511. The same applies to 512A, 513A,.

  A wire 521 (see FIG. 13) is connected to the back surface of the circular portion 610. A wire 522 (see FIG. 13) is connected to the back surface of the circular portion 611. The same applies to other circular portions.

  FIG. 16 is a process cross-sectional view after etching the metal substrate. That is, it is a cross-sectional view along the line AA ′ of FIG.

  First, as shown in FIG. 16A, the LSIs 511 and 514 are sealed with a resin 650.

  Next, as shown in FIG. 16B, in order to connect the solder balls to all the circular portions described above, a solder resist 701 is coated on the portions other than the connection portions of these circular portions.

  Next, as shown in FIG. 16 (c), after forming solder balls 702 and 703 by a normal solder ball forming method, as the last step, the dashed lines C1, C3,..., C2, C4 shown in FIG. , C6, C8,...

  Next, in order to improve the heat radiation of the LSI, as shown in FIG. 16 (d), it is also possible to improve the thermal contact with the substrate by applying solder or the like to 511A, 512A, 513A,. It is. Here, a situation in which the heat conduction good material 704 is provided together with the solder balls is shown.

  FIG. 17 is a plan view of an LSI mounting board according to the sixth embodiment of the present invention.

  In FIG. 17, 1000 is a support, on which metal pieces (rectangular parts) 1210, 1220, 1230, 1240, 1250, 1260 and metal pieces (circular parts) 1010, 1020,... 1050,. ing. As an example of the manufacturing method, reference numeral 1000 denotes a Kapton tape coated with an adhesive as a support. A metal substrate is attached to the tape, and an arrangement of metal pieces as shown in the figure is obtained by etching.

  Next, wire bonding is performed to the metal pieces 1010, 1020,..., 1050, from the LSI pads (electrodes) obtained by die bonding the LSI to the metal pieces 1210 in the same manner as in FIG. The same applies to the metal pieces 1220, 1230,.

  Further, after sufficiently covering the entire surface of the epoxy resin, as already described in the first embodiment, it is cured by pressing and heating with a hot press. Next, similarly, as shown in the fifth embodiment, the solder resist is applied and the solder balls are installed, and thereafter, C1, C3, C5,. Cutting positions such as C6 and C8.

  18 is a plan view of an LSI mounting board according to a seventh embodiment of the present invention, and FIG. 19 is a cross-sectional view taken along line FF ′ of FIG. Here, description will be made with reference to FIG. 18, but the same applies to other small package regions. In this embodiment, the metal piece also serves as a wiring.

  In this figure, a wire from an LSI pad is bonded to the metal piece 4030, but no solder ball is placed on the back surface of the metal piece 4030. The metal piece 4030 reaches the metal piece 4032 through the wiring 4031 connected thereto. The wiring 4031 passes directly under the LSI. A solder ball for mounting is formed on the back surface of the metal piece 4032.

  Further, a wire from the LSI pad is also bonded to the metal piece 4060, but reaches the metal piece 4062 through the wiring 4061, and a solder ball is formed on the back surface of the metal piece 4062. Similarly, a wire is connected to the metal piece 4110, but no solder ball is formed on the back surface of the metal piece 4110, and reaches the metal piece 4112 through the wiring 4111 connected to the metal piece 4110. Is installed.

  Here, the work of obtaining the shape of the metal piece may be before the LSI is mounted or after the resin is cured. In order to fix the LSI, the wirings 4111, 4031, etc. can be designed to be wide, and metal pieces that are not electrically connected are placed in locations corresponding to the regions 4210 ′, 4220 ′,. It may be done (not shown).

  19, 4100 is a solder resist, 4406 and 4416 are wires, 4514 is an LSI, and 4650 is a mold resin.

  The epoxy resin mold, the application of the solder mask, the installation of the solder balls, the cutting of the resin, etc. are exactly the same as in the fifth and sixth embodiments. FIG. 19 shows a cross-section of the main part at a location corresponding to the line FF ′ in FIG. 18 after the completion of all the steps. In FIG. 19, reference numerals 4060 and 4061 denote solder balls.

  20 to 22 are configuration diagrams showing an eighth embodiment of the present invention. FIG. 20 is a perspective view of the LSI mounting board, FIG. 21 is a rear view of FIG. 20, and FIG. FIG.

  In this embodiment, a so-called multichip module system will be described.

  The LSI 4020, the LSI 4030, and the chip component 4040 are mounted on the BGA and include the multilayer wiring 4500.

  In the process of this embodiment, the LSI 4020, the LSI 4030, and the chip component 4040 are die-bonded at predetermined locations on the metal plate 4010 (the metal plate 4010 is the same as that in the fifth embodiment, and is not shown in this embodiment). . The die bonding is performed as shown in FIG. However, in this process, the substrate is 4010, and the wiring pattern as shown in the figure has not yet been formed. The mounting work is done as it is formed. This die bonding process can be carried out by a general connection technique.

  Next, wire bonding is performed from the pads of the LSI 4020 and the LSI 4030 to the metal plate 4011 at predetermined positions. The procedure for this wire bond is the same as in the fifth embodiment. Further, the multilayer wiring portion 4500 is formed by a bonding technique or the like.

  The order of bonding of LSI, chip parts, and wires is not particular.

  These LSI 4020 and LSI 4030, chip component 4040, multilayer wiring 4500, and a large number of bonded wires are regularly formed on a metal plate 4010 as shown in FIG.

  Next, as in the fifth embodiment, an epoxy resin 4650 is deposited on the entire surface, and heated and pressed by a hot press to cure the epoxy resin. Further, this is also etched from the exposed side of the metal plate 4010 in the same process as in the fifth embodiment. FIG. 21 shows the state after the etching process.

  In FIG. 21, LSIs 4020 and 4030 are connected to the opposite surface of 4071 and 4072. Reference numeral 4040 denotes a chip component. In addition, the substrate 4010 is etched to form metal pieces 4401, 4402, 4403, 4404, 4405, 4406,.

  In this BGA, the solder balls for connection are installed at both ends of the completed module. Based on this policy, a soldering resist was applied by an established method, and then solder balls were installed. Further, cutting was performed along the dashed lines C1, C3, C5,..., C2, C4, C6, C8.

  As shown in FIG. 22, solder balls 4031 and 4033 and a solder resist 4100 are formed in the cut small package.

  FIG. 23 is a plan view of an LSI mounting substrate according to the ninth embodiment of the present invention, and FIG. 24 is a cross-sectional view (cross-sectional view taken along the line H-H 'in FIG. 23) of the small package according to the ninth embodiment of the present invention. .

  In this embodiment, BGA connection solder balls are also installed directly under the LSI.

  A plurality of LSIs are die-bonded to a metal substrate (not shown) as in the fifth embodiment, but before the die bonding, insulating sheets 5210, 5220,..., 5260 are bonded to the place where the LSIs are installed. (FIG. 23 is a diagram after the metal piece 1010 is etched, but the relationship between the LSI 1021 and the insulating sheet 5210 can be understood from this diagram).

  After the die bonding of the LSI, wire bonding is performed from each pad of the LSI to each of the metal pieces 1010, 1020, 1030, 1040, 1050,... Shown in FIG. This process is almost the same as the first embodiment. Further, epoxy resin is deposited (not shown), and the resin is cured by heating and pressing.

  Next, the metal plate 4010 is etched as shown in FIG. In this figure, a wiring 1021 is connected to a metal piece 1020 (wire is connected to the back surface), and further reaches a metal piece 1022 directly below the LSI 1021. Solder balls are installed on the metal piece 1022 later. The same applies to the metal piece 1122.

  After the solder balls are installed, cutting is performed along the dashed lines C1, C3, C5,..., C2, C4, C6, C8,.

  Furthermore, the following usage forms can be taken.

  In the fifth embodiment, the metal substrate is made of copper or Kovar. However, the present invention is not limited to these metals, and copper alloys or other metals can be used, and surface plating is also specified. It is not a thing.

  The same applies to the other examples of the metal substrate. Further, the thickness is not limited.

  In the embodiments of the present invention, the mounting of the LSI has been described by wire bonding, but it is needless to say that it can be performed by other methods such as a flip chip method.

  Moreover, it demonstrated as an epoxy resin as a molding material which molds LSI etc. Depending on the situation used, for example, heat-resistant epoxy resin, polyimide resin, etc. should be used in an atmosphere that requires heat resistance.

  In the fifth embodiment, a resin film is inserted during pressing between the hot press and the resin, but this prevents adhesion between the cured resin and the press, and the same applies to the other embodiments. Paper or the like may be used instead of the resin film. Often unnecessary.

  In the above embodiment, it has been described that the module is connected to the outside with solder balls. However, depending on the situation, it is possible to connect lead wires and lead terminals instead of solder balls, and a mounting method similar to a so-called leadless package is also possible.

  Since it is configured as described above, the connection point by the solder ball can be installed at the most efficient place.

  In the conventional method using the lead frame, the LSI pad and the package pin correspond to each other as they are, so there is no degree of freedom in design, and as a result, the wiring of the printed circuit board on which the LSI is mounted often needs to be largely routed. Also, even with BGA, the total number of printed circuit boards increased when trying to change the arrangement inside, leading to an increase in price.

  In the structure of the present invention, the arrangement of the connection points can be easily changed.

  Furthermore, it is possible to obtain an MCM (multichip module) that does not use a printed circuit board. In recent years, with the development of electronic devices, for example, there is a large demand for installing a low-cost MCM in the vicinity of an automobile engine. A conventional module comprising an FR-4 substrate has a problem in heat resistance and cannot be mounted.

  Furthermore, the MCM according to the present invention can sufficiently cope.

  In addition, it is easier to manufacture than a normal BGA. Further, since no printed circuit board is used, warpage is unlikely to occur during mounting, which is convenient for mounting.

  Further, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

  The semiconductor device of the present invention can be used as an LSI package that can keep the price low.

It is a top view of the single layer resin substrate for mounting LSI which shows 1st Example of this invention. It is AA 'sectional drawing of FIG. It is sectional drawing of the small package which has a resin substrate which shows 1st Example of this invention. It is a top view of the single layer resin substrate for mounting LSI which shows 2nd Example of this invention. It is a cross section (cross section corresponding to the BB 'line of FIG. 4) of the small package which mounted LSI on the resin substrate which shows 2nd Example of this invention. It is a top view of the single layer resin substrate for mounting LSI which shows the 3rd example of the present invention. It is a cross section (cross section corresponding to the CC 'line of FIG. 6) of the small package which mounted LSI on the resin substrate which shows 3rd Example of this invention. It is a top view of the single layer resin substrate for mounting LSI which shows 4th Example of this invention. It is DD 'sectional drawing of FIG. It is sectional drawing of the small package which has a resin substrate which shows 4th Example of this invention. It is a whole sectional view in which a conventional chip size package is mounted on a ceramic substrate. It is the A section expanded sectional view of FIG. It is a perspective view which shows the mounting substrate of LSI which shows 5th Example of this invention. It is the EE 'sectional view taken on the line of FIG. It is a top view of the mounting substrate of LSI which shows 5th Example of this invention. It is manufacturing process sectional drawing of the small package which shows 5th Example of this invention. It is a top view of the mounting substrate of LSI which shows 6th Example of this invention. It is a top view of the mounting substrate of LSI which shows 7th Example of this invention. It is the FF 'sectional view taken on the line of FIG. It is a perspective view of the mounting substrate of LSI which shows the 8th Example of this invention. FIG. 21 is a rear view of FIG. 20. It is the GG 'sectional view taken on the line of FIG. It is a top view of the mounting substrate of LSI which shows 9th Example of this invention. It is a cross section (cross section corresponding to the HH 'line of FIG. 23) of the small package which shows 9th Example of this invention.

Explanation of symbols

100, 200, 300 Resin substrate 101-108, 201-208 Copper wiring board 111-118, 211, 214, 218, 311-318 Land 121-128, 221, 224, 228, 321-328, 421-428 Hole 130 , 151, 511A, 512A, 513A,... 516A Die pad 131 opening 140, 240, 350, 450, 511-516, 1021, 4020, 4030, 4514 LSI
141, 142, 241, 242, 521, 522, 523, ... 531, 536, 541, 542, 543, ..., 556, 561, ... 563, ... 571, 4406, 4416 Wires 143, 243, 4650 Mold resin 152, 153, 234, 238, 334, 338, 702, 703, 4031, 4033 Solder balls 231, 341, 5210, 5220,..., 5260 Insulating sheets 301-308 Metal wiring boards 344, 348, 454, 458 Bumps 400 Insulating substrate 401 408 wiring board 411, 414, 418 terminal 500 metal substrate 501, 502 ... reference hole 610, 611, 612, 614, 620, 621, 631, 632 circular portion 650, 4650 resin 701, 4100 solder resist 704 good thermal conductivity material 1000 Puton tape (support)
1010, 1020, 1022, 1050, 1160, 1210, 1220, 1230, 1240, 1250, 1260, 4030, 4032, 4060, 4062, 4110, 4112, 4401, 4402, ... 4406 Metal pieces 1031, 1061, 1111, 4031 4061, 4111 wiring 4011 metal plate 4040 chip component 4500 multilayer wiring

Claims (12)

(A) a resin substrate having a first surface and a second surface opposite to the first surface and provided with a through-hole penetrating the first surface and the second surface; ,
(B) a metal wiring formed on the first surface of the resin substrate so as to partially cover the through hole;
(C) a semiconductor chip including a plurality of bump electrodes connected to the metal wiring and mounted on a region corresponding to the through hole on the first surface of the resin substrate;
(D) an insulating sheet covering the metal wiring excluding a region connected to the bump electrode;
(E) a solder ball formed on the second surface side of the resin substrate and connected to the metal wiring exposed in the through hole;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.   2. The semiconductor device according to claim 1, wherein a portion of the metal wiring connected to the bump electrode is disposed in the vicinity of the periphery of the resin substrate.   2. The semiconductor device according to claim 1, wherein the resin substrate has substantially the same shape as the semiconductor chip. (A) a resin substrate having a first surface and a second surface opposite to the first surface and provided with a through-hole penetrating the first surface and the second surface; ,
(B) a metal wiring formed on the first surface of the resin substrate and bent so as to partially protrude toward the second surface of the resin substrate through the through hole;
(C) a semiconductor chip including a plurality of bump electrodes connected to the metal wiring on the first surface and mounted on the first surface side of the resin substrate;
A semiconductor device comprising:   6. The semiconductor device according to claim 5, wherein a portion of the metal wiring corresponding to the through hole is located in a region of the resin substrate where the semiconductor chip is mounted.   7. The semiconductor device according to claim 6, wherein a portion of the metal wiring connected to the bump electrode is disposed in the vicinity of the periphery of the resin substrate. A resin substrate having a first surface and a second surface opposite to the first surface and provided with a through-hole penetrating the first surface and the second surface;
A metal wiring formed on the first surface of the resin substrate so that a part thereof covers the through hole;
An insulating sheet provided on a region corresponding to the through hole of the metal wiring;
A semiconductor chip mounted on a region corresponding to the through hole of the insulating sheet and having a plurality of electrodes electrically connected to a portion of the metal wiring exposed from the insulating sheet;
A sealing resin for sealing the semiconductor chip so as to expose a part of the first surface of the resin substrate;
A solder ball formed on the second surface side of the resin substrate and connected to the metal wiring exposed in the through hole.   9. The semiconductor device according to claim 8, wherein the resin substrate is a single layer substrate.   10. The semiconductor device according to claim 8, wherein the resin substrate is a glass epoxy substrate.   10. The semiconductor device according to claim 8, wherein the resin substrate is a polyimide film.   12. The semiconductor device according to claim 8, wherein the electrode of the semiconductor chip is connected to the metal wiring via a wire.

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