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JP2005277115A - Chip capacitor mounting structure and printed wiring board - Google Patents

Chip capacitor mounting structure and printed wiring board Download PDF

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Publication number
JP2005277115A
JP2005277115A JP2004088301A JP2004088301A JP2005277115A JP 2005277115 A JP2005277115 A JP 2005277115A JP 2004088301 A JP2004088301 A JP 2004088301A JP 2004088301 A JP2004088301 A JP 2004088301A JP 2005277115 A JP2005277115 A JP 2005277115A
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Japan
Prior art keywords
chip capacitor
mounting
wiring board
printed wiring
bga package
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Pending
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Japanese (ja)
Inventor
Yukio Mizoe
幸生 溝江
満 ▲高▼平
Mitsuru Takahira
Akira Kamisaka
晃 神坂
Takashi Matsumoto
隆 松本
Atsumi Kawada
篤美 川田
Atsushi Tsunoda
淳 角田
Takayuki Ono
孝之 尾野
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. <P>SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、プリント配線板に実装するＢＧＡパッケージを有する半導体素子の電源およびグランドノイズ低減に使用されるチップコンデンサの実装構造および前記実装用プリント配線板に関するものである。   The present invention relates to a power supply for a semiconductor element having a BGA package mounted on a printed wiring board and a mounting structure of a chip capacitor used for ground noise reduction, and the printed wiring board for mounting.

プリント配線板にＢＧＡパッケージを有する半導体素子を実装する場合、パッケージ高速動作の妨げとなる電源およびグランドノイズを極力低減することが必要となる。近年、電子機器の小型化に伴い、プリント配線板組立においても高密度実装化が進んでいる。そのため、電子部品であるチップコンデンサも小型化により、１６０８（横１．６ｍｍ、縦０．８ｍｍ）サイズが主に使用されているが、静電容量は０．１~１．０μＦ程度であるためパッケージ実装面の近傍に配置されるのが一般的である。   When a semiconductor element having a BGA package is mounted on a printed wiring board, it is necessary to reduce as much as possible power supply and ground noise that hinder high-speed operation of the package. In recent years, with the miniaturization of electronic devices, high-density mounting is also progressing in printed wiring board assembly. For this reason, chip capacitors, which are electronic components, are also mainly used in the size of 1608 (1.6 mm in width, 0.8 mm in length) due to miniaturization, but the capacitance is about 0.1 to 1.0 μF. Generally, it is arranged near the package mounting surface.

図８に従来のチップコンデンサ実装構造を示す。１はＢＧＡパッケージ、２は実装に必要なエリア、３はチップコンデンサ、４はチップコンデンサ搭載用パッドである。   FIG. 8 shows a conventional chip capacitor mounting structure. 1 is a BGA package, 2 is an area required for mounting, 3 is a chip capacitor, and 4 is a chip capacitor mounting pad.

プリント配線板に実装されるＢＧＡパッケージ１の高性能化、高周波数化に伴いＢＧＡパッケージ１の近傍には１６０８サイズのチップコンデンサ３を相当数配置する必要がある。チップコンデンサ３の個数が増えることによりＢＧＡパッケージ１から配置位置までの距離が遠くなり、チップコンデンサ３からＢＧＡパッケージ１までの電源およびグランドの回路接続距離が長くなる。
これに伴い、式１に示す抵抗ＲやインダクタンスＬが増加し、インピーダンスＺ0が高くなる。 As the performance and frequency of the BGA package 1 mounted on the printed wiring board increases, it is necessary to dispose a considerable number of 1608 size chip capacitors 3 in the vicinity of the BGA package 1. As the number of chip capacitors 3 increases, the distance from the BGA package 1 to the arrangement position becomes longer, and the power and ground circuit connection distance from the chip capacitor 3 to the BGA package 1 becomes longer.
Along with this, the resistance R and the inductance L shown in Equation 1 increase, and the impedance Z0 increases.

（式１）

Figure 2005277115
Ｚ0：インピーダンス，Ｒ：抵抗，ｆ：周波数，Ｌ：インダクタンス，Ｃ：静電容量
前述のノイズはインピーダンスＺ0が高くなることにより増加し、実装的にみると回路接続距離が長くなることにより、電源およびグランドのノイズが大きくなるという問題となる。また、現状の構造ではチップコンデンサ３の実装に必要なエリア２は、ＢＧＡパッケージ１の面積を１とした場合、２倍程度必要であり単位面積当りの搭載個数は０．０６個／ｍｍ２であった。 (Formula 1)
Figure 2005277115
Z0: Impedance, R: Resistance, f: Frequency, L: Inductance, C: Capacitance The noise described above increases as the impedance Z0 increases. In addition, there is a problem that the noise of the ground becomes large. In the current structure, the area 2 necessary for mounting the chip capacitor 3 is about twice as long as the area of the BGA package 1 is 1, and the number of mounted units per unit area is 0.06 / mm 2 . there were.

特開２００３−５１５６５JP 2003-51565 A 特開２００１−１５６２１１JP 2001-156 211 A

本発明は、上記問題点より、チップコンデンサの実装面積を抑え、電源およびグランドの電気的なノイズを低減するのに適したチップコンデンサ実装構造及び前記実装用プリント配線板パッド構造を提供することを目的とする。   In view of the above problems, the present invention provides a chip capacitor mounting structure and a printed wiring board pad structure for mounting which are suitable for reducing the mounting area of the chip capacitor and reducing electric noise of the power supply and the ground. Objective.

上記目的を達成するために、本発明は、ＢＧＡパッケージをはんだ接続するプリント配線板において、前記ＢＧＡパッケージの搭載箇所裏面に形成された電源およびグランド用スルホールパッド上にチップコンデンサをはんだ接続する実装構造としたものである。   In order to achieve the above object, according to the present invention, a printed wiring board for soldering a BGA package has a mounting structure in which a chip capacitor is solder-connected on a power and ground through-hole pad formed on the back surface of the BGA package. It is what.

本発明によればＢＧＡパッケージをはんだ接続するプリント配線板の搭載箇所裏面の電源およびグランド用スルホールパッド上へチップコンデンサをはんだ接続することにより、チップコンデンサの実装面積を縮小し、電源およびグランドの回路接続距離が短くなり、電源およびグランドノイズを低減できる。   According to the present invention, the mounting area of the chip capacitor is reduced by solder-connecting the chip capacitor onto the power supply and ground through-hole pads on the back surface of the printed wiring board where the BGA package is solder-connected, thereby reducing the power supply and ground circuit. Connection distance is shortened, and power and ground noise can be reduced.

以下、本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１に本発明の実施例１におけるチップコンデンサ搭載図、図２に図１における断面図であるチップコンデンサ実装構造概略図を示す。１はＢＧＡパッケージ、３はチップコンデンサ、５はプリント配線板、６はスルホールパッド、７ははんだボール接続端子、８はＢＧＡパッケージ実装箇所裏面である。   FIG. 1 shows a chip capacitor mounting diagram in Embodiment 1 of the present invention, and FIG. 2 shows a chip capacitor mounting structure schematic diagram which is a cross-sectional view in FIG. Reference numeral 1 denotes a BGA package, 3 denotes a chip capacitor, 5 denotes a printed wiring board, 6 denotes a through-hole pad, 7 denotes a solder ball connection terminal, and 8 denotes a back surface of the BGA package mounting portion.

図において、ＢＧＡパッケージ１の電源およびグランドノイズ低減のために実装するチップコンデンサ３のはんだ接続箇所を従来のＢＧＡパッケージ１搭載面近傍から、ＢＧＡパッケージ実装箇所裏面８の電源およびグランド用スルホールパッド６上へ直接実装する構造へ変更した。ここでチップコンデンサ３を接続するスルホールパッド６は電源およびグランド用であり、本発明の実施の形態１においては、接続するチップコンデンサ３を従来の１６０８サイズより１００５サイズに小型化したものを使用した。チップコンデンサ３についてはパッドの大きさを変えることにより更に小型サイズ、例えば０６０３サイズも使用可能である。   In the figure, the power supply of the BGA package 1 and the solder connection location of the chip capacitor 3 mounted for ground noise reduction from the vicinity of the conventional BGA package 1 mounting surface to the power supply and ground through hole pad 6 on the back surface 8 of the BGA package mounting location. Changed to a structure that directly implements Here, the through-hole pad 6 to which the chip capacitor 3 is connected is for power supply and ground, and in the first embodiment of the present invention, the chip capacitor 3 to be connected is made smaller than the conventional 1608 size to 1005 size. . For the chip capacitor 3, a smaller size, for example, 0603 size, can be used by changing the size of the pad.

これにより、従来のＢＧＡパッケージ１近傍へのチップコンデンサ３の実装がなくなり、チップコンデンサ３の実装に必要な面積を大幅に縮小することができた。図９に従来品との単位面積あたりのチップコンデンサ搭載数比較グラフを示す。本発明において単位面積あたりの搭載数は０．３６個／ｍｍ２となり、従来品の０．０６個／ｍｍ２と比較してチップコンデンサ３の搭載に必要な面積を１／６に低減することができ、今までチップコンデンサ３を搭載していたエリアに配線を実施することや、他の部品を実装することが可能となる。また、チップコンデンサ３の実装位置がＢＧＡパッケージ１直下のスルホールパッド上となったことから、従来構造より電源およびグランドの回路接続距離が短くなり、配線の抵抗、インダクタンスを低減でき、電源およびグランドノイズを低減できる効果がある。 Thereby, the mounting of the chip capacitor 3 in the vicinity of the conventional BGA package 1 is eliminated, and the area required for mounting the chip capacitor 3 can be greatly reduced. FIG. 9 shows a comparison graph of the number of chip capacitors mounted per unit area with the conventional product. In the present invention, the number of mounted units per unit area is 0.36 / mm 2 , and the area required for mounting the chip capacitor 3 is reduced to 1/6 compared with 0.06 / mm 2 of the conventional product. Thus, it is possible to carry out wiring in an area where the chip capacitor 3 has been mounted so far, and to mount other components. In addition, since the mounting position of the chip capacitor 3 is on the through-hole pad immediately below the BGA package 1, the circuit connection distance between the power source and the ground is shorter than in the conventional structure, the wiring resistance and inductance can be reduced, and the power source and ground noise are reduced. Is effective.

図３，４に、本発明の実施例１であるプリント配線板のパッド構造を示す。３はチップコンデンサ、６はスルホールパッド、９はソルダレジスト、１０はスルホールである。図３においてスルホールパッド６は角型形状であり、スルホールパッド６周辺部にソルダレジスト９が形成された構造である。また、図４のスルホールパッドは丸形状であり、ソルダレジスト９は図３と同様に形成された構造である。   3 and 4 show a pad structure of a printed wiring board that is Embodiment 1 of the present invention. 3 is a chip capacitor, 6 is a through-hole pad, 9 is a solder resist, and 10 is a through-hole. In FIG. 3, the through-hole pad 6 has a square shape, and has a structure in which a solder resist 9 is formed around the through-hole pad 6. 4 has a round shape, and the solder resist 9 has a structure formed in the same manner as in FIG.

本発明の実施例２におけるチップコンデンサ搭載図およびチップコンデンサ実装構造概略図は実施例１と同じであり、また、効果についても同様であるため説明を省略する。   The chip capacitor mounting diagram and the chip capacitor mounting structure schematic diagram in the second embodiment of the present invention are the same as those in the first embodiment, and the effects are also the same, so the description is omitted.

図５に本発明の実施例２におけるプリント配線板パッド構造を示す。３はチップコンデンサ、６はスルホールパッド、９はソルダレジスト、１０はスルホールである。   FIG. 5 shows a printed wiring board pad structure according to the second embodiment of the present invention. 3 is a chip capacitor, 6 is a through-hole pad, 9 is a solder resist, and 10 is a through-hole.

図５においてスルホールパッド６はチップコンデンサ３搭載用の接続エリヤを設けた四角形状であり、チップコンデンサ３実装位置以外はソルダレジストが形成された構造である。これにより、スルホール内へのはんだの流れ込みを防止し、接続のためのはんだ量を適切なものにすることができる。   In FIG. 5, the through-hole pad 6 has a quadrangular shape provided with a connection area for mounting the chip capacitor 3, and has a structure in which a solder resist is formed except for the mounting position of the chip capacitor 3. As a result, it is possible to prevent the solder from flowing into the through hole and to make the amount of solder for connection appropriate.

図６に本発明の実施例３における実装構造概略図を示す。１はＢＧＡパッケージ、３はチップコンデンサ、５はプリント配線板、６はスルホールパッド、７ははんだボール接続端子である。   FIG. 6 shows a schematic view of the mounting structure in the third embodiment of the present invention. Reference numeral 1 is a BGA package, 3 is a chip capacitor, 5 is a printed wiring board, 6 is a through-hole pad, and 7 is a solder ball connection terminal.

図６において、ＢＧＡパッケージ１の電源およびグランドノイズ低減のために実装するチップコンデンサ３のはんだ接続箇所を従来のＢＧＡパッケージ１搭載面近傍から、ＢＧＡパッケージ実装箇所裏面８であるスルホールパッド６上へ直接実装する構造は、本発明の実施例１及び２と同じであるが、チップコンデンサ３を搭載するスルホールパッド形状を図７のプリント配線板パッド構造とした。３はチップコンデンサ、６はスルホールパッド、９はソルダレジスト、１０はスルホールである。   In FIG. 6, the solder connection location of the chip capacitor 3 to be mounted to reduce the power and ground noise of the BGA package 1 is directly from the vicinity of the conventional BGA package 1 mounting surface to the through hole pad 6 which is the back surface 8 of the BGA package mounting location. The mounting structure is the same as in the first and second embodiments of the present invention, but the through-hole pad shape on which the chip capacitor 3 is mounted is the printed wiring board pad structure shown in FIG. 3 is a chip capacitor, 6 is a through-hole pad, 9 is a solder resist, and 10 is a through-hole.

本発明の実施例１及び２では２つの電源及びグランド用スルホールパッド間にチップコンデンサを搭載するパッド構造としていたが、図７の実施例３では、複数の電源及びグランド用スルホール間をパッドで接続して大きなパッドを形成し、それらのパッドとパッド間にチップコンデンサ３を実装する構造とした。チップコンデンサ３実装部以外はソルダレジスト９が形成された構造である。   In the first and second embodiments of the present invention, a pad structure is used in which a chip capacitor is mounted between two power supply and ground through hole pads. However, in the third embodiment of FIG. 7, a plurality of power supplies and ground through holes are connected by pads. Thus, a large pad is formed, and the chip capacitor 3 is mounted between the pads. The solder resist 9 is formed except for the chip capacitor 3 mounting portion.

実施例３の発明により、実施例１及び２と同様に従来のＢＧＡパッケージ１近傍へのチップコンデンサ３の実装がなくなり、チップコンデンサ３の実装に必要な面積を１／６に低減することができ、今までチップコンデンサ３を搭載していたエリアに配線を実施することや、他の部品を実装することが可能となる。また、チップコンデンサ３の実装位置がＢＧＡパッケージ１直下のスルホールパッド上となったことから、従来構造より電源およびグランドの回路接続距離が短くなり、配線の抵抗、インダクタンスを低減でき、電源およびグランドノイズを低減できる効果がある。   According to the invention of the third embodiment, as in the first and second embodiments, the chip capacitor 3 is not mounted in the vicinity of the conventional BGA package 1, and the area required for mounting the chip capacitor 3 can be reduced to 1/6. It becomes possible to carry out wiring in an area where the chip capacitor 3 has been mounted so far, and to mount other components. In addition, since the mounting position of the chip capacitor 3 is on the through-hole pad immediately below the BGA package 1, the circuit connection distance between the power source and the ground is shorter than in the conventional structure, the wiring resistance and inductance can be reduced, and the power source and ground noise are reduced. Is effective.

更に、スルホール間を複数接続してスルホールパッド６を拡大したパッド間にチップコンデンサ３を実装する構造であるため、チップコンデンサ３のサイズを１００５より大きなサイズにして、静電容量を増やすことも可能。静電容量が増えることにより、電源及びグランドノイズの低減性が向上することから、使用するチップコンデンサ３の数を実施例１，２より低減することが可能である。   Furthermore, since the chip capacitor 3 is mounted between the pads in which a plurality of through holes are connected and the through hole pads 6 are enlarged, it is possible to increase the capacitance by making the size of the chip capacitors 3 larger than 1005. . As the capacitance increases, the power supply and ground noise can be reduced. Therefore, the number of chip capacitors 3 to be used can be reduced as compared with the first and second embodiments.

発明の実施例１のチップコンデンサ搭載図（平面図）である。It is a chip capacitor mounting view (plan view) of Example 1 of the invention. 発明の実施例１のチップコンデンサ実装構造概略図である。It is a chip capacitor mounting structure schematic diagram of Example 1 of the invention. 発明の実施例１のプリント配線板パッド構造（平面図）である。It is a printed wiring board pad structure (plan view) of Example 1 of the invention. 発明の実施例１のプリント配線板パッド構造（平面図）である。It is a printed wiring board pad structure (plan view) of Example 1 of the invention. 発明の実施例２のプリント配線板パッド構造（平面図）である。It is a printed wiring board pad structure (plan view) of Example 2 of the invention. 発明の実施例３のチップコンデンサ実装構造概略図である。It is the chip capacitor mounting structure schematic of Example 3 of invention. 発明の実施例３のプリント配線板パッド構造（平面図）である。It is a printed wiring board pad structure (plan view) of Example 3 of the invention. 従来のチップコンデンサ実装構造概略図である。It is the conventional chip capacitor mounting structure schematic. 従来品との単位面積あたりのチップコンデンサ搭載数比較グラフである。It is a graph comparing the number of chip capacitors mounted per unit area with a conventional product.

符号の説明Explanation of symbols

１・・・・・ＢＧＡパッケージ
２・・・・・実装に必要なエリア
３・・・・・チップコンデンサ
４・・・・・チップコンデンサ搭載用パッド
５・・・・・プリント配線板
６・・・・・スルホールパッド
７・・・・・はんだボール接続端子
８・・・・・ＢＧＡパッケージ実装箇所裏面
９・・・・・ソルダレジスト
１０・・・・スルホール
１１・・・・ＢＧＡパッケージ領域
DESCRIPTION OF SYMBOLS 1 ... BGA package 2 ... Area required for mounting 3 ... Chip capacitor 4 ... Pad for chip capacitor mounting 5 ... Printed wiring board 6 ... ... Thru-hole pad 7 ... Solder ball connection terminal 8 ... BGA package mounting location back 9 ... Solder resist 10 ...... Thru hole 11 ... BGA package area

Claims (4)

ＢＧＡパッケージをはんだ接続するプリント配線板において、前記ＢＧＡパッケージの搭載箇所裏面に形成された電源およびグランド用スルホールパッド上にチップコンデンサをはんだ接続することを特徴とするチップコンデンサ実装構造。   A printed circuit board for solder-connecting a BGA package, wherein the chip capacitor is solder-connected on a power supply and ground through-hole pad formed on the back surface of the BGA package mounting location. 請求項１記載の実装構造に使用するプリント配線板において、角型形状または丸形状のスルホールパッドと前記パッド部周辺にソルダレジストが形成されていることを特徴とするプリント配線板。   The printed wiring board used for the mounting structure according to claim 1, wherein a square-shaped or round-shaped through-hole pad and a solder resist are formed around the pad portion. 請求項１記載の実装構造に使用するプリント配線板において、スルホールを有する四角形状のパッド上にチップコンデンサ搭載エリアが形成され、前記搭載エリア以外はソルダレジストが形成されていることを特徴とするプリント配線板。   2. The printed wiring board used in the mounting structure according to claim 1, wherein a chip capacitor mounting area is formed on a quadrangular pad having a through hole, and a solder resist is formed in areas other than the mounting area. Wiring board. 請求項１記載の実装構造に使用するプリント配線板において、複数のスルホール間をパッドで接続して大型パッドを形成し、それらのパッドとパッドの間にチップコンデンサ搭載用に接続エリアが形成されており、前記接続エリア以外はソルダレジストが形成されていることを特徴とするプリント配線板。
The printed wiring board used for the mounting structure according to claim 1, wherein a plurality of through holes are connected by pads to form a large pad, and a connection area for mounting a chip capacitor is formed between the pads. A printed wiring board, wherein a solder resist is formed outside the connection area.
JP2004088301A 2004-03-25 2004-03-25 Chip capacitor mounting structure and printed wiring board Pending JP2005277115A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227484A (en) * 2006-02-22 2007-09-06 Hitachi Ltd Printed wiring board structure
US7292450B2 (en) * 2006-01-31 2007-11-06 Microsoft Corporation High density surface mount part array layout and assembly technique
JP2012256752A (en) * 2011-06-09 2012-12-27 Ngk Spark Plug Co Ltd Multilayer wiring board and method for manufacturing the same
US9006580B2 (en) 2011-06-09 2015-04-14 Ngk Spark Plug Co., Ltd. Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate
CN110402022A (en) * 2019-06-27 2019-11-01 苏州浪潮智能科技有限公司 A kind of pcb board and terminal

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7292450B2 (en) * 2006-01-31 2007-11-06 Microsoft Corporation High density surface mount part array layout and assembly technique
JP2007227484A (en) * 2006-02-22 2007-09-06 Hitachi Ltd Printed wiring board structure
JP2012256752A (en) * 2011-06-09 2012-12-27 Ngk Spark Plug Co Ltd Multilayer wiring board and method for manufacturing the same
US9006580B2 (en) 2011-06-09 2015-04-14 Ngk Spark Plug Co., Ltd. Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate
CN110402022A (en) * 2019-06-27 2019-11-01 苏州浪潮智能科技有限公司 A kind of pcb board and terminal
CN110402022B (en) * 2019-06-27 2020-12-04 苏州浪潮智能科技有限公司 PCB and terminal

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