JP2005137045A - Multi-level output power converter - Google Patents
Multi-level output power converter Download PDFInfo
- Publication number
- JP2005137045A JP2005137045A JP2003367391A JP2003367391A JP2005137045A JP 2005137045 A JP2005137045 A JP 2005137045A JP 2003367391 A JP2003367391 A JP 2003367391A JP 2003367391 A JP2003367391 A JP 2003367391A JP 2005137045 A JP2005137045 A JP 2005137045A
- Authority
- JP
- Japan
- Prior art keywords
- reverse
- switching element
- circuit
- output power
- switching elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000903 blocking effect Effects 0.000 claims abstract description 27
- 230000015556 catabolic process Effects 0.000 claims abstract description 8
- 230000006378 damage Effects 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 20
- 230000007704 transition Effects 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
Description
この発明は、3レベルインバータを含む3以上の異なる電圧を出力する多レベル出力電力変換装置に関する。 The present invention relates to a multilevel output power converter that outputs three or more different voltages including a three-level inverter.
図13に、IGBT(絶縁ゲート形バイポーラトランジスタ)を用い3つの電圧を出力する3レベルインバータの一般的な例を示す。これは、直流電源EpとEnとの直列回路に回路S1,S2,S3を並列に接続したもので、回路S1はIGBTとダイオード(以下、フリーホイールダイオードFWDと呼ぶ)が逆並列に接続されたスイッチQ1〜Q4、クランプダイオードCD1,CD2から構成され、他の回路S2,S3も同様に構成される。
図13の3レベルインバータは、図14(a)〜(c)に示すようなパルスパターンの組み合わせにより、各相でP(+),C(0),N(−)の3つの電圧を出力する。なお、図14(a)〜(c)に示すパルスパターンによる動作モードは、その負荷電流の向きによりさらに図14(a1)〜(c2)の6つの動作モードに細分化される。
FIG. 13 shows a general example of a three-level inverter that outputs three voltages using an IGBT (insulated gate bipolar transistor). In this circuit, circuits S1, S2, and S3 are connected in parallel to a series circuit of DC power supplies Ep and En. In the circuit S1, an IGBT and a diode (hereinafter referred to as a freewheel diode FWD) are connected in antiparallel. It is composed of switches Q1 to Q4 and clamp diodes CD1 and CD2, and the other circuits S2 and S3 are similarly constructed.
The three-level inverter in FIG. 13 outputs three voltages P (+), C (0), and N (−) in each phase by combining pulse patterns as shown in FIGS. 14 (a) to 14 (c). To do. 14A to 14C are further subdivided into six operation modes shown in FIGS. 14A1 to 14C2 depending on the direction of the load current.
図13のような回路構成では一般的に、スイッチQ1〜Q4の損失がクランプダイオードCD1,CD2に比べて大きくなる傾向にある。このため、図15に示すように、クランプダイオードCD1,CD2をIGBTとダイオード(以下、フリーホイールダイオードFWDと呼ぶ)を逆並列接続したスイッチQ5,Q6に置き換え、各素子に流れる電流経路を変更して、各素子の損失を均等化する方法(非特許文献1参照)や、転流ループの配線インダクタンスの影響を小さくして、スイッチング素子の電流遮断時に発生するサージ電圧から、スイッチング素子破壊を防止する方法(特許文献1参照)がとられている。 In the circuit configuration as shown in FIG. 13, the loss of the switches Q1 to Q4 generally tends to be larger than that of the clamp diodes CD1 and CD2. Therefore, as shown in FIG. 15, the clamp diodes CD1 and CD2 are replaced with switches Q5 and Q6 in which IGBTs and diodes (hereinafter referred to as freewheel diodes FWD) are connected in antiparallel, and the current paths flowing through the respective elements are changed. Thus, the loss of each element is equalized (see Non-Patent Document 1) and the influence of the wiring inductance of the commutation loop is reduced to prevent the switching element from being destroyed by the surge voltage generated when the current of the switching element is interrupted. (Refer to Patent Document 1).
しかし、上記各文献に示す方法には下記のような問題がある。
いま、図13に示す例えばスイッチQ2,Q3がオンで、この状態から図16(a)に示すようにスイッチQ3をオフし、次に図16(b)に示すようにスイッチQ1をオンさせた場合を考える。このような場合に、スイッチQ3が破壊していたとすると、直流電源EpはスイッチQ1→Q2→Q3(破壊)→CD2を通して短絡するため、図16(b)に太線で示すよう短絡電流Isが流れる。
However, the methods described in the above documents have the following problems.
Now, for example, the switches Q2 and Q3 shown in FIG. 13 are on, and from this state, the switch Q3 is turned off as shown in FIG. 16 (a), and then the switch Q1 is turned on as shown in FIG. 16 (b). Think about the case. In such a case, assuming that the switch Q3 has been destroyed, the DC power supply Ep is short-circuited through the switches Q1, Q2, Q3 (break), and CD2, so that a short-circuit current Is flows as shown by a bold line in FIG. .
短絡を検出して装置を停止させる場合、すべてのIGBTにオフ信号を入力してオフさせるが、直流電源Epから流れ出る短絡電流Isは大電流であり、図16の場合はこれをスイッチQ1,Q2の2個の素子で遮断することとなる。このとき、主回路配線インダクタンスLmと短絡電流Isの電流減少率dIs/dtとの積で決まるサージ電圧が発生する。このサージ電圧は、最悪の場合スイッチQ1またはQ2、もしくはQ1,Q2ともに
破壊する可能性が発生する。したがって、従来はこのようなサージ電圧を抑制するために、スナバ回路の容量を大きくしたり、ゲート電圧を緩やかに下降させてサージ電圧を抑制する等の種々の対策がとられているが、素子の短絡耐量がないなどの場合には、可能な限り速やかに短絡電流を遮断することが必要となる(このようにする例としては、例えば特許文献2に示すものがある)。
When a short circuit is detected and the apparatus is stopped, an OFF signal is input to all IGBTs to turn them off. However, the short circuit current Is flowing from the DC power supply Ep is a large current, and in the case of FIG. These two elements are used for blocking. At this time, a surge voltage determined by the product of the main circuit wiring inductance Lm and the current reduction rate dIs / dt of the short circuit current Is is generated. In the worst case, this surge voltage may break down both the switches Q1 and Q2 or Q1 and Q2. Therefore, conventionally, in order to suppress such a surge voltage, various measures such as increasing the capacity of the snubber circuit or suppressing the surge voltage by gently lowering the gate voltage have been taken. When there is no short-circuit withstand capability, it is necessary to cut off the short-circuit current as quickly as possible (an example of this is shown in
また、特に上記特許文献1の例では、図16のクランプダイオードCD1,CD2をIGBTとダイオードが逆並列接続されたスイッチQ5,Q6に置き換えた場合、図16で説明したような動作は図17に示すように、図16と同様となる。さらに、図17は図18のように細分化されるが、この場合でもスイッチQ3が破壊した場合は図18(b1),(b2)のようになり、図16の場合と同様になる。
そこで、特許文献3のように直流電源と直列にスイッチを接続し、短絡電流を遮断するものがあるが、直流電源と直列に挿入されたスイッチにより、主回路配線インダクタンスの増加、不要なスイッチの通流損失を招くことになる。
In particular, in the example of
Therefore, as in
したがって、この発明の課題は、部品点数の増加を極力抑えつゝ、素子破壊などによる短絡電流を安全に遮断することにある。 Accordingly, an object of the present invention is to safely cut off a short-circuit current due to element destruction while suppressing an increase in the number of parts as much as possible.
このような課題を解決するために、請求項1の発明では、第1と第2の直流電源を直列に接続し、前記直流電源の正極と負極間に第1から第4のスイッチング素子を直列に接続し、前記第1と第2のスイッチング素子の接続点と前記直流電源の接続点との間には逆方向に耐圧を有する第1の逆阻止型スイッチング素子を接続し、前記第3と第4のスイッチング素子の接続点と前記直流電源の接続点との間には逆方向に耐圧を有する第2の逆阻止型スイッチング素子を接続したことを特徴とする。この請求項1の発明においては、前記第1,第2の逆阻止型スイッチング素子は、前記多レベル出力電力変換装置の運転時にオンし、その停止時にオフすることができ(請求項2の発明)、これら請求項1または2の発明においては、前記第1の逆阻止型スイッチング素子は第2のスイッチング素子と同期してオン,オフさせ、前記第2の逆阻止型スイッチング素子は第3のスイッチング素子と同期してオン,オフさせることができる(請求項3の発明)。
In order to solve such a problem, according to the first aspect of the present invention, the first and second DC power supplies are connected in series, and the first to fourth switching elements are connected in series between the positive electrode and the negative electrode of the DC power supply. A first reverse blocking switching element having a withstand voltage in a reverse direction is connected between a connection point of the first and second switching elements and a connection point of the DC power source, and the third and A second reverse blocking switching element having a withstand voltage in the reverse direction is connected between the connection point of the fourth switching element and the connection point of the DC power supply. In the first aspect of the present invention, the first and second reverse blocking switching elements can be turned on when the multilevel output power converter is in operation, and can be turned off when the multilevel output power converter is stopped. In the invention of
第1と第2の直流電源を直列に接続し、前記直流電源の正極と負極間に第1から第4のスイッチング素子を直列に接続し、前記第1と第2のスイッチング素子の接続点と前記直流電源の接続点との間には逆方向に耐圧を有する逆阻止型スイッチング素子を逆並列に接続した第1の逆並列接続回路を接続し、前記第3と第4のスイッチング素子の接続点と前記直流電源の接続点との間には逆方向に耐圧を有する逆阻止型スイッチング素子を逆並列に接続した第2の逆並列接続回路を接続したことを特徴とする。この請求項4の発明においては、前記第2のスイッチング素子と前記第1の逆並列接続回路とからなる電流経路、または、前記第3のスイッチング素子と前記第2の逆並列接続回路とからなる電流経路を、スイッチング素子に与えるパルスパターンにより選択可能にすることができる(請求項5の発明)。また、上記請求項1〜5のいずれかの発明においては、エミッタ側が同電位となるスイッチング素子は、共通の駆動電源で駆動することができる(請求項6の発明)。
First and second DC power sources are connected in series, first to fourth switching elements are connected in series between a positive electrode and a negative electrode of the DC power source, and a connection point between the first and second switching elements is A first anti-parallel connection circuit in which reverse blocking type switching elements having a withstand voltage in the reverse direction are connected in anti-parallel is connected between the connection points of the DC power supplies, and the third and fourth switching elements are connected. A second anti-parallel connection circuit in which reverse blocking switching elements having a withstand voltage in the reverse direction are connected in anti-parallel is connected between the point and the connection point of the DC power supply. In this invention of Claim 4, it consists of a current path comprising the second switching element and the first antiparallel connection circuit, or comprising the third switching element and the second antiparallel connection circuit. The current path can be selected by a pulse pattern applied to the switching element (invention of claim 5). In the invention of any one of
この発明によれば、素子破壊などの故障時に装置を停止する際、安全に装置を停止することができるだけでなく、各スイッチ素子の温度上昇をバランスさせることができる。 According to the present invention, when stopping the apparatus at the time of failure such as element destruction, not only can the apparatus be stopped safely, but also the temperature rise of each switch element can be balanced.
図1はこの発明の実施の形態を示す回路構成図である。
図示のように、直流電源EpとEnとの直列回路の両端に、IGBTとダイオードが逆並列に接続されたスイッチQ1〜Q4の直列回路が接続されており、スイッチQ1とQ2の接続点と直流電源Ep,Enの接続点との間には、逆方向に耐圧を有する逆阻止型IGBTQD1(以下、スイッチQD1と呼ぶ)が接続され、スイッチQ3とQ4の接続点と直流電源Ep,Enの接続点との間には、逆方向に耐圧を有する逆阻止型IGBTQD2(以下、スイッチQD2と呼ぶ)が接続されて構成されている。
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.
As shown in the figure, a series circuit of switches Q1 to Q4 in which IGBTs and diodes are connected in antiparallel is connected to both ends of a series circuit of DC power supplies Ep and En, and a connection point between the switches Q1 and Q2 and a DC A reverse blocking IGBT QD1 (hereinafter referred to as a switch QD1) having a withstand voltage in the reverse direction is connected between the connection points of the power supplies Ep and En, and the connection point between the switches Q3 and Q4 and the DC power supplies Ep and En. A reverse blocking IGBT QD2 (hereinafter referred to as a switch QD2) having a breakdown voltage in the reverse direction is connected between the points.
逆方向に耐圧を有する逆阻止型IGBTは公知であり、図2(a)のように、順方向に印加される電圧をVCE、順方向に流れる電流をIcとすると、両者の関係は図2(b)のような静特性で示される。また、正方向の印加電圧に対しては図2(c1)のように、オン,オフ信号に追従して電流をオン,オフ制御でき、また、オン,オフ信号とは無関係に、図2(c2)のように、逆方向の印加電圧に対して従来のダイオードと同様に阻止する動特性を有している。 A reverse blocking IGBT having a withstand voltage in the reverse direction is known, and as shown in FIG. 2A, assuming that the voltage applied in the forward direction is VCE and the current flowing in the forward direction is Ic, the relationship between the two is shown in FIG. The static characteristics as shown in (b) are shown. Further, as shown in FIG. 2 (c1), the on / off control of the current can be performed with respect to the applied voltage in the positive direction, following the on / off signal, and regardless of the on / off signal, FIG. As in c2), it has a dynamic characteristic that blocks the applied voltage in the reverse direction in the same manner as in the conventional diode.
図3に、図1の1相分の回路を示し、図4に図3の回路を駆動する制御装置の例を示す。
図4では、運転指令Srunが入力されてスイッチQ1〜Q4のオン,オフ指令を生成する一般的なPWM(パルス幅変調信号)発生回路が設けられ、ここで生成されたQ1〜Q4のオン,オフ指令(パルスパターン)は、各スイッチQ1〜Q4を駆動するためのゲート駆動回路GDU(Q1)〜GDU(Q4)にそれぞれ入力される。また、Srunと同期したオン,オフ信号を、スイッチQD1,QD2を駆動するためのゲート駆動回路GDU(QD1),GDU(QD2)にそれぞれ入力する。各ゲート駆動回路からは図5のような指令が出力され、それぞれの図3に示すスイッチQ1〜Q4に与えられる。
FIG. 3 shows a circuit for one phase of FIG. 1, and FIG. 4 shows an example of a control device for driving the circuit of FIG.
In FIG. 4, a general PWM (pulse width modulation signal) generation circuit that generates an ON / OFF command for the switches Q1 to Q4 when the operation command Srun is input is provided, and the generated Q1 to Q4 ON, The off command (pulse pattern) is input to gate drive circuits GDU (Q1) to GDU (Q4) for driving the switches Q1 to Q4, respectively. On / off signals synchronized with Srun are input to gate drive circuits GDU (QD1) and GDU (QD2) for driving the switches QD1 and QD2, respectively. A command as shown in FIG. 5 is output from each gate drive circuit and is given to each of the switches Q1 to Q4 shown in FIG.
したがって、図4の制御装置に運転指令Srunが入力されると、PWM発生回路は図5のようなオン,オフパルス指令を生成し、各スイッチQ1〜Q4に与える。また、運転指令と同じオン,オフを、スイッチQD1,QD2に与える。これにより、運転中はスイッチQD1,QD2に常時オン信号が与えられる。
その結果、図2の逆阻止型IGBTの特性から、順方向の電圧に対しては電流を流し、逆方向の電圧に対しては阻止するため、ダイオードと同じ動作となり、従来の3レベルインバータと同様の動作が可能となる。なお、運転指令にかかわらずQD1,QD2に常時オン信号を与えても同様の動作をさせることができる。
Therefore, when the operation command Srun is input to the control device of FIG. 4, the PWM generation circuit generates an on / off pulse command as shown in FIG. 5 and applies it to the switches Q1 to Q4. Further, the same ON / OFF as the operation command is given to the switches QD1, QD2. Thereby, an ON signal is always given to the switches QD1 and QD2 during operation.
As a result, from the characteristics of the reverse blocking IGBT of FIG. 2, the current flows for the forward voltage and the reverse voltage is blocked, so that the operation is the same as that of the diode. Similar operations are possible. Note that the same operation can be performed even if a constant on signal is given to QD1 and QD2 regardless of the operation command.
次に、素子が破壊したときの動作を、図6を参照して説明する。
図6はスイッチQ2,Q3にオン信号が入力されている状態から、スイッチQ3が破壊したときの例を示す。図6(a)のスイッチQ3→スイッチQD2に負荷電流ILが流れている状態から、何らかの事故でスイッチQ3が破壊したとする。スイッチQ3が正常時には、スイッチQ1,Q2のFWD(フリーホイールダイオード)に負荷電流ILが転流するが、スイッチQ3が破壊している場合は負荷電流ILが転流せずに、図6(b)に示すように、スイッチQ3(破壊)→スイッチQD2に電流が流れ続ける。
Next, the operation when the element is destroyed will be described with reference to FIG.
FIG. 6 shows an example when the switch Q3 is destroyed from the state in which the ON signal is input to the switches Q2 and Q3. Assume that the switch Q3 is destroyed due to some accident from the state in which the load current IL flows from the switch Q3 to the switch QD2 in FIG. When the switch Q3 is normal, the load current IL is commutated to the FWD (free wheel diode) of the switches Q1 and Q2. However, when the switch Q3 is broken, the load current IL is not commutated, and FIG. As shown, the current continues to flow from the switch Q3 (destruction) to the switch QD2.
次に、スイッチQ1にオン信号が入力されると、図6(c)に示すように直流電源Ep→スイッチQ1→スイッチQ2→スイッチQ3(破壊)→スイッチQD2の経路で短絡電流Isが流れる。短絡を検出してすべてのスイッチをオフさせると、短絡電流はスイッチQ1,Q2,QD2で遮断する(図6(d)参照)。したがって、図16〜18で説明した従来の遮断時に比べ、2個の素子から3個の素子で電圧を分担することになり、サージ電圧に対する素子耐圧超過の可能性は減少する。その結果、スナバ回路を小さくすることができ、短絡電流をより速やかに遮断することができる。 Next, when an ON signal is input to the switch Q1, as shown in FIG. 6C, a short-circuit current Is flows through the path of the DC power supply Ep → the switch Q1 → the switch Q2 → the switch Q3 (destruction) → the switch QD2. When a short circuit is detected and all the switches are turned off, the short circuit current is interrupted by the switches Q1, Q2, and QD2 (see FIG. 6D). Therefore, compared with the conventional interruption described with reference to FIGS. 16 to 18, the voltage is shared by three elements from two elements, and the possibility of the element withstand voltage exceeding the surge voltage is reduced. As a result, the snubber circuit can be reduced and the short-circuit current can be cut off more quickly.
図7は図1または図3の別の動作を説明するための状態遷移図である。
これは、スイッチQD1,QD2をスイッチQ2,Q3と同期をとってオン,オフさせるもので、スイッチQ2,Q3にオン信号が入力されている図7(a)の状態で、スイッチQ3が破壊したときの例について説明する。図7(a)の状態から同図(b)のように、スイッチQ3にオフ信号を入力するとともに、スイッチQD2もオフさせると、スイッチQ3が破壊したことで、これでは負荷電流ILを遮断できず、スイッチQD2により遮断する。これにより、負荷電流ILはスイッチQ1,Q2の各FWDに転流する。
FIG. 7 is a state transition diagram for explaining another operation of FIG. 1 or FIG.
This is because the switches QD1 and QD2 are turned on and off in synchronization with the switches Q2 and Q3, and the switch Q3 is destroyed in the state of FIG. 7A in which the ON signal is input to the switches Q2 and Q3. An example will be described. As shown in FIG. 7 (b) from the state of FIG. 7 (a), when the OFF signal is input to the switch Q3 and the switch QD2 is also turned OFF, the switch Q3 is destroyed, and this can interrupt the load current IL. First, it is shut off by the switch QD2. Thereby, load current IL is commutated to each FWD of switches Q1 and Q2.
このとき、スイッチQ1,Q2はオン状態であり、スイッチQ3が破壊しているため、スイッチQD2に直流電圧Epが印加される(図7(c)参照)。スイッチQD2に印加された電圧を検出すれば、スイッチQ3の破壊が把握できるため、次にQ1にオン信号が入力されるまでのデッドタイム期間中に破壊を検出することができ、さらには破壊を検出して、次にオンさせるスイッチQ1をオフさせて装置を停止させる(図7(d)参照)ことで、短絡電流を未然に防ぐことが可能となる。 At this time, since the switches Q1 and Q2 are in the ON state and the switch Q3 is broken, the DC voltage Ep is applied to the switch QD2 (see FIG. 7C). By detecting the voltage applied to the switch QD2, the breakdown of the switch Q3 can be grasped, so that the breakdown can be detected during the dead time period until the next ON signal is input to the Q1, and further the breakdown is detected. By detecting and turning off the switch Q1 to be turned on next time to stop the apparatus (see FIG. 7D), it is possible to prevent a short circuit current.
図8はこの発明の他の実施の形態を示す回路図である。これは、図1または3の逆阻止型IGBTQD1,QD2と逆並列に、逆阻止型IGBTを接続したスイッチ(双方向スイッチ)QS1,QS2を用いた点が特徴である。
図9に図8の1相分の回路を示す。図3で説明した機能は、スイッチQS1,QS2のQS1RおよびQS2のQS2Rの制御動作により、同様に実現できる。
FIG. 8 is a circuit diagram showing another embodiment of the present invention. This is characterized in that switches (bidirectional switches) QS1 and QS2 in which reverse blocking IGBTs are connected in reverse parallel to the reverse blocking IGBTs QD1 and QD2 of FIG. 1 or 3 are used.
FIG. 9 shows a circuit for one phase of FIG. The function described in FIG. 3 can be similarly realized by the control operation of the QS1R of the switches QS1 and QS2 and the QS2R of the QS2.
図10に、オン,オフ中性点電位を出力している状態を示す。図10(a)は負荷電流ILが流入している状態で、スイッチQ2のFWD→スイッチQS1のQS1Fを通るIL1と、スイッチQ3→スイッチQS2のQS2Rを通るIL2との2つの流入経路がある。流入する負荷電流ILの経路としてIL1とIL2の経路、IL1の経路またはIL2の経路などがあるが、どの経路を選択するかは例えば各部のスイッチの温度上昇などを考慮し、各スイッチに与えるパルスパターンにより決定することができる。
図10(b)は負荷電流ILが流出している状態を示す。この場合も、同様にIL1,IL2の経路を選択することができる。この場合も、従来と同様のパルスパターンでQ2,Q3をオン,オフすればよい。
FIG. 10 shows a state in which an on / off neutral point potential is being output. FIG. 10A shows a state in which the load current IL is flowing, and there are two inflow paths of F1 from the switch Q2 → IL1 passing through the QS1F of the switch QS1 and IL2 passing through the QS2R of the switch Q3 → the switch QS2. There are IL1 and IL2 paths, IL1 paths, or IL2 paths as the path of the load current IL that flows in. The path to be selected depends on, for example, the temperature rise of the switches in each part, and the pulse given to each switch. It can be determined by the pattern.
FIG. 10B shows a state where the load current IL is flowing out. In this case, the IL1 and IL2 paths can be selected in the same manner. In this case as well, Q2 and Q3 may be turned on and off with the same pulse pattern as in the prior art.
図11にこの発明のさらに他の実施の形態を示す。
図11(a)に示す回路は、スイッチがQ1〜Q4とQD1,QD2の6個で構成される。ここでは、スイッチQ1とQD1のエミッタ電位が共通であるため、スイッチQ1とQD1は駆動電源を共通として、全部で5個の電源で駆動することができる。また、図11(b)に示す回路は、スイッチがQ1〜Q4、QS1(正負両方向)、QS2(正負両方向)の8個で構成されるが、スイッチQ1とQS1(逆方向:QS1R)、スイッチQS1(正方向:QS1F)とスイッチQS2(逆方向:QS2R)、スイッチQ3とQS2(正方向:QS2F)のエミッタ電位がそれぞれ共通であるため、同じ電源で駆動することができ、図11(a)と同じく全部で5個の電源でよい。
FIG. 11 shows still another embodiment of the present invention.
The circuit shown in FIG. 11A includes six switches Q1 to Q4 and QD1 and QD2. Here, since the emitter potentials of the switches Q1 and QD1 are common, the switches Q1 and QD1 can be driven by a total of five power supplies with a common drive power supply. In addition, the circuit shown in FIG. 11B includes eight switches Q1 to Q4, QS1 (both positive and negative directions), and QS2 (both positive and negative directions), but switches Q1 and QS1 (reverse direction: QS1R), switches Since the emitter potentials of QS1 (forward direction: QS1F) and switch QS2 (reverse direction: QS2R) and switches Q3 and QS2 (forward direction: QS2F) are common to each other, they can be driven by the same power source. ) And 5 power supplies in all.
以上では、逆阻止型IGBTを用いた例について説明したが、この発明はIGBTとダイオードを直列接続したものにも、同様にして適用できる。
また、3つの電位を出力できる3レベルインバータを例に説明したが、図12に示されるようなマルチレベルインバータにも、同様にして適用できるのは言うまでもない。
Although the example using the reverse blocking IGBT has been described above, the present invention can be similarly applied to a structure in which an IGBT and a diode are connected in series.
Further, although a three-level inverter capable of outputting three potentials has been described as an example, it goes without saying that the present invention can be similarly applied to a multi-level inverter as shown in FIG.
Q1〜Q6…IGBT(絶縁ゲート型バイポーラトランジスタ)、QD1,QD2…逆阻止型IGBT、QS1,QS2…(双方向)スイッチ、CD1,CD2…クランプダイオード、GDU…ゲート駆動回路、Ep,En…直流電源。
Q1-Q6 ... IGBT (Insulated Gate Bipolar Transistor), QD1, QD2 ... Reverse Blocking IGBT, QS1, QS2 ... (Bidirectional) Switch, CD1, CD2 ... Clamp Diode, GDU ... Gate Drive Circuit, Ep, En ... DC Power supply.
Claims (6)
6. The multilevel output power converter according to claim 1, wherein the switching elements having the same potential on the emitter side are driven by a common driving power source.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003367391A JP4244005B2 (en) | 2003-10-28 | 2003-10-28 | Multi-level output power converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003367391A JP4244005B2 (en) | 2003-10-28 | 2003-10-28 | Multi-level output power converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005137045A true JP2005137045A (en) | 2005-05-26 |
JP4244005B2 JP4244005B2 (en) | 2009-03-25 |
Family
ID=34645406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003367391A Expired - Lifetime JP4244005B2 (en) | 2003-10-28 | 2003-10-28 | Multi-level output power converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4244005B2 (en) |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007185064A (en) * | 2006-01-10 | 2007-07-19 | Toshiba Mitsubishi-Electric Industrial System Corp | Multi-level power conversion device |
JP2007274778A (en) * | 2006-03-30 | 2007-10-18 | Yokohama National Univ | Bi-directional voltage step up/step down chopper circuit |
KR100928549B1 (en) * | 2007-11-30 | 2009-11-24 | 한국전기연구원 | Switch clamp multi-level inverter |
JP2010246189A (en) * | 2009-04-01 | 2010-10-28 | Nagaoka Univ Of Technology | Power conversion equipment |
JP2012029384A (en) * | 2010-07-21 | 2012-02-09 | Fuji Electric Co Ltd | Control circuit for power conversion system |
JP2012210150A (en) * | 2012-08-02 | 2012-10-25 | Toshiba Mitsubishi-Electric Industrial System Corp | Multilevel power conversion device |
US20120326506A1 (en) * | 2009-12-23 | 2012-12-27 | Pukyong National University Industry-University Cooperation Foundation | Load-segmentation-based 3-level inverter and method of controlling the same |
CN102857120A (en) * | 2012-10-21 | 2013-01-02 | 山东博诚机电有限公司 | Insulated gate bipolar translator (IGBT) clamping three-level frequency converter |
CN102882413A (en) * | 2012-06-11 | 2013-01-16 | 合肥工业大学 | Three-level inverter dead-time compensation algorithm based on modulated wave correction |
CN103051228A (en) * | 2012-12-12 | 2013-04-17 | 江苏大学 | Method and device for balancing neutral point voltage deviation on direct current side of diode-clamped three-level inverter |
CN103051229A (en) * | 2012-12-12 | 2013-04-17 | 江苏大学 | Method and device thereof for restraining mid-voltage fluctuation of direct current side of diode clamping three-level inverter |
KR101287444B1 (en) | 2011-11-30 | 2013-07-19 | 경북대학교 산학협력단 | Multi-level Inverter and Driving Method Thereof |
KR101312589B1 (en) | 2013-05-24 | 2013-09-30 | 경북대학교 산학협력단 | Multi-level Inverter and Driving Method Thereof |
US20130314957A1 (en) * | 2012-05-25 | 2013-11-28 | General Electric Company | High voltage high power multi-level drive structure |
CN103516244A (en) * | 2012-06-14 | 2014-01-15 | 富士电机株式会社 | Protection control system for a multilevel power conversion circuit |
JP2014147200A (en) * | 2013-01-29 | 2014-08-14 | Meidensha Corp | Gate drive signal generating device of multilevel power converter |
CN104052254A (en) * | 2013-03-14 | 2014-09-17 | Abb公司 | Method for controlling switching branch of three-level converter and switching branch for three-level converter |
US20160043659A1 (en) * | 2014-08-11 | 2016-02-11 | Ge Energy Power Conversion Technology Ltd | Multilevel converter |
EP2884651A4 (en) * | 2012-08-10 | 2016-12-14 | Mitsubishi Electric Corp | Three-level power conversion device |
CN110311581A (en) * | 2019-08-06 | 2019-10-08 | 阳光电源股份有限公司 | Inverter circuit control method, device and inverter |
US10840903B2 (en) | 2018-09-14 | 2020-11-17 | Kabushiki Kaisha Toshiba | Semiconductor module |
-
2003
- 2003-10-28 JP JP2003367391A patent/JP4244005B2/en not_active Expired - Lifetime
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007185064A (en) * | 2006-01-10 | 2007-07-19 | Toshiba Mitsubishi-Electric Industrial System Corp | Multi-level power conversion device |
JP2007274778A (en) * | 2006-03-30 | 2007-10-18 | Yokohama National Univ | Bi-directional voltage step up/step down chopper circuit |
KR100928549B1 (en) * | 2007-11-30 | 2009-11-24 | 한국전기연구원 | Switch clamp multi-level inverter |
JP2010246189A (en) * | 2009-04-01 | 2010-10-28 | Nagaoka Univ Of Technology | Power conversion equipment |
US20120326506A1 (en) * | 2009-12-23 | 2012-12-27 | Pukyong National University Industry-University Cooperation Foundation | Load-segmentation-based 3-level inverter and method of controlling the same |
US8902615B2 (en) * | 2009-12-23 | 2014-12-02 | Pukyong National University Industry-University Cooperation Foundation | Load-segmentation-based 3-level inverter and method of controlling the same |
JP2012029384A (en) * | 2010-07-21 | 2012-02-09 | Fuji Electric Co Ltd | Control circuit for power conversion system |
KR101287444B1 (en) | 2011-11-30 | 2013-07-19 | 경북대학교 산학협력단 | Multi-level Inverter and Driving Method Thereof |
US9148069B2 (en) * | 2012-05-25 | 2015-09-29 | General Electric Company | High voltage high power multi-level drive structure |
US20130314957A1 (en) * | 2012-05-25 | 2013-11-28 | General Electric Company | High voltage high power multi-level drive structure |
CN102882413A (en) * | 2012-06-11 | 2013-01-16 | 合肥工业大学 | Three-level inverter dead-time compensation algorithm based on modulated wave correction |
CN103516244A (en) * | 2012-06-14 | 2014-01-15 | 富士电机株式会社 | Protection control system for a multilevel power conversion circuit |
JP2012210150A (en) * | 2012-08-02 | 2012-10-25 | Toshiba Mitsubishi-Electric Industrial System Corp | Multilevel power conversion device |
US9654026B2 (en) | 2012-08-10 | 2017-05-16 | Mitsubishi Electric Corporation | Three-level power converting apparatus with reduced conduction loss |
EP2884651A4 (en) * | 2012-08-10 | 2016-12-14 | Mitsubishi Electric Corp | Three-level power conversion device |
CN102857120A (en) * | 2012-10-21 | 2013-01-02 | 山东博诚机电有限公司 | Insulated gate bipolar translator (IGBT) clamping three-level frequency converter |
CN103051229A (en) * | 2012-12-12 | 2013-04-17 | 江苏大学 | Method and device thereof for restraining mid-voltage fluctuation of direct current side of diode clamping three-level inverter |
CN103051228B (en) * | 2012-12-12 | 2014-12-03 | 江苏大学 | Method and device for balancing neutral point voltage deviation on direct current side of diode-clamped three-level inverter |
CN103051229B (en) * | 2012-12-12 | 2015-02-04 | 江苏大学 | Method and device thereof for restraining mid-voltage fluctuation of direct current side of diode clamping three-level inverter |
CN103051228A (en) * | 2012-12-12 | 2013-04-17 | 江苏大学 | Method and device for balancing neutral point voltage deviation on direct current side of diode-clamped three-level inverter |
JP2014147200A (en) * | 2013-01-29 | 2014-08-14 | Meidensha Corp | Gate drive signal generating device of multilevel power converter |
CN104052254B (en) * | 2013-03-14 | 2016-08-17 | Abb技术有限公司 | Switch branch and control method thereof for three level translators |
CN104052254A (en) * | 2013-03-14 | 2014-09-17 | Abb公司 | Method for controlling switching branch of three-level converter and switching branch for three-level converter |
KR101312589B1 (en) | 2013-05-24 | 2013-09-30 | 경북대학교 산학협력단 | Multi-level Inverter and Driving Method Thereof |
US20160043659A1 (en) * | 2014-08-11 | 2016-02-11 | Ge Energy Power Conversion Technology Ltd | Multilevel converter |
US10840903B2 (en) | 2018-09-14 | 2020-11-17 | Kabushiki Kaisha Toshiba | Semiconductor module |
CN110311581A (en) * | 2019-08-06 | 2019-10-08 | 阳光电源股份有限公司 | Inverter circuit control method, device and inverter |
CN110311581B (en) * | 2019-08-06 | 2021-01-08 | 阳光电源股份有限公司 | Inverter circuit control method and device and inverter |
US11411488B2 (en) | 2019-08-06 | 2022-08-09 | Sungrow Power Supply Co., Ltd. | Method and apparatus for controlling modes of inverter circuit, and inverter |
Also Published As
Publication number | Publication date |
---|---|
JP4244005B2 (en) | 2009-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4244005B2 (en) | Multi-level output power converter | |
JP6040582B2 (en) | Protection control method for multi-level power conversion circuit | |
US6392907B1 (en) | NPC inverter control system | |
CA2563457C (en) | Inverter bridge controller implementing short-circuit protection scheme | |
JP5226183B2 (en) | Multi-level power converter | |
JP4759673B2 (en) | Multi-level converter and control method thereof | |
EP2897278B1 (en) | System and method of power conversion | |
JP4313658B2 (en) | Inverter circuit | |
JP2012029429A (en) | Three level power conversion device | |
US20200366186A1 (en) | Modular multilevel converter sub-module having dc fault current blocking function and method of controlling the same | |
JP2017163392A (en) | Inverter driving device and semiconductor module | |
CN110299696B (en) | T-shaped three-level converter and short-circuit protection circuit thereof | |
JPH11262242A (en) | Semiconductor element drive circuit and power conversion device using the same | |
JP5298557B2 (en) | Voltage-driven semiconductor device gate drive device | |
JP4946103B2 (en) | Power converter | |
JP5695379B2 (en) | Power converter | |
US6903911B2 (en) | Protective circuit for a network-controlled thyristor bridge | |
JP2002165462A (en) | Semiconductor power converter | |
JP2006271042A (en) | Multilevel inverter | |
KR101712445B1 (en) | Mixed voltage neutral point clamped type multi-level inverter having no dead-time | |
CN110829802B (en) | Three-level half-bridge driving circuit and converter | |
JP2005185003A (en) | Protective device of power conversion apparatus | |
JP4839794B2 (en) | PWM pulse generator for AC direct converter | |
JPH05244777A (en) | Gate driving circuit for serial multiple inverter | |
JP2009278704A (en) | Gate drive of voltage-driven semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060414 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081211 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081224 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4244005 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120116 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120116 Year of fee payment: 3 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120116 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120116 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130116 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130116 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140116 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |