JP2005123294A - Semiconductor device and method for forming gold bump in device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a damage generated in a foundation for an electrode pad by composing an Au bump of two layers or more, in the Au bump formed on the electrode pad for a semiconductor device. <P>SOLUTION: The first layer Au bump 7 is formed by carrying out a plating bath heated at a liquid temperature of 55°C by a first plating tank in a gold plating process in the Au bump formed on a semiconductor electrode 1 for a semiconductor element 12. A growth height is grown in approximately 3 μm. The plating bath heated at the liquid temperature of 60°C is carried out continuously by a second plating tank. The Au bump 8 of a second layer having a hardness higher than a first layer is grown to a height of approximately 12 μm. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which an Au (gold) bump is formed on an electrode pad, and a method for forming an Au bump in the semiconductor device.

  2 (a) to 2 (f) are flow charts showing a part of the process for forming a Au bump in a conventional semiconductor device, wherein 1 is a semiconductor electrode, and 2 is a surface protective film. 3 is a resist, 4 is a TiW barrier metal, 5 is an Au barrier metal, 6 is an Au bump, and 12 is a semiconductor element.

  In FIG. 2A, the surface protective film 2 is formed on the entire surface of the semiconductor device including the outer periphery on the semiconductor electrode 1 formed as the external electrode pad of the semiconductor device. However, the center portion of the semiconductor electrode 1 is not covered with the surface protective film 2 and the surface is exposed as the semiconductor electrode opening 15. In FIG. 2B, a TiW barrier metal 4 and an Au barrier metal 5 are formed on the entire surface of the semiconductor device including the entire surface of the semiconductor electrode 1 by sputtering or the like. In FIG. 2C, a resist 3 is applied to the entire surface of the semiconductor device, and a portion where the Au bump 6 is formed is removed by a mask process. In FIG. 2D, Au bumps 6 are formed by gold plating. Thereafter, in FIG. 2E, the resist 3 is removed, and unnecessary portions of the TiW barrier metal 4 and the Au barrier metal 5 in the region other than the region under the Au bump 6 are removed by etching, and FIG. The shape of the Au bump 6 as shown is completed.

In addition, Au bump formation methods other than those described above and their configurations are described in Patent Document 1 and the like.
JP-A-6-77232

  However, when the Au bump 6 formed by the conventional Au bump forming method is mounted on a set substrate such as a liquid crystal panel, there is a possibility that a problem may occur.

  The malfunction will be described with reference to FIGS. 3 (a) and 3 (b). FIG. 3 is a cross-sectional view of the shape when the semiconductor element 12 having the Au bumps 6 is mounted on the panel glass electrode 10 formed on the liquid crystal panel glass 9 by COG (Chip On Glass).

  First, the chip on which the Au bumps 6 are formed is COG mounted on the liquid crystal panel glass 9. An anisotropic conductive film 13 is attached to a region of the liquid crystal panel glass 9 that sufficiently includes the panel glass electrode 10. The anisotropic conductive film 13 contains conductive particles 14, and the Au bump 6 and the panel glass electrode 10 are sufficiently aligned to be mounted under a predetermined pressure and temperature. Thus, the Au bump 6 and the panel glass electrode 10 are electrically connected (FIG. 3A).

  At this time, the Au bump 6 is subjected to heating and pressurization during mounting, but the Au bump 6 is crushed and deformed by this stress. The side wall of the Au bump 6 swells because it is free from deformation. However, the portion of the Au bump 6 in contact with the semiconductor electrode 1 does not have a place to be deformed due to stress, and a large stress is generated around the semiconductor electrode opening 15 to cause damage such as a crack 18 in the surface protective film 2 ( In FIG. 3 (b)), when damage further progresses / accelerates, there is a possibility that the semiconductor element 12 including the wiring or circuit formed in the lower layer of the semiconductor electrode 1 may be damaged or change in element characteristics.

  On the other hand, if the overall hardness of the Au bump 6 is lowered to reduce the occurrence of stress, the lateral bulge of the Au bump 6 becomes large, causing a problem of short-circuiting with adjacent bumps. .

  The present invention solves the above-described conventional problems, suppresses the occurrence of bulging as a whole Au bump, and reduces the interval between adjacent Au bumps, and the Au bump in the semiconductor device. An object is to provide a forming method.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which an Au bump is formed on an electrode pad, and at least two kinds of Au bump layers having different hardnesses are formed on the electrode pad. It is characterized in that the hardness of the second Au bump layer formed on the first Au bump layer is higher than the hardness of the formed first Au bump layer.

  Further, the thickness of the second Au bump layer is made thicker than the thickness of the first Au bump layer.

  The Au bump forming method in the semiconductor device of the present invention uses the same patterned resist, uses two or more different plating tanks, and uses a plating solution of two or more temperatures, It is characterized in that at least two Au bump layers are formed.

  According to the present invention, the hardness of the Au bump of the first layer of the Au bump that is grounded to the semiconductor electrode is lower than the hardness of the Au bump of the second layer or is deformed by stress. Since the thickness of the Au bump is thinner than the thickness of the second-layer Au bump, the first-layer Au bump is preferentially deformed, thereby suppressing the lateral swelling of the entire Au bump. . For this reason, it is possible to prevent the semiconductor element including the periphery of the semiconductor electrode opening, the wiring, and the circuit from being damaged or causing fluctuations in the element characteristics, and the interval distance between the adjacent Au bumps can be reduced. It can be miniaturized.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, members corresponding to those described based on FIGS. 1 and 3 are denoted by the same reference numerals.

  FIGS. 1A to 1G are flow charts showing a part of a process for explaining the Au bump forming method according to an embodiment of the present invention, wherein 1 is a semiconductor electrode, and 2 is a surface protective film. 3 is a resist, 4 is a TiW barrier metal, 5 is an Au barrier metal, 6 is an Au bump, 7 is a first layer Au bump, and 8 is a second layer Au bump.

  In FIG. 1A, a semiconductor electrode 1 which is an external electrode pad of a semiconductor element 12 is formed. Usually, the semiconductor electrode 1 is made of Al or Cu. In some cases, Cu or the like is mixed as a countermeasure against migration. Thereafter, the entire surface of the semiconductor electrode 1 is covered with the surface protective film 2, and then a semiconductor electrode opening 15 is formed in the surface protective film 2 on the semiconductor electrode 1 by dry etching or the like. As a material for the surface protective film 2, Pl-SiN, polyimide resin, or the like is used. Thereafter, in FIG. 1B, a TiW barrier metal 4 and an Au barrier metal 5 are formed on the entire surface of the semiconductor element 12 including the semiconductor electrode 1 by sputtering or the like.

  When these barrier metals are formed by sputtering, reverse sputtering is usually performed for the purpose of removing the oxide film on the semiconductor electrode 1, and then the barrier metal is continuously formed. The TiW barrier metal 4 and the Au barrier metal 5 are formed in two layers depending on the material of the semiconductor electrode 1, and when the material of the semiconductor electrode 1 is Al as in the present embodiment, the first layer of the barrier metal is compatible with Al. TiW, which is a compatible metal, is used, and Au, which is the same metal as the Au bump 6, is used as the second barrier metal layer. This is because, if Au is directly formed on Al of the semiconductor electrode 1, the adhesion strength between Al and the first layer Au barrier metal becomes very weak, and Au bumps 6 are formed on TiW. This is because the adhesion strength between the TiW barrier metal 4 and the Au bump 6 becomes very weak.

  Thereafter, in FIG. 1C, the resist 3 is applied to the entire surface of the semiconductor device, and portions other than the portion where the Au bumps 6 are formed are removed by a mask process. In FIG. A plating bath heated to a liquid temperature of 55 ° C. is carried out in a bath to form the first layer Au bump 7. The growth height is about 3 μm. In FIG. 1 (e), a plating bath heated to a liquid temperature of 60 ° C. is continuously performed in the second plating tank, and the second layer Au bump 8 having a hardness higher than that of the first layer is about 12 μm high. Grow to become. Thereafter, in FIG. 1 (f), the resist 3 is removed, and in FIG. 1 (g), the Au barrier metal 5 and the TiW barrier metal 4 are removed by etching.

  As a result, the hardness of the Au bump 7 of the first layer of the Au bump 6 can be made higher than the hardness of the Au bump 8 of the second layer. The thickness 16 can be made thinner than the thickness 17 of the second-layer Au bump.

  As described above, in this embodiment, the hardness of the Au bump 7 of the first layer of the Au bump 6 that is grounded to the semiconductor electrode 1 is lower than the hardness of the Au bump 8 of the second layer. In addition, the structure is preferentially deformed to prevent damage to the semiconductor element 12 including the periphery of the semiconductor electrode opening 15, wiring, or circuit, or fluctuations in element characteristics.

  Further, since the Au bump thickness 16 of the first layer of the Au bump 6 that is deformed by stress is thinner than the Au bump thickness 17 of the second layer, the Au bump 7 of the first layer is preferentially deformed. Thus, the lateral bulge of the Au bump 6 as a whole can be suppressed. Thereby, the interval distance 11 between the Au bumps 6 arranged adjacent to each other can be miniaturized.

  The present invention is applied to a semiconductor device in which Au bumps are formed on electrode pads, and a method for forming Au bumps in the semiconductor device, and in particular, suppresses bulging in the lateral direction as a whole Au bump, thereby damaging elements. Alternatively, the present invention is effective when applied to a semiconductor device in which fluctuation of element characteristics is prevented and the distance between Au bumps arranged adjacent to each other is reduced.

(A)-(g) is a flowchart which shows a part in cross section for demonstrating the process of the Au bump formation method of one Example of this invention. (A)-(f) is a flowchart which shows a part in cross section for demonstrating the process of the formation method of Au bump in the conventional semiconductor device Explanatory diagram of defects in a conventional semiconductor device on which Au bumps are formed Explanatory drawing of prevention of element damage occurrence and element characteristic fluctuation prevention in an embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor electrode 2 Surface protective film 3 Resist 4 TiW barrier metal 5 Au barrier metal 6 Au bump 7 1st layer Au bump 8 2nd layer Au bump 9 Liquid crystal panel glass 10 Panel glass electrode 11 Between Au bump adjacent Distance 12 Semiconductor element 13 Anisotropic conductive film 14 Conductive particle 15 Semiconductor electrode opening 16 Thickness of Au bump of first layer 17 Thickness of Au bump of second layer 18 Crack

Claims (3)

  A semiconductor device having gold bumps formed on an electrode pad, wherein at least two types of gold bump layers having different hardnesses are formed, and the hardness of the first gold bump layer formed on the electrode pad A semiconductor device characterized in that the second gold bump layer formed on one gold bump layer has a higher hardness.   2. The semiconductor device according to claim 1, wherein the thickness of the second gold bump layer is made thicker than the thickness of the first gold bump layer.   3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the same patterned resist is used, two or more different plating tanks are used, and a plating solution having two or more temperatures is used. To form a gold bump layer in a semiconductor device, wherein at least two gold bump layers are formed.

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