[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JP5280650B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5280650B2
JP5280650B2 JP2007159351A JP2007159351A JP5280650B2 JP 5280650 B2 JP5280650 B2 JP 5280650B2 JP 2007159351 A JP2007159351 A JP 2007159351A JP 2007159351 A JP2007159351 A JP 2007159351A JP 5280650 B2 JP5280650 B2 JP 5280650B2
Authority
JP
Japan
Prior art keywords
semiconductor device
barrier metal
metal layer
opening
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007159351A
Other languages
Japanese (ja)
Other versions
JP2008311530A (en
Inventor
茂幸 上田
忠洋 森藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2007159351A priority Critical patent/JP5280650B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to US12/663,563 priority patent/US8436467B2/en
Priority to PCT/JP2008/060844 priority patent/WO2008153128A1/en
Priority to TW097122280A priority patent/TW200915511A/en
Priority to CN2008800202805A priority patent/CN101681859B/en
Publication of JP2008311530A publication Critical patent/JP2008311530A/en
Priority to US13/856,905 priority patent/US8922010B2/en
Application granted granted Critical
Publication of JP5280650B2 publication Critical patent/JP5280650B2/en
Priority to US14/337,959 priority patent/US9053991B2/en
Priority to US14/491,556 priority patent/US9123628B2/en
Priority to US14/803,207 priority patent/US9466583B2/en
Priority to US15/219,912 priority patent/US9685419B2/en
Priority to US15/591,456 priority patent/US10032739B2/en
Priority to US16/018,128 priority patent/US10510700B2/en
Priority to US16/683,647 priority patent/US11037897B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05555—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing reliability from being deteriorated. <P>SOLUTION: The semiconductor device includes an electrode pad 2 formed on the top surface of a semiconductor substrate 1 and a first opening 3a that exposes the top surface of the electrode pad 2, and comprises, on the top surface of the semiconductor substrate 1, a passivation layer 3 formed so as to partially overlap the electrode pad 2, a barrier metal layer 5 formed on the electrode pad 2, and a solder bump 6 formed on the barrier metal layer 5. The outer circumferential end 5b of the barrier metal layer 5 is formed inside the first opening 3a of the passivation layer 3 in a planar view. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

この発明は、半導体装置に関し、特に、半導体チップがフリップチップ接合された半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip is flip-chip bonded.

従来、半導体チップがフリップチップ接合された半導体パッケージ（半導体装置）が知られている。このような半導体パッケージに搭載される半導体チップには、フリップチップ接合を行うための半田バンプ（バンプ電極）が形成されている（たとえば、特許文献１参照）。   Conventionally, a semiconductor package (semiconductor device) in which semiconductor chips are flip-chip bonded is known. Solder bumps (bump electrodes) for performing flip chip bonding are formed on a semiconductor chip mounted on such a semiconductor package (see, for example, Patent Document 1).

図１６〜図１８は、特許文献１に記載された従来の半導体装置の構造を示した概略断面図である。従来の半導体装置では、図１６に示すように、半導体基板５０１の上面上に、電極パッド部５０２が形成されている。なお、半導体基板５０１の上面には、ＩＣやＬＳＩなどの回路（図示せず）が作り込まれている。また、半導体基板５０１の上面上には、半導体基板５０１の上面を保護するための保護層５０３が形成されている。この保護層５０３には、電極パッド部５０２上の所定領域を露出させる開口部５０３ａが設けられている。また、電極パッド部５０２上には、バリアメタル層５０４を介してバンプ電極５０５が形成されている。このバリアメタル層５０４は、その周縁部５０４ａが保護層５０３上に乗り上げるように、電極パッド部５０２上に形成されている。   16 to 18 are schematic cross-sectional views showing the structure of a conventional semiconductor device described in Patent Document 1. FIG. In the conventional semiconductor device, an electrode pad portion 502 is formed on the upper surface of a semiconductor substrate 501 as shown in FIG. Note that a circuit (not shown) such as an IC or an LSI is formed on the upper surface of the semiconductor substrate 501. A protective layer 503 for protecting the upper surface of the semiconductor substrate 501 is formed on the upper surface of the semiconductor substrate 501. The protective layer 503 is provided with an opening 503 a that exposes a predetermined region on the electrode pad portion 502. A bump electrode 505 is formed on the electrode pad portion 502 via a barrier metal layer 504. The barrier metal layer 504 is formed on the electrode pad portion 502 so that the peripheral edge portion 504 a rides on the protective layer 503.

また、図１７に示すように、バンプ電極５０５が形成された半導体基板５０１は、上面（回路面）がプリント基板５０６と対向するようにフェースダウンでプリント基板５０６上に配置され、バンプ電極５０５によって、プリント基板５０６の電極５０７とフリップチップ接合されている。   As shown in FIG. 17, the semiconductor substrate 501 on which the bump electrode 505 is formed is disposed on the printed board 506 face down so that the upper surface (circuit surface) faces the printed board 506, and the bump electrode 505 Flip chip bonding is performed with the electrode 507 of the printed circuit board 506.

特開２００７−１３０６３号公報JP 2007-13063 A

上記特許文献１に記載された従来の半導体装置では、バリアメタル層５０４の周縁部５０４ａが保護層５０３上に乗り上げるように構成されているので、図１７および図１８に示すように、半導体基板５０１とプリント基板５０６との熱膨張係数の差に起因する熱応力がバンプ電極５０５に加わった際に、保護層５０３におけるバリアメタル層５０４の外周端部５０４ｂ下の領域（外周端部５０４ｂに対応する領域）に亀裂が発生し易くなるという不都合がある。このため、保護層５０３が破断し易くなるので、保護層５０３が破断した場合には、保護層５０３の破断に起因して、半導体装置の信頼性が低下するという問題点がある。   In the conventional semiconductor device described in Patent Document 1, the peripheral portion 504a of the barrier metal layer 504 is configured to run on the protective layer 503. Therefore, as shown in FIGS. When the thermal stress caused by the difference in thermal expansion coefficient between the printed circuit board 506 and the printed circuit board 506 is applied to the bump electrode 505, the protective layer 503 has a region below the outer peripheral end 504b of the barrier metal layer 504 (corresponding to the outer peripheral end 504b There is an inconvenience that cracks are likely to occur in the region. For this reason, since the protective layer 503 is easily broken, when the protective layer 503 is broken, there is a problem that reliability of the semiconductor device is lowered due to the breakage of the protective layer 503.

この発明は、上記のような課題を解決するためになされたものであり、この発明の１つの目的は、信頼性の低下を抑制することが可能な半導体装置を提供することである。   The present invention has been made to solve the above-described problems, and one object of the present invention is to provide a semiconductor device capable of suppressing a decrease in reliability.

上記目的を達成するために、この発明の一の局面による半導体装置は、基板の表面上に形成された電極パッド部と、電極パッド部の上面を露出させる第１開口部を含み、基板の表面上に、電極パッド部の一部と重なるように形成された第１保護層と、電極パッド部上に形成されたバリアメタル層と、バリアメタル層上に形成されたバンプ電極とを備えている。そして、バリアメタル層は、平面的に見て、外周端部が第１保護層の第１開口部の内側に形成されている。   In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes an electrode pad portion formed on a surface of a substrate, and a first opening that exposes an upper surface of the electrode pad portion. A first protective layer formed on the electrode pad portion so as to overlap with the electrode pad portion, a barrier metal layer formed on the electrode pad portion, and a bump electrode formed on the barrier metal layer are provided. . The barrier metal layer has an outer peripheral end formed inside the first opening of the first protective layer as viewed in a plan view.

この一の局面による半導体装置では、上記のように、バリアメタル層を、平面的に見て、外周端部が第１保護層の第１開口部の内側に形成されるように構成することによって、バリアメタル層の外周端部の下方には第１保護層が形成されないので、プリント基板上に基板をフリップチップ接合した際に、基板とプリント基板との熱膨張係数の差に起因する熱応力がバンプ電極に加わった場合でも、第１保護層に亀裂が発生するのを抑制することができる。このため、第１保護層の破断を抑制することができるので、第１保護層の破断に起因する半導体装置の信頼性の低下を抑制することができる。   In the semiconductor device according to this aspect, as described above, the barrier metal layer is configured so that the outer peripheral end portion is formed inside the first opening of the first protective layer when seen in a plan view. Since the first protective layer is not formed below the outer peripheral edge of the barrier metal layer, when the substrate is flip-chip bonded onto the printed circuit board, thermal stress caused by the difference in thermal expansion coefficient between the circuit board and the printed circuit board Even when is added to the bump electrode, it is possible to prevent the first protective layer from cracking. For this reason, since the fracture | rupture of a 1st protective layer can be suppressed, the fall of the reliability of the semiconductor device resulting from the fracture | rupture of a 1st protective layer can be suppressed.

上記一の局面による半導体装置において、好ましくは、第１保護層上の所定領域および電極パッド部上の所定領域を覆うように形成された第２保護層をさらに備え、バリアメタル層は、第２保護層上に周縁部を位置させた状態で、電極パッド部上に形成されている。このように構成すれば、電極パッド部上にバリアメタル層を形成する際に、容易に、バリアメタル層を、平面的に見て、外周端部が第１保護層の第１開口部の内側に位置するように形成することができる。   In the semiconductor device according to the above aspect, it is preferable that the semiconductor device further includes a second protective layer formed so as to cover a predetermined region on the first protective layer and a predetermined region on the electrode pad portion, It is formed on the electrode pad part with the peripheral part positioned on the protective layer. According to this structure, when the barrier metal layer is formed on the electrode pad portion, the barrier metal layer is easily seen in a plan view, and the outer peripheral end is inside the first opening of the first protective layer. It can form so that it may be located in.

この場合において、好ましくは、第２保護層には、電極パッド部の上面を露出させるとともに、第１開口部よりも小さい開口幅を有する第２開口部が設けられており、第２開口部を規定する端縁部は、傾斜形状を有している。このように構成すれば、バリアメタル層の周縁部を第２保護層上に形成した場合でも、バリアメタル層の破断を抑制することができる。このため、第１保護層の破断に起因する半導体装置の信頼性の低下を抑制することができることに加えて、バリアメタル層の破断に起因する半導体装置の信頼性の低下をも抑制することができるので、より容易に、半導体装置の信頼性の低下を抑制することができる。   In this case, the second protective layer is preferably provided with a second opening having an opening width smaller than that of the first opening and exposing the upper surface of the electrode pad portion. The defining edge has an inclined shape. If comprised in this way, even when the peripheral part of a barrier metal layer is formed on a 2nd protective layer, a fracture | rupture of a barrier metal layer can be suppressed. For this reason, in addition to being able to suppress a decrease in reliability of the semiconductor device due to the breakage of the first protective layer, it is also possible to suppress a decrease in reliability of the semiconductor device due to the breakage of the barrier metal layer. Therefore, a decrease in reliability of the semiconductor device can be suppressed more easily.

上記第２保護層が形成された構成において、好ましくは、第２保護層は、ポリイミドから構成されている。このように構成すれば、より容易に、第１保護層の破断を抑制することができる。   In the configuration in which the second protective layer is formed, the second protective layer is preferably made of polyimide. If comprised in this way, the fracture | rupture of a 1st protective layer can be suppressed more easily.

上記一の局面による半導体装置において、電極パッド部を、アルミニウム含む材料から構成することができるとともに、バリアメタル層を、チタンを含む材料から構成することができ、かつ、バンプ電極を、半田バンプから構成することができる。   In the semiconductor device according to the above aspect, the electrode pad portion can be made of a material containing aluminum, the barrier metal layer can be made of a material containing titanium, and the bump electrode can be made of a solder bump. Can be configured.

以上のように、本発明によれば、信頼性の低下を抑制することが可能な半導体装置を容易に得ることができる。   As described above, according to the present invention, a semiconductor device capable of suppressing a decrease in reliability can be easily obtained.

以下、本発明を具体化した実施形態を図面に基づいて説明する。なお、一実施形態による半導体装置は、半導体チップがフリップチップ接合されたＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージ型の半導体装置である。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below with reference to the drawings. The semiconductor device according to an embodiment is a BGA (Ball Grid Array) package type semiconductor device in which semiconductor chips are flip-chip bonded.

図１は、本発明の一実施形態による半導体装置の構造を示した断面図である。図２は、図１に示した本発明の一実施形態による半導体装置における半導体チップの電極部の構造を示した断面図である。図３〜図５は、本発明の一実施形態による半導体装置の構造を説明するための図である。まず、図１〜図５を参照して、本発明の一実施形態による半導体装置の構造について説明する。   FIG. 1 is a cross-sectional view illustrating the structure of a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view showing the structure of the electrode portion of the semiconductor chip in the semiconductor device according to the embodiment of the present invention shown in FIG. 3 to 5 are views for explaining the structure of a semiconductor device according to an embodiment of the present invention. First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.

一実施形態による半導体装置は、図１に示すように、半導体チップ１０と、半導体チップ１０が実装されるプリント基板２０と、半導体チップ１０を封止する樹脂封止層３０とを備えている。なお、樹脂封止層３０は、たとえば、エポキシ樹脂などの熱硬化性樹脂によって構成されている。   As shown in FIG. 1, the semiconductor device according to the embodiment includes a semiconductor chip 10, a printed circuit board 20 on which the semiconductor chip 10 is mounted, and a resin sealing layer 30 that seals the semiconductor chip 10. In addition, the resin sealing layer 30 is comprised by thermosetting resins, such as an epoxy resin, for example.

半導体チップ１０は、シリコン基板などの半導体基板１からなり、半導体基板１の上面には、たとえば、ＩＣやＬＳＩなどの回路（図示せず）が作り込まれている。なお、半導体基板１は、本発明の「基板」の一例である。   The semiconductor chip 10 includes a semiconductor substrate 1 such as a silicon substrate, and a circuit (not shown) such as an IC or an LSI is formed on the upper surface of the semiconductor substrate 1. The semiconductor substrate 1 is an example of the “substrate” in the present invention.

また、半導体基板１の上面上には、図２および図３に示すように、アルミニウムまたはアルミニウム合金からなる電極パッド部２が形成されている。また、半導体基板１の上面上には、窒化シリコンからなるパッシベーション層３が形成されている。このパッシベーション層３には、電極パッド部２の所定領域を露出させる第１開口部３ａが形成されている。なお、第１開口部３ａは、図４に示すように、平面的に見て、略円形形状を有しており、約８５μｍ〜約９５μｍの開口幅Ｄ１に形成されている。また、パッシベーション層３は、電極パッド部２の周縁部と重なるように半導体基板１の上面上に形成されている。なお、パッシベーション層３は、本発明の「第１保護層」の一例である。   On the upper surface of the semiconductor substrate 1, as shown in FIGS. 2 and 3, an electrode pad portion 2 made of aluminum or an aluminum alloy is formed. A passivation layer 3 made of silicon nitride is formed on the upper surface of the semiconductor substrate 1. In the passivation layer 3, a first opening 3 a that exposes a predetermined region of the electrode pad portion 2 is formed. As shown in FIG. 4, the first opening 3a has a substantially circular shape in plan view, and is formed with an opening width D1 of about 85 μm to about 95 μm. The passivation layer 3 is formed on the upper surface of the semiconductor substrate 1 so as to overlap with the peripheral edge of the electrode pad portion 2. The passivation layer 3 is an example of the “first protective layer” in the present invention.

また、パッシベーション層３上の所定領域、および、電極パッド部２上の所定領域には、ポリイミドからなる絶縁保護層４が形成されている。この絶縁保護層４には、図３および図４に示すように、パッシベーション層３の第１開口部３ａの開口幅Ｄ１（約８５μｍ〜約９５μｍ）よりも小さい開口幅Ｄ２（約５５μｍ〜約６５μｍ）を有する第２開口部４ａが設けられている。なお、第２開口部４ａは、図４に示すように、平面的に見て、略円形形状を有しており、第１開口部３ａとほぼ同心円状に形成されている。また、絶縁保護層４の第２開口部４ａを規定する端縁部４ｂは、傾斜形状に形成されている。なお、絶縁保護層４は、本発明の「第２保護層」の一例である。   An insulating protective layer 4 made of polyimide is formed in a predetermined region on the passivation layer 3 and a predetermined region on the electrode pad portion 2. As shown in FIGS. 3 and 4, the insulating protective layer 4 has an opening width D2 (about 55 μm to about 65 μm) smaller than the opening width D1 (about 85 μm to about 95 μm) of the first opening 3a of the passivation layer 3. ) Having a second opening 4a. As shown in FIG. 4, the second opening 4a has a substantially circular shape in plan view, and is formed substantially concentrically with the first opening 3a. Moreover, the edge part 4b which prescribes | regulates the 2nd opening part 4a of the insulating protective layer 4 is formed in the inclined shape. The insulating protective layer 4 is an example of the “second protective layer” in the present invention.

また、電極パッド部２上には、図２および図３に示すように、約１０μｍの厚みを有するとともに、チタン（Ｔｉ）からなるバリアメタル層５が、周縁部５ａを絶縁保護層４上の端縁部４ｂ近傍領域に位置させた状態で形成されている。なお、バリアメタル層５は、図４に示すように、平面的に見て、略円形形状を有しており、第１開口部３ａおよび第２開口部４ａとほぼ同心円状に形成されている。   2 and 3, the barrier metal layer 5 having a thickness of about 10 μm and made of titanium (Ti) is disposed on the electrode pad portion 2, and the peripheral portion 5 a is formed on the insulating protective layer 4. It is formed in a state where it is positioned in the vicinity of the edge 4b. As shown in FIG. 4, the barrier metal layer 5 has a substantially circular shape in plan view, and is formed substantially concentrically with the first opening 3a and the second opening 4a. .

ここで、本実施形態では、バリアメタル層５は、平面的に見て、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に位置するように形成されている。すなわち、バリアメタル層５は、図３または図４に示すように、パッシベーション層３の第１開口部３ａの幅Ｄ１以下の幅Ｄ３（約７０μｍ〜約８０μｍ）に構成されている。   Here, in the present embodiment, the barrier metal layer 5 is formed so that the outer peripheral end portion 5b is positioned inside the first opening 3a of the passivation layer 3 in plan view. That is, as shown in FIG. 3 or FIG. 4, the barrier metal layer 5 is configured to have a width D3 (about 70 μm to about 80 μm) that is equal to or smaller than the width D1 of the first opening 3a of the passivation layer 3.

また、バリアメタル層５上には、図２に示すように、約７０μｍ〜約１００μｍの高さ（厚み）を有する球状の半田バンプ６が形成されている。この半田バンプ６は、バリアメタル層５を介して、電極パッド部２と電気的に接続されている。また、半田バンプ６は、バリアメタル層５の上面に加えて、バリアメタル層５の外周端部５ｂとも接触するように、バリアメタル層５上に形成されている。すなわち、半田バンプ６は、バリアメタル層５の外周端部５ｂを覆うように、バリアメタル層５に接合されている。これにより、上面のみに半田バンプ６が接合される場合に比べて、接合面積が大きくなるので、半田バンプ６とバリアメタル層５との接合強度が向上する。なお、半田バンプ６は、本発明の「バンプ電極」の一例である。   On the barrier metal layer 5, as shown in FIG. 2, spherical solder bumps 6 having a height (thickness) of about 70 μm to about 100 μm are formed. The solder bump 6 is electrically connected to the electrode pad portion 2 through the barrier metal layer 5. Further, the solder bump 6 is formed on the barrier metal layer 5 so as to come into contact with the outer peripheral end 5 b of the barrier metal layer 5 in addition to the upper surface of the barrier metal layer 5. That is, the solder bump 6 is joined to the barrier metal layer 5 so as to cover the outer peripheral end 5 b of the barrier metal layer 5. Thereby, compared with the case where the solder bump 6 is bonded only to the upper surface, the bonding area is increased, so that the bonding strength between the solder bump 6 and the barrier metal layer 5 is improved. The solder bump 6 is an example of the “bump electrode” in the present invention.

また、図１に示すプリント基板２０は、ガラスエポキシ樹脂などから構成されており、多層構造の配線層（図示せず）を有している。また、プリント基板２０の上面上には、半導体チップ１０の半田バンプ６と電気的に接続される接続パッド部２１（図５参照）が複数形成されている。また、プリント基板２０の下面上には、接続パッド部２１と電気的に接続された電極端子２２が複数形成されている。この電極端子２２は、球状の半田バンプ６から構成されており、プリント基板２０の下面上に格子状に配列されている。   Further, the printed board 20 shown in FIG. 1 is made of glass epoxy resin or the like, and has a wiring layer (not shown) having a multilayer structure. A plurality of connection pad portions 21 (see FIG. 5) that are electrically connected to the solder bumps 6 of the semiconductor chip 10 are formed on the upper surface of the printed circuit board 20. In addition, a plurality of electrode terminals 22 electrically connected to the connection pad portion 21 are formed on the lower surface of the printed circuit board 20. The electrode terminals 22 are composed of spherical solder bumps 6 and are arranged on the lower surface of the printed circuit board 20 in a grid pattern.

また、半田バンプ６が形成された半導体チップ１０は、図１および図５に示すように、フェースダウンでプリント基板２０上に実装されている。具体的には、図５に示すように、半導体チップ１０は、上面（回路面）がプリント基板２０と対向するように配置され、半導体チップ１０の半田バンプ６が、プリント基板２０の接続パッド部２１にフリップチップ接合されている。これにより、半田バンプ６と接続パッド部２１とが電気的に接続される。   The semiconductor chip 10 on which the solder bumps 6 are formed is mounted on the printed circuit board 20 face down as shown in FIGS. Specifically, as shown in FIG. 5, the semiconductor chip 10 is disposed so that the upper surface (circuit surface) faces the printed circuit board 20, and the solder bumps 6 of the semiconductor chip 10 are connected pad portions of the printed circuit board 20. 21 is flip-chip bonded. Thereby, the solder bump 6 and the connection pad part 21 are electrically connected.

なお、半導体チップ１０とプリント基板２０との間には、図１に示すように、シリコン系樹脂、エポキシ樹脂、または、アクリル系樹脂などからなる樹脂部材４０が充填されている。   As shown in FIG. 1, a resin member 40 made of silicon resin, epoxy resin, acrylic resin, or the like is filled between the semiconductor chip 10 and the printed circuit board 20.

本実施形態では、上記のように、バリアメタル層５を、平面的に見て、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に形成されるように構成することによって、バリアメタル層５の外周端部５ｂの下方にはパッシベーション層３が形成されないので、プリント基板２０上に半導体チップ１０（半導体基板１）をフリップチップ接合した際に、半導体チップ１０とプリント基板２０との熱膨張係数の差に起因する熱応力が半田バンプ６に加わった場合でも、パッシベーション層３に亀裂が発生するのを抑制することができる。このため、パッシベーション層３の破断を抑制することができるので、パッシベーション層３の破断に起因する半導体装置の信頼性の低下を抑制することができる。   In the present embodiment, as described above, the barrier metal layer 5 is configured such that the outer peripheral end portion 5b is formed inside the first opening 3a of the passivation layer 3 in a plan view, thereby providing a barrier. Since the passivation layer 3 is not formed below the outer peripheral end 5 b of the metal layer 5, when the semiconductor chip 10 (semiconductor substrate 1) is flip-chip bonded onto the printed substrate 20, the semiconductor chip 10 and the printed substrate 20 Even when thermal stress due to the difference in thermal expansion coefficient is applied to the solder bumps 6, it is possible to suppress the generation of cracks in the passivation layer 3. For this reason, since the fracture | rupture of the passivation layer 3 can be suppressed, the fall of the reliability of the semiconductor device resulting from the fracture | rupture of the passivation layer 3 can be suppressed.

なお、バリアメタル層５の外周端部５ｂの下方には、絶縁保護層４が形成されている一方、この絶縁保護層４は、パッシベーション層３を構成する窒化シリコンに比べて柔らかいポリイミドから構成されているため、バリアメタル層５の周縁部５ａが絶縁保護層４上に形成された場合でも、絶縁保護層４が破断されるのを抑制することができる。   An insulating protective layer 4 is formed below the outer peripheral end portion 5b of the barrier metal layer 5. On the other hand, the insulating protective layer 4 is made of polyimide that is softer than silicon nitride constituting the passivation layer 3. Therefore, even when the peripheral edge portion 5a of the barrier metal layer 5 is formed on the insulating protective layer 4, it is possible to suppress the insulating protective layer 4 from being broken.

また、本実施形態では、絶縁保護層４を、パッシベーション層３上の所定領域および電極パッド部２上の所定領域に形成するとともに、バリアメタル層５を、絶縁保護層４上に周縁部５ａを位置させた状態で電極パッド部２上に形成することによって、後述する電極部の形成プロセスにおいて、容易に、バリアメタル層５を、平面的に見て、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に位置するように形成することができる。   In this embodiment, the insulating protective layer 4 is formed in a predetermined region on the passivation layer 3 and a predetermined region on the electrode pad portion 2, and the barrier metal layer 5 is formed on the insulating protective layer 4 with a peripheral portion 5 a. By forming the electrode pad portion 2 on the electrode pad portion 2 in a positioned state, the outer peripheral end portion 5b of the passivation layer 3 can be easily seen in the planar view of the barrier metal layer 5 in the electrode portion forming process described later. It can form so that it may be located inside the 1 opening part 3a.

また、本実施形態では、絶縁保護層４の第２開口部４ａを規定する端縁部４ｂを、傾斜形状に形成することによって、バリアメタル層５の周縁部５ａを絶縁保護層４上に形成した場合でも、バリアメタル層５を破断し難くすることができる。このため、パッシベーション層３の破断に起因する半導体装置の信頼性の低下を抑制することができることに加えて、バリアメタル層５の破断に起因する半導体装置の信頼性の低下をも抑制することができるので、より容易に、半導体装置の信頼性の低下を抑制することができる。   In the present embodiment, the peripheral edge portion 5a of the barrier metal layer 5 is formed on the insulating protective layer 4 by forming the edge portion 4b defining the second opening 4a of the insulating protective layer 4 in an inclined shape. Even in this case, the barrier metal layer 5 can be made difficult to break. For this reason, in addition to being able to suppress a decrease in the reliability of the semiconductor device due to the breakage of the passivation layer 3, it is also possible to suppress a decrease in the reliability of the semiconductor device due to the breakage of the barrier metal layer 5. Therefore, a decrease in reliability of the semiconductor device can be suppressed more easily.

図６〜図１２は、一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。次に、図１〜４および図６〜図１２を参照して、半導体チップ１０の電極部の形成プロセスについて説明する。   6 to 12 are cross-sectional views illustrating a process for forming an electrode portion of a semiconductor chip in a semiconductor device according to an embodiment. Next, with reference to FIGS. 1-4 and FIGS. 6-12, the formation process of the electrode part of the semiconductor chip 10 is demonstrated.

まず、図６に示すように、電極パッド部２が形成された半導体基板１の上面上の全面に、プラズマＣＶＤ法などを用いて、窒化シリコンからなるパッシベーション層３を形成する。次に、図７に示すように、フォトリソグラフィ技術などを用いて、パッシベーション層３上の所定領域にレジスト５０を形成する。そして、レジスト５０をマスクとして、エッチングにより、パッシベーション層３の所定領域を除去する。これにより、パッシベーション層３に、電極パッド部２上の所定領域を露出させる第１開口部３ａが形成される。この際、第１開口部３ａは、開口幅Ｄ１（約８５μｍ〜約９５μｍ、図３および図４参照）に形成する。その後、レジスト５０を除去する。   First, as shown in FIG. 6, a passivation layer 3 made of silicon nitride is formed on the entire upper surface of the semiconductor substrate 1 on which the electrode pad portion 2 is formed using a plasma CVD method or the like. Next, as shown in FIG. 7, a resist 50 is formed in a predetermined region on the passivation layer 3 by using a photolithography technique or the like. Then, a predetermined region of the passivation layer 3 is removed by etching using the resist 50 as a mask. As a result, a first opening 3 a that exposes a predetermined region on the electrode pad portion 2 is formed in the passivation layer 3. At this time, the first opening 3a is formed to have an opening width D1 (about 85 μm to about 95 μm, see FIGS. 3 and 4). Thereafter, the resist 50 is removed.

続いて、図８に示すように、スピンコーティング法などを用いて、全面に、ポリイミドからなる絶縁保護層１４を形成する。そして、フォトリソグラフィ技術およびエッチング技術を用いて、絶縁保護層１４の所定領域を除去する。その後、熱処理を行うことによって、絶縁保護層１４をフローさせる。これにより、図９に示すような絶縁保護層４が得られる。すなわち、絶縁保護層１４（図８参照）に、パッシベーション層３の第１開口部３ａの開口幅Ｄ１（約８５μｍ〜約９５μｍ）よりも小さい開口幅Ｄ２（約５５μｍ〜約６５μｍ）を有する第２開口部４ａが形成されるとともに、その第２開口部４ａを規定する端縁部４ｂが、傾斜形状に形成される。   Subsequently, as shown in FIG. 8, an insulating protective layer 14 made of polyimide is formed on the entire surface by using a spin coating method or the like. Then, a predetermined region of the insulating protective layer 14 is removed using a photolithography technique and an etching technique. Thereafter, the insulating protective layer 14 is caused to flow by performing heat treatment. Thereby, the insulating protective layer 4 as shown in FIG. 9 is obtained. That is, the insulating protective layer 14 (see FIG. 8) has a second opening width D2 (about 55 μm to about 65 μm) smaller than the opening width D1 (about 85 μm to about 95 μm) of the first opening 3a of the passivation layer 3. The opening 4a is formed, and the edge 4b that defines the second opening 4a is formed in an inclined shape.

次に、図１０に示すように、蒸着法などを用いて、全面に、約１０μｍの厚みを有するとともに、チタン（Ｔｉ）からなるバリアメタル層１５を形成する。次に、図１１に示すように、フォトリソグラフィ技術およびエッチング技術を用いて、バリアメタル層１５上の所定領域にレジスト６０を形成する。この際、パッシベーション層３の第１開口部３ａの内側に対応する領域が開口するように、レジスト６０をパターニングする。そして、メッキ法などを用いて、レジスト６０をマスクとして、バリアメタル層１５上に半田層１６を形成する。   Next, as shown in FIG. 10, a barrier metal layer 15 having a thickness of about 10 μm and made of titanium (Ti) is formed on the entire surface by vapor deposition or the like. Next, as shown in FIG. 11, a resist 60 is formed in a predetermined region on the barrier metal layer 15 by using a photolithography technique and an etching technique. At this time, the resist 60 is patterned so that a region corresponding to the inside of the first opening 3a of the passivation layer 3 is opened. Then, the solder layer 16 is formed on the barrier metal layer 15 by using a plating method or the like using the resist 60 as a mask.

その後、図１２に示すように、レジスト６０（図１１参照）を除去するとともに、半田層１６の周囲のバリアメタル層１５をエッチングにより除去する。これにより、図４に示したような、平面的に見て、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に形成されたバリアメタル層５が電極パッド部２上に形成される。また、図２および図３に示したように、電極パッド部２上に形成されたバリアメタル層５は、周縁部５ａが絶縁保護層４上に位置するように構成される。   Thereafter, as shown in FIG. 12, the resist 60 (see FIG. 11) is removed, and the barrier metal layer 15 around the solder layer 16 is removed by etching. As a result, as shown in FIG. 4, the barrier metal layer 5 having the outer peripheral end portion 5 b formed inside the first opening 3 a of the passivation layer 3 is formed on the electrode pad portion 2 as viewed in plan. The As shown in FIGS. 2 and 3, the barrier metal layer 5 formed on the electrode pad portion 2 is configured such that the peripheral edge portion 5 a is positioned on the insulating protective layer 4.

なお、図１２に示すように、上記した絶縁保護層４を形成することによって、電極パッド部２の上面が露出しないように構成することが可能となる。このため、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に形成されるように、バリアメタル層１５のエッチングを行ったとしても、電極パッド部２までエッチングされるのを抑制することが可能となる。これにより、容易に、バリアメタル層５を、平面的に見て、外周端部５ｂがパッシベーション層３の第１開口部３ａの内側に位置するように形成することが可能となる。   As shown in FIG. 12, by forming the insulating protective layer 4 described above, the upper surface of the electrode pad portion 2 can be configured not to be exposed. For this reason, even if the barrier metal layer 15 is etched so that the outer peripheral end 5b is formed inside the first opening 3a of the passivation layer 3, the etching to the electrode pad 2 is suppressed. It becomes possible. Thereby, the barrier metal layer 5 can be easily formed so that the outer peripheral end portion 5b is located inside the first opening 3a of the passivation layer 3 when viewed in plan.

最後に、リフロー炉内で加熱することによって、半田層１６を一旦溶融することにより、半田層１６を、図２に示したような球状の半田バンプ６に形成する。これにより、バリアメタル層５上に、半田バンプ６（図２参照）が形成される。このようにして、図１に示した本発明の一実施形態による半導体装置における半導体チップ１０の電極部が形成される。   Finally, the solder layer 16 is once melted by heating in a reflow furnace to form the solder layer 16 on the spherical solder bumps 6 as shown in FIG. As a result, solder bumps 6 (see FIG. 2) are formed on the barrier metal layer 5. Thus, the electrode part of the semiconductor chip 10 in the semiconductor device according to the embodiment shown in FIG. 1 is formed.

なお、今回開示された実施形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施形態の説明ではなく特許請求の範囲によって示され、さらに特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれる。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

たとえば、上記実施形態では、絶縁保護層をポリイミドから構成した例を示したが、本発明はこれに限らず、絶縁保護層をポリイミド以外のＢＣＢ（ベンゾシクロブテン）や、フッ素樹脂などの有機材料から構成してもよい。   For example, in the said embodiment, although the example which comprised the insulating protective layer from the polyimide was shown, this invention is not restricted to this, Organic materials, such as BCB (benzocyclobutene) other than a polyimide, a fluororesin, are not limited to this. You may comprise.

また、上記実施形態では、ポリイミドからなる絶縁保護層を備えた例を示したが、本発明はこれに限らず、図１３に示す本実施形態の第１変形例による半導体チップ１１０のように、絶縁保護層を備えない構成にしてもよい。この場合、ポリイミドからなる絶縁保護層の代わりにレジストを用いて上記実施形態と同様の電極構造を形成し、その後、レジストを除去することによって、絶縁保護層を備えない構成にすることが可能となる。なお、半導体チップ１１０とプリント基板との間に、図１に示したような樹脂部材４０を充填することによって、レジストを除去した場合でも、フリップチップ接合の信頼性の低下が抑制される。また、図１４に示す本実施形態の第２変形例による半導体チップ２１０のように、電極パッド部２上のパッシベーション層３の第１開口部３ａによって露出された領域の全面に、バリアメタル層２０５を形成するようにしてもよい。この際、バリアメタル層２０５の厚みをパッシベーション層３の厚みよりも大きくすることによって、半田バンプ６を、バリアメタル層２０５の外周端部２０５ａを覆うように形成することが可能となる。さらに、図１５に示す本実施形態の第３変形例による半導体チップ３１０のように、バリアメタル層３０５の外周端部３０５ａを、パッシベーション層３の第１開口部３ａから所定の距離を隔てた領域に形成するようにしてもよい。   Moreover, in the said embodiment, although the example provided with the insulation protective layer which consists of polyimides was shown, this invention is not restricted to this, Like the semiconductor chip 110 by the 1st modification of this embodiment shown in FIG. A configuration without an insulating protective layer may also be used. In this case, it is possible to form an electrode structure similar to that of the above embodiment by using a resist instead of the insulating protective layer made of polyimide, and then removing the resist to make a configuration without the insulating protective layer. Become. In addition, by filling the resin member 40 as shown in FIG. 1 between the semiconductor chip 110 and the printed board, even when the resist is removed, a decrease in reliability of flip chip bonding is suppressed. Further, like the semiconductor chip 210 according to the second modification of the present embodiment shown in FIG. 14, the barrier metal layer 205 is formed on the entire surface of the region exposed by the first opening 3 a of the passivation layer 3 on the electrode pad portion 2. May be formed. At this time, by making the thickness of the barrier metal layer 205 larger than the thickness of the passivation layer 3, the solder bump 6 can be formed so as to cover the outer peripheral end portion 205 a of the barrier metal layer 205. Further, like the semiconductor chip 310 according to the third modification of the present embodiment shown in FIG. 15, the outer peripheral end portion 305 a of the barrier metal layer 305 is separated from the first opening 3 a of the passivation layer 3 by a predetermined distance. You may make it form in.

また、上記実施形態では、パッシベーション層を窒化シリコンから構成した例を示したが、本発明はこれに限らず、パッシベーション層を窒化シリコン以外の無機材料から構成してもよい。たとえば、パッシベーション層を、ＳｉＯＮや、ＳｉＯ2などから構成してもよい。 Moreover, although the example which comprised the passivation layer from the silicon nitride was shown in the said embodiment, this invention is not restricted to this, You may comprise a passivation layer from inorganic materials other than silicon nitride. For example, the passivation layer may be made of SiON, SiO 2 or the like.

また、上記実施形態では、電極パッド部をアルミニウムまたはアルミニウム合金から構成した例を示したが、本発明はこれに限らず、電極パッド部を、アルミニウムまたはアルミニウム合金以外の金属材料である金（Ａｕ）や、ＡｌＣｕ合金などから構成してもよい。   Moreover, although the example which comprised the electrode pad part from aluminum or aluminum alloy was shown in the said embodiment, this invention is not restricted to this, Gold (Au which is metal materials other than aluminum or aluminum alloy is used for an electrode pad part. ) Or an AlCu alloy.

また、上記実施形態では、バリアメタル層を、チタンから構成した例を示したが、本発明はこれに限らず、バリアメタル層を、チタン以外の材料から構成してもよい。チタン以外の材料としては、たとえば、ＴｉＮや、Ｔａなどが考えられる。また、バリアメタル層を、複数の金属層が積層された積層構造にしてもよい。   Moreover, although the example which comprised the barrier metal layer from titanium was shown in the said embodiment, this invention is not restricted to this, You may comprise a barrier metal layer from materials other than titanium. Examples of materials other than titanium include TiN and Ta. Further, the barrier metal layer may have a laminated structure in which a plurality of metal layers are laminated.

また、上記実施形態では、半田バンプからなるバンプ電極を電極パッド部上に形成した例を示したが、本発明はこれに限らず、半田バンプ以外のメタルバンプ（たとえば、ＡｕバンプやＣｕバンプ）などからなるバンプ電極を電極パッド部上に形成してもよい。   In the above-described embodiment, an example in which bump electrodes made of solder bumps are formed on the electrode pad portion has been shown. However, the present invention is not limited to this, and metal bumps other than solder bumps (for example, Au bumps and Cu bumps) A bump electrode made of the above may be formed on the electrode pad portion.

また、上記実施形態では、半導体チップとプリント基板との間に、樹脂部材を充填した例を示したが、本発明はこれに限らず、半導体チップとプリント基板との間に、樹脂部材を充填しない構成してもよい。   Moreover, in the said embodiment, although the example which filled the resin member between the semiconductor chip and the printed circuit board was shown, this invention is not limited to this, The resin member is filled between the semiconductor chip and the printed circuit board. It may be configured not to.

本発明の一実施形態による半導体装置の構造を示した断面図である。It is sectional drawing which showed the structure of the semiconductor device by one Embodiment of this invention. 図１に示した本発明の一実施形態による半導体装置における半導体チップの電極部の構造を示した断面図である。FIG. 2 is a cross-sectional view showing a structure of an electrode portion of a semiconductor chip in the semiconductor device according to the embodiment of the present invention shown in FIG. 1. 図１に示した本発明の一実施形態による半導体装置における半導体チップの半田バンプを省略した電極部の構造を示した断面図である。FIG. 2 is a cross-sectional view showing a structure of an electrode portion in which a solder bump of a semiconductor chip is omitted in the semiconductor device according to the embodiment of the present invention shown in FIG. 1. 図１に示した本発明の一実施形態による半導体装置における半導体チップの半田バンプを省略した電極部の平面図である。FIG. 2 is a plan view of an electrode part in which a solder bump of a semiconductor chip is omitted in the semiconductor device according to the embodiment of the present invention shown in FIG. 1. 半導体チップをプリント基板上に実装した状態を示した断面図である。It is sectional drawing which showed the state which mounted the semiconductor chip on the printed circuit board. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本発明の一実施形態による半導体装置における半導体チップの電極部の形成プロセスを説明するための断面図である。It is sectional drawing for demonstrating the formation process of the electrode part of the semiconductor chip in the semiconductor device by one Embodiment of this invention. 本実施形態の第１変形例による半導体チップの電極部の構造を示した断面図である。It is sectional drawing which showed the structure of the electrode part of the semiconductor chip by the 1st modification of this embodiment. 本実施形態の第２変形例による半導体チップの電極部の構造を示した断面図である。It is sectional drawing which showed the structure of the electrode part of the semiconductor chip by the 2nd modification of this embodiment. 本実施形態の第３変形例による半導体チップの電極部の構造を示した断面図である。It is sectional drawing which showed the structure of the electrode part of the semiconductor chip by the 3rd modification of this embodiment. 特許文献１に記載された従来の半導体装置の構造を示した概略断面図である。It is the schematic sectional drawing which showed the structure of the conventional semiconductor device described in patent document 1. 特許文献１に記載された従来の半導体装置の構造を示した概略断面図である。It is the schematic sectional drawing which showed the structure of the conventional semiconductor device described in patent document 1. 図１７のＡ部の拡大断面図である。It is an expanded sectional view of the A section of FIG.

符号の説明Explanation of symbols

１ 半導体基板（基板）
２ 電極パッド部
３ パッシベーション層（第１保護層）
３ａ 第１開口部
４ 絶縁保護層（第２保護層）
４ａ 第２開口部
４ｂ 端縁部
５、１５、２０５、３０５ バリアメタル層
５ａ 周縁部
５ｂ 外周端部
６ 半田バンプ（バンプ電極）
１０、１１０、２１０、３１０ 半導体チップ
２０ プリント基板
２１ 接続パッド部
２２ 電極端子
３０ 樹脂封止層
４０ 樹脂部材 1 Semiconductor substrate (substrate)
2 Electrode pad part 3 Passivation layer (first protective layer)
3a First opening 4 Insulating protective layer (second protective layer)
4a Second opening 4b Edge 5, 5, 205, 305 Barrier metal layer 5a Perimeter 5b Outer edge 6 Solder bump (bump electrode)
10, 110, 210, 310 Semiconductor chip 20 Printed circuit board 21 Connection pad part 22 Electrode terminal 30 Resin sealing layer 40 Resin member

Claims (15)

基板の表面上に形成された電極パッド部と、
前記電極パッド部の上面を露出させる第１開口部を含み、前記基板の表面上に、前記電極パッド部の一部と重なるように形成された第１保護層と、
前記電極パッド部上に形成されたバリアメタル層と、
前記バリアメタル層上に形成されたバンプ電極と、
前記第１保護層上の所定領域および前記電極パッド部上の所定領域を覆うように形成された第２保護層と、
を備え、
前記バリアメタル層は、平面的に見て、外周端部が前記第１保護層の前記第１開口部の内側に形成され、
前記バリアメタル層は、前記第２保護層上に周縁部を位置させた状態で、前記電極パッド部上に形成され、
前記第２保護層には、前記電極パッド部の上面を露出させるとともに、前記第１開口部よりも小さい開口幅を有する第２開口部が設けられており、
前記第２開口部を規定する端縁部は、傾斜形状を有し、
前記バンプ電極は、前記バリアメタル層の前記外周端部を覆うように形成され、
前記バリアメタル層の前記周縁部の前記電極パッド部側の表面は、断面視において曲率の中心が前記電極パッド部側のみにある曲面で形成されることを特徴とする、半導体装置。 An electrode pad formed on the surface of the substrate;
A first protective layer that includes a first opening that exposes an upper surface of the electrode pad portion, and is formed on the surface of the substrate so as to overlap a part of the electrode pad portion;
A barrier metal layer formed on the electrode pad portion;
A bump electrode formed on the barrier metal layer;
A second protective layer formed so as to cover a predetermined region on the first protective layer and a predetermined region on the electrode pad portion;
With
The barrier metal layer has an outer peripheral end formed inside the first opening of the first protective layer, as viewed in plan.
The barrier metal layer is formed on the electrode pad portion with a peripheral portion positioned on the second protective layer,
The second protective layer is provided with a second opening that exposes an upper surface of the electrode pad portion and has an opening width smaller than the first opening.
The edge portion defining the second opening has an inclined shape,
The bump electrode is formed so as to cover the outer peripheral end of the barrier metal layer ,
The surface of the peripheral portion of the barrier metal layer on the electrode pad portion side is formed by a curved surface having a center of curvature only on the electrode pad portion side in a sectional view . 前記第２保護層は、ポリイミドから構成されていることを特徴とする、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second protective layer is made of polyimide. 前記電極パッド部は、アルミニウムを含む材料から構成されているとともに、前記バリアメタル層は、チタンを含む材料から構成されており、かつ、前記バンプ電極は、半田バンプから構成されていることを特徴とする、請求項１または２に記載の半導体装置。   The electrode pad portion is made of a material containing aluminum, the barrier metal layer is made of a material containing titanium, and the bump electrode is made of a solder bump. The semiconductor device according to claim 1 or 2. 前記バンプ電極は、半田バンプに代えて、Ａｕバンプ又はＣｕバンプから構成されていることを特徴とする、請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the bump electrode is made of an Au bump or a Cu bump instead of the solder bump. 前記バリアメタル層の厚さが１０μｍであることを特徴とする、請求項１〜４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thickness of the barrier metal layer is 10 μm. 前記バリアメタル層は、平面的に見て、前記第１開口部と略同心円状に形成されていることを特徴とする、請求項１〜５のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the barrier metal layer is formed substantially concentrically with the first opening when viewed in a plan view. 前記第２開口部は、平面的に見て、前記第１開口部と略同心円状に形成されていることを特徴とする、請求項１〜６のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second opening is formed substantially concentrically with the first opening when viewed in a plan view. 前記バリアメタル層の幅は、平面的に見て、７０μｍ〜８０μｍであることを特徴とする、請求項１〜７のいずれか１項に記載の半導体装置。   8. The semiconductor device according to claim 1, wherein a width of the barrier metal layer is 70 μm to 80 μm in a plan view. 9. 前記電極パッド部と、前記第１保護層と、前記バリアメタル層と、前記バンプ電極と、前記第２保護層と、を含む半導体チップと、
前記半導体チップが実装されるプリント基板と、
前記半導体チップと前記プリント基板との間に充填される樹脂部材と、
をさらに備えることを特徴とする、請求項１〜８のいずれか１項に記載の半導体装置。 A semiconductor chip including the electrode pad portion, the first protective layer, the barrier metal layer, the bump electrode, and the second protective layer;
A printed circuit board on which the semiconductor chip is mounted;
A resin member filled between the semiconductor chip and the printed circuit board;
The semiconductor device according to claim 1, further comprising: 前記プリント基板は、ガラスエポキシ樹脂で構成されることを特徴とする、請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein the printed board is made of glass epoxy resin. 前記樹脂部材は、エポキシ樹脂またはアクリル系樹脂からなることを特徴とする、請求項９または１０に記載の半導体装置。   The semiconductor device according to claim 9, wherein the resin member is made of an epoxy resin or an acrylic resin. 前記第１開口部の開口幅は、平面的に見て、８５μｍ〜９５μｍであることを特徴とする、請求項１〜１１のいずれか１項に記載の半導体装置。   12. The semiconductor device according to claim 1, wherein an opening width of the first opening portion is 85 μm to 95 μm in a plan view. 前記第２開口部の開口幅は、平面的に見て、５５μｍ〜６５μｍであることを特徴とする、請求項１〜１２のいずれか１項に記載の半導体装置。   13. The semiconductor device according to claim 1, wherein an opening width of the second opening is 55 μm to 65 μm in a plan view. 前記第１保護層は、ＳｉＯＮ又はＳｉＯ2で構成されることを特徴とする、請求項１〜１３のいずれか１項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first protective layer is made of SiON or SiO 2 . 前記電極パッド部は、アルミニウム又はアルミニウム合金で構成されることを特徴とする、請求項１〜１４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode pad portion is made of aluminum or an aluminum alloy.
JP2007159351A 2007-06-15 2007-06-15 Semiconductor device Active JP5280650B2 (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2007159351A JP5280650B2 (en) 2007-06-15 2007-06-15 Semiconductor device
US12/663,563 US8436467B2 (en) 2007-06-15 2008-06-13 Semiconductor device
PCT/JP2008/060844 WO2008153128A1 (en) 2007-06-15 2008-06-13 Semiconductor device
TW097122280A TW200915511A (en) 2007-06-15 2008-06-13 Semiconductor device
CN2008800202805A CN101681859B (en) 2007-06-15 2008-06-13 Semiconductor device
US13/856,905 US8922010B2 (en) 2007-06-15 2013-04-04 Semiconductor device
US14/337,959 US9053991B2 (en) 2007-06-15 2014-07-22 Semiconductor device
US14/491,556 US9123628B2 (en) 2007-06-15 2014-09-19 Semiconductor device
US14/803,207 US9466583B2 (en) 2007-06-15 2015-07-20 Semiconductor device
US15/219,912 US9685419B2 (en) 2007-06-15 2016-07-26 Semiconductor device
US15/591,456 US10032739B2 (en) 2007-06-15 2017-05-10 Semiconductor device
US16/018,128 US10510700B2 (en) 2007-06-15 2018-06-26 Semiconductor device
US16/683,647 US11037897B2 (en) 2007-06-15 2019-11-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007159351A JP5280650B2 (en) 2007-06-15 2007-06-15 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013108550A Division JP5656301B2 (en) 2013-05-23 2013-05-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2008311530A JP2008311530A (en) 2008-12-25
JP5280650B2 true JP5280650B2 (en) 2013-09-04

Family

ID=40238865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007159351A Active JP5280650B2 (en) 2007-06-15 2007-06-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5280650B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013030498A (en) * 2009-11-12 2013-02-07 Panasonic Corp Semiconductor device
CN103180936A (en) * 2010-10-12 2013-06-26 株式会社安川电机 Electronic device and electronic component
JP5921142B2 (en) * 2011-10-26 2016-05-24 キヤノン株式会社 Liquid discharge head and method of manufacturing liquid discharge head

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01187949A (en) * 1988-01-22 1989-07-27 Fujitsu Ltd Manufacture of semiconductor device
JPH09129647A (en) * 1995-10-27 1997-05-16 Toshiba Corp Semiconductor element
JP4058198B2 (en) * 1999-07-02 2008-03-05 富士通株式会社 Manufacturing method of semiconductor device
JP2001035876A (en) * 1999-07-23 2001-02-09 Nec Corp Flip-chip connection structure, semiconductor device and fabrication thereof
JP2005259848A (en) * 2004-03-10 2005-09-22 Toshiba Corp Semiconductor device and its manufacturing method
JP2006147648A (en) * 2004-11-16 2006-06-08 Seiko Epson Corp Manufacturing method of electronic device, electronic device, manufacturing apparatus of electronic device, and electronic equipment

Also Published As

Publication number Publication date
JP2008311530A (en) 2008-12-25

Similar Documents

Publication Publication Date Title
US11037897B2 (en) Semiconductor device
US11257767B2 (en) Interconnect crack arrestor structure and methods
JP4772844B2 (en) Wafer level package and manufacturing method thereof
US20070200251A1 (en) Method of fabricating ultra thin flip-chip package
JP2012028708A (en) Semiconductor device
WO2011058680A1 (en) Semiconductor device
JP5280650B2 (en) Semiconductor device
US9524944B2 (en) Method for fabricating package structure
JP5243734B2 (en) Semiconductor device
JP2013021085A (en) Interposer, method for manufacturing the same, semiconductor device, and method for manufacturing the same
JP5656301B2 (en) Semiconductor device
JP2000164617A (en) Chip-sized package and its manufacture
JP4812673B2 (en) Semiconductor device
JP2008028109A (en) Semiconductor device and manufacturing method therefor
JP2008091774A (en) Semiconductor device
JP4536757B2 (en) Semiconductor package and semiconductor package manufacturing method
JP2011034988A (en) Semiconductor device
JP2005236318A (en) Semiconductor device, its manufacturing method, circuit board, and electronic apparatus
JP2008135628A (en) Semiconductor device
JP2008028108A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120723

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130507

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130523

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5280650

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: R3D03

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250