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JP2005197355A - Semiconductor device and manufacturing method thereof, circuit board, and electronic equipment - Google Patents

Semiconductor device and manufacturing method thereof, circuit board, and electronic equipment Download PDF

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JP2005197355A
JP2005197355A JP2004000401A JP2004000401A JP2005197355A JP 2005197355 A JP2005197355 A JP 2005197355A JP 2004000401 A JP2004000401 A JP 2004000401A JP 2004000401 A JP2004000401 A JP 2004000401A JP 2005197355 A JP2005197355 A JP 2005197355A
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electrodes
semiconductor device
insulating film
opening end
portions
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Naoya Sato
直也 佐藤
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for improving packaging precision, a method for manufacturing the semiconductor device, a circuit board, and electronic equipment. <P>SOLUTION: The semiconductor device comprises a substrate 1 in which a plurality of leads are formed, an insulating film 7 for covering leads so that one portion of each lead is arranged in an opening 8, and a semiconductor chip 5 that is mounted on the substrate 1 while a plurality of electrodes 6 and a lead are electrically connected opposingly in the opening 8. An open end 9 in the insulating film 7 includes first and second sections 10, 11 positioned in a region overlapping with the semiconductor chip 5. The first section 10 is positioned so that it opposes a first side 18 facing the first direction of either electrode 6, and the second section 11 is positioned so that it opposes the second side 19 facing the second direction crossing the first direction of either electrode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。   The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

ＣＯＦ(chip on film)構造の半導体装置では、その使用目的から、自由に折り曲げることが可能な薄膜の絶縁テープがフレキシブル配線板の基材として使用されている。この絶縁テープの表面に配置された配線パターンのうち各インナーリードが、その接続部で、半導体チップの対応するバンプと電気的に接続される。そして、この半導体装置は、アウターリードを介して、液晶パネルやプリント基板などに接続されることになる（例えば、特許文献１参照）。
特開２００２−１２４５４４号公報（図１） In a semiconductor device having a COF (chip on film) structure, a thin insulating tape that can be bent freely is used as a substrate of a flexible wiring board for the purpose of use. Of the wiring pattern arranged on the surface of the insulating tape, each inner lead is electrically connected to a corresponding bump of the semiconductor chip at the connecting portion. And this semiconductor device is connected to a liquid crystal panel, a printed circuit board, etc. via an outer lead (for example, refer to patent documents 1).
JP 2002-124544 A (FIG. 1)

従来のボンディング方法におけるＣＯＦ用フィルムのインナーリードと半導体チップのバンプとのボンディングでは、半導体チップの４辺に設置されたバンプに対して、インナーリードは、４辺それぞれに対して垂直に配置されるため、バンプとインナーリードの位置決めは、Ｘ方向及びＹ方向同時に行わなければ、インナーリードが隣接するバンプに接触して、ショートしてしまうという問題があった。   In the bonding of the inner leads of the COF film and the bumps of the semiconductor chip in the conventional bonding method, the inner leads are arranged perpendicular to the four sides with respect to the bumps installed on the four sides of the semiconductor chip. Therefore, if positioning of the bump and the inner lead is not performed simultaneously in the X direction and the Y direction, there is a problem that the inner lead comes into contact with the adjacent bump and short-circuits.

また、全てのバンプと全てのインナーリードの位置決めを同時に行わなければ、インナーリードが所定のバンプに接続されない場合に生じるオープン不良が発生してしまうという問題があった。   Further, if all the bumps and all the inner leads are not positioned at the same time, there is a problem that an open defect occurs when the inner leads are not connected to the predetermined bumps.

例えば、液晶駆動装置では、バンプの数が５００個以上あり、さらに、バンプサイズ及びインナーリードの微細精密化が進んでいるため、幅は狭くなり近接している。そのため、インナーリードとバンプは高精度で位置決めする必要がある。   For example, in the liquid crystal drive device, the number of bumps is 500 or more, and the bump size and the inner lead are becoming finer, so the width is narrow and close. Therefore, it is necessary to position the inner lead and the bump with high accuracy.

また、前記のボンディング方法におけるインナーリードとバンプとの位置決めでは、ＣＯＦ用フィルムの絶縁テープが半透明であり、インナーリード及びバンプの画像を同時に得ることが困難であるため、半導体チップのバンプを有する面と、基板の配線パターンを有する面との間に、光学系を配置させて、両方の面をカメラで撮像して位置を把握して位置決めを行っていた。これによれば、光学系が複雑であるため、誤差が生じやすく実装精度の低下を招いていた。   In the positioning of the inner lead and the bump in the bonding method, the insulating tape of the COF film is translucent, and it is difficult to obtain images of the inner lead and the bump at the same time. An optical system is arranged between the surface and the surface having the wiring pattern of the board, and both surfaces are imaged with a camera to determine the position and positioning is performed. According to this, since the optical system is complicated, an error is likely to occur and the mounting accuracy is reduced.

本発明の目的は、実装精度を向上させる半導体装置及びその製造方法、回路基板並びに電子機器を提供することにある。   An object of the present invention is to provide a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device that improve mounting accuracy.

（１）本発明に係る半導体装置は、複数のリードが形成されてなる基板と、
開口を有し、前記開口内にそれぞれの前記リードの一部が配置されるように前記リードを覆う絶縁膜と、複数の電極を有し、前記基板に搭載され、前記開口内で前記複数の電極と前記リードが対向して電気的に接続されてなる半導体チップと、を有し、
前記絶縁膜の前記開口端部は、前記半導体チップとオーバーラップする領域内に位置する第１及び第２の部分を含み、
前記第１の部分は、いずれかの前記電極の第１の方向を向く第１の側面に対向するように位置し、前記第２の部分は、いずれかの前記電極の前記第１の方向に交差する第２の方向を向く第２の側面に対向するように位置してなる。本発明によれば、絶縁膜に第１及び２の部分を設けているので、半導体チップを基板上に載せたときに、電極の第１及び２の側面を第１及び２の部分にそれぞれ対向させることにより、容易に半導体チップと基板の位置合わせができる。その結果、高精度な実装が可能となる。
（２）この半導体装置において、
前記絶縁膜の前記開口端部は、前記半導体チップとオーバーラップする領域内に位置する第３及び第４の部分をさらに含み、
前記第３の部分は、いずれかの前記電極の前記第１の方向とは反対の第３の方向を向く第３の側面に対向するように位置し、前記第４の部分は、いずれかの前記電極の前記第２の方向とは反対の第４の方向を向く第４の側面に対向するように位置してもよい。
（３）この半導体装置において、
前記複数の電極は、前記半導体チップの第１，２，３及び４の辺を含む矩形の面に設けられ、
前記第１の辺と前記第３の辺とは、向き合うように位置し、前記第２の辺と前記第４の辺とは、向き合うように位置してもよい。
（４）この半導体装置において、
前記第１，２，３及び４の部分は、それぞれ複数設けられ、
前記複数の第１の部分は、前記第１の辺に沿って並ぶ第１のグループの電極に対向するように位置し、前記複数の第２の部分は、前記第２の辺に沿って並ぶ第２のグループの電極に対向するように位置し、前記複数の第３の部分は、前記第３の辺に沿って並ぶ第３のグループの電極に対向するように位置し、前記複数の第４の部分は、前記第４の辺に沿って並ぶ第４のグループの電極に対向するように位置してもよい。
（５）この半導体装置において、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記絶縁膜の前記開口端部は、前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面に隣接する第１の凸部と、前記第２の辺に最も近い前記電極の前記第２の辺を向く側面である前記第２の側面に隣接する第２の凸部と、前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面に隣接する第３の凸部と、前記第４の辺に最も近い前記電極の前記第４の辺を向く側面である前記第４の側面に隣接する第４の凸部と、を含んでもよい。
（６）この半導体装置において、
前記開口端部の全体が前記半導体チップとオーバーラップする領域内に位置してもよい。
（７）この半導体装置において、
前記開口端部の全体が前記半導体チップとオーバーラップする領域内に位置し、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記絶縁膜の前記開口端部は、前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面と、それぞれの列において最も前記第２の辺に近いいずれかの前記電極の前記第２の辺を向く側面である前記第２の側面と、前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面と、それぞれの列において最も前記第４の辺に近いいずれかの前記電極の前記第４の辺を向く側面である第４の側面とに隣接するように形成されてもよい。
（８）この半導体装置において、
前記複数の電極は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループをなす第１の電極と、前記第１の辺に沿って前記第１の電極よりも前記第１の辺から離れた位置で間隔をあけて並ぶ１つのグループをなす第２の電極と、を含み、
前記第１及び第２の電極は、千鳥状に配置されてなり、
前記絶縁膜の前記開口端部は、複数の凸部が間隔をあけて形成されてなる、くし形形状を含み、
前記くし形形状は、それぞれの前記凸部が隣同士の一対の前記第１の電極の間を通って、いずれかの前記第２の電極に隣接するように形成されてもよい。
（９）この半導体装置において、
前記絶縁膜の前記開口端部は、複数の凹凸部が形成されてなる、くし形形状を含み、
前記くし形形状は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループの電極の隣に、それぞれの前記凸部が隣同士の一対の前記電極の間に配置され、それぞれの前記凹部内に、いずれかの前記電極が隣接するように形成されもよい。
（１０）この半導体装置において、
前記複数の電極は、前記第１の辺に対して斜めに交差する直線に沿って配列される一対の電極を含み、
前記絶縁膜の前記開口端部は、前記半導体チップの角部から、前記一対の電極の間の方向に突出する凸部を有してもよい。
（１１）本発明に係る回路基板は、上記半導体装置が電気的に接続されてなる。
（１２）本発明に係る電子機器は、上記半導体装置を有する。
（１３）本発明に係る半導体装置の製造方法は、半導体チップの複数の電極と、基板に形成された複数のリードと、を対向するように位置合わせすること、及び、前記電極と前記リードを電気的に接続することを含み、
前記リードは、開口を有する絶縁膜によって、前記開口内にそれぞれの前記リードの一部が配置されるように覆われ、前記絶縁膜の前記開口端部は、第１及び第２の部分を含み、
前記位置合わせは、いずれかの前記電極の第１の方向を向く第１の側面を、前記第１の部分に接触させて、前記第１の方向及びその反対方向の位置合わせを行うこと、及び、いずれかの前記電極の前記第１の方向に交差する第２の方向を向く第２の側面を、前記第２の部分に接触させて、前記第２の方向及びその反対方向の位置合わせを行うことを含む。本発明によれば、上述した効果を達成できる基板を使用するので、位置合わせの実装精度を向上して工程を行うことができる。
（１４）この半導体装置の製造方法において、
前記絶縁膜の前記開口端部は、第３及び第４の部分をさらに含み、
前記位置合わせは、いずれかの前記電極の前記第１の方向とは反対の第３の方向を向く第３の側面を、前記第３の部分に接触させて、前記第３の方向の位置合わせを行うこと、及び、いずれかの前記電極の前記第２の方向とは反対の第４の方向を向く第４の側面を、前記第４の部分に接触させて、前記第４の方向の位置合わせを行うことを含んでもよい。
（１５）この半導体装置の製造方法において、
前記複数の電極は、前記半導体チップの第１，２，３及び４の辺を含む矩形の面に設けられ、
前記第１の辺と前記第３の辺とは、向き合うように位置し、前記第２の辺と前記第４の辺とは、向き合うように位置してもよい。
（１６）この半導体装置の製造方法において、
前記第１，２，３及び４の部分は、それぞれ複数設けられ、
前記位置合わせで、前記第１の辺に沿って並ぶ第１のグループの電極を、前記複数の第１の部分に対向するように配置し、前記第２の辺に沿って並ぶ第２のグループの電極を、前記複数の第２の部分に対向するように配置し、前記第３の辺に沿って並ぶ第３のグループの電極を、前記複数の第３の部分に対向するように配置し、前記第４の辺に沿って並ぶ第４のグループの電極を、前記複数の第４の部分に対向するように配置してもよい。
（１７）この半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記位置合わせは、前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面を、前記絶縁膜の前記開口端部の第１の凸部に接触させて、前記第1の方向の位置合わせを行うこと、前記第２の辺に最も近い前記電極の前記第２の辺を向く側面である前記第２の側面を、前記絶縁膜の前記開口端部の第２の凸部に接触させて、前記第２の方向の位置合わせを行うこと、前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面を、前記絶縁膜の前記開口端部の第３の凸部に接触させて、前記第３の方向の位置合わせを行うこと、及び、前記第４の辺に最も近い前記電極の前記第４の辺を向く側面である前記第４の側面を、前記絶縁膜の前記開口端部の第４の凸部に接触させて、前記第４の方向の位置合わせを行うことを含んでもよい。
（１８）この半導体装置の製造方法において、
前記位置合わせで、前記開口端部の全体を、前記半導体チップとオーバーラップする領域内に配置してもよい。
（１９）この半導体装置の製造方法において、
前記開口端部は、全体が前記半導体チップとオーバーラップするように形成され、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記位置合わせは、前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面を、前記絶縁膜の前記開口端部に接触させて、前記第１の方向の位置合わせを行うこと、それぞれの列において最も前記第２の辺に近いいずれかの前記電極の前記第２の辺を向く側面である前記第２の側面を、前記絶縁膜の前記開口端部に接触させて、前記第２の方向の位置合わせを行うこと、前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面を、前記絶縁膜の前記開口端部に接触させて、前記第３の方向の位置合わせを行うこと、それぞれの列において最も前記第４の辺に近いいずれかの前記電極の前記第４の辺を向く側面である第４の側面を、前記絶縁膜の前記開口端部に接触させて、前記第４の方向の位置合わせを行うことを含んでもよい。
（２０）この半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループをなす第１の電極と、前記第１の辺に沿って前記第１の電極よりも前記第１の辺から離れた位置で間隔をあけて並ぶ１つのグループをなす第２の電極と、を含み、
前記第１及び第２の電極は、千鳥状に配置されてなり、
前記絶縁膜の前記開口端部は、複数の凸部が間隔をあけて形成されてなる、くし形形状を含み、
前記位置合わせで、前記くし形形状を、それぞれの前記凸部が隣同士の一対の前記第１の電極の間を通って、いずれかの前記第２の電極に隣接するように配置してもよい。
（２１）この半導体装置の製造方法において、
前記絶縁膜の前記開口端部は、複数の凹凸部が形成されてなる、くし形形状を含み、
前記位置合わせで、前記くし形形状を、前記第１の辺に沿って間隔をあけて並ぶ１つのグループの電極の隣に、それぞれの前記凸部が隣同士の一対の前記電極の間に配置し、それぞれの前記凹部内に、いずれかの前記電極が隣接するように配置してもよい。
（２２）この半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に対して斜めに交差する直線に沿って配列される一対の電極を含み、
前記位置合わせで、前記絶縁膜の前記開口端部を、前記半導体チップの角部から、前記一対の電極の間の方向に突出する凸部になるように配置してもよい。 (1) A semiconductor device according to the present invention includes a substrate on which a plurality of leads are formed,
An insulating film that covers the leads so that a portion of each of the leads is disposed in the opening, and a plurality of electrodes, and is mounted on the substrate, and the plurality of the leads are disposed in the opening. A semiconductor chip in which the electrodes and the leads are electrically connected to face each other,
The opening end of the insulating film includes first and second portions located in a region overlapping with the semiconductor chip,
The first portion is positioned so as to face a first side surface facing the first direction of any one of the electrodes, and the second portion is in the first direction of any one of the electrodes. It is located so as to face the second side surface facing the second direction that intersects. According to the present invention, since the first and second portions are provided in the insulating film, the first and second side surfaces of the electrode are opposed to the first and second portions, respectively, when the semiconductor chip is placed on the substrate. By doing so, it is possible to easily align the semiconductor chip and the substrate. As a result, highly accurate mounting is possible.
(2) In this semiconductor device,
The opening end of the insulating film further includes third and fourth portions located in a region overlapping with the semiconductor chip,
The third portion is positioned so as to face a third side surface facing a third direction opposite to the first direction of any one of the electrodes, and the fourth portion is any one of The electrode may be positioned so as to face a fourth side surface facing a fourth direction opposite to the second direction.
(3) In this semiconductor device,
The plurality of electrodes are provided on a rectangular surface including the first, second, third and fourth sides of the semiconductor chip,
The first side and the third side may be positioned so as to face each other, and the second side and the fourth side may be positioned so as to face each other.
(4) In this semiconductor device,
A plurality of the first, second, third and fourth portions are provided,
The plurality of first portions are positioned to face a first group of electrodes arranged along the first side, and the plurality of second portions are arranged along the second side. The plurality of third portions are positioned to face the second group of electrodes, and are positioned to face the third group of electrodes arranged along the third side, and The portion 4 may be positioned so as to face the fourth group of electrodes arranged along the fourth side.
(5) In this semiconductor device,
The plurality of electrodes are arranged in a plurality of rows along the first side,
The opening end portion of the insulating film includes a first convex portion adjacent to the first side surface, which is a side surface facing the first side of the electrode in the row closest to the first side, and the first A second convex portion adjacent to the second side surface, which is a side surface facing the second side of the electrode closest to the second side, and the third of the electrodes in a row closest to the third side. A third convex portion adjacent to the third side surface which is a side surface facing the side of the electrode, and an adjacent to the fourth side surface which is the side surface facing the fourth side of the electrode closest to the fourth side. And a fourth convex portion.
(6) In this semiconductor device,
The entire opening end may be located in a region overlapping with the semiconductor chip.
(7) In this semiconductor device,
The entire opening end is located in a region overlapping with the semiconductor chip,
The plurality of electrodes are arranged in a plurality of rows along the first side,
The opening end portion of the insulating film includes the first side surface which is a side surface facing the first side of the electrodes in the row closest to the first side, and the second side in each row. The second side surface that is the side surface facing the second side of any one of the electrodes that is close to the first side, and the side surface that faces the third side of the electrode in the row closest to the third side. 3 side surfaces and a fourth side surface which is a side surface facing the fourth side of any one of the electrodes closest to the fourth side in each row.
(8) In this semiconductor device,
The plurality of electrodes includes a first electrode forming a group arranged at intervals along the first side, and the first side along the first side than the first electrode. A second electrode that forms a group that is spaced apart at a distance from each other, and
The first and second electrodes are arranged in a staggered manner,
The opening end portion of the insulating film includes a comb shape, in which a plurality of convex portions are formed at intervals.
The comb shape may be formed such that each convex portion passes between a pair of adjacent first electrodes and is adjacent to any one of the second electrodes.
(9) In this semiconductor device,
The opening end portion of the insulating film includes a comb shape formed with a plurality of uneven portions,
The comb-shaped shape is arranged next to one group of electrodes arranged at intervals along the first side, and each of the convex portions is arranged between a pair of adjacent electrodes, Any one of the electrodes may be formed adjacent to the recess.
(10) In this semiconductor device,
The plurality of electrodes include a pair of electrodes arranged along a straight line that obliquely intersects the first side,
The opening end portion of the insulating film may have a convex portion protruding from a corner portion of the semiconductor chip in a direction between the pair of electrodes.
(11) A circuit board according to the present invention is formed by electrically connecting the semiconductor device.
(12) An electronic apparatus according to the present invention includes the semiconductor device.
(13) In the method of manufacturing a semiconductor device according to the present invention, the plurality of electrodes of the semiconductor chip and the plurality of leads formed on the substrate are aligned so as to face each other, and the electrodes and the leads are aligned. Including electrical connection,
The lead is covered with an insulating film having an opening so that a part of the lead is disposed in the opening, and the opening end of the insulating film includes first and second portions. ,
The alignment is performed by bringing a first side surface of any one of the electrodes facing the first direction into contact with the first portion to perform alignment in the first direction and the opposite direction; and The second side surface of the electrode facing the second direction intersecting the first direction is brought into contact with the second portion, and the alignment in the second direction and the opposite direction is performed. Including doing. According to the present invention, since the substrate that can achieve the above-described effect is used, the process can be performed with improved mounting accuracy of alignment.
(14) In this method of manufacturing a semiconductor device,
The opening end of the insulating film further includes third and fourth portions,
The alignment is performed by bringing a third side surface of any one of the electrodes facing a third direction opposite to the first direction into contact with the third portion, thereby aligning the third direction. And a fourth side surface of any one of the electrodes facing a fourth direction opposite to the second direction is brought into contact with the fourth portion, so that the position in the fourth direction is reached. It may also include performing a combination.
(15) In this method of manufacturing a semiconductor device,
The plurality of electrodes are provided on a rectangular surface including the first, second, third and fourth sides of the semiconductor chip,
The first side and the third side may be positioned so as to face each other, and the second side and the fourth side may be positioned so as to face each other.
(16) In this method of manufacturing a semiconductor device,
A plurality of the first, second, third and fourth portions are provided,
In the alignment, a second group of electrodes arranged along the first side is arranged so as to face the plurality of first portions, and arranged along the second side. Are arranged so as to face the plurality of second portions, and a third group of electrodes arranged along the third side are arranged so as to face the plurality of third portions. A fourth group of electrodes arranged along the fourth side may be arranged to face the plurality of fourth portions.
(17) In this method of manufacturing a semiconductor device,
The plurality of electrodes are arranged in a plurality of rows along the first side,
In the alignment, the first side surface, which is the side surface facing the first side of the electrodes in the row closest to the first side, is used as the first convex portion of the opening end of the insulating film. Performing the alignment in the first direction by contacting the second side surface, which is the side surface facing the second side of the electrode closest to the second side, the opening of the insulating film The second convex portion at the end is brought into contact with the alignment in the second direction, and the side that faces the third side of the electrode in the row closest to the third side is the first side 3 side surface is brought into contact with the third convex portion of the opening end portion of the insulating film to perform alignment in the third direction, and the electrode of the electrode closest to the fourth side The fourth side surface, which is a side surface facing the fourth side, is brought into contact with a fourth convex portion of the opening end of the insulating film, and the fourth side surface It may also include performing direction alignment.
(18) In this method of manufacturing a semiconductor device,
In the alignment, the entire opening end may be disposed in a region overlapping with the semiconductor chip.
(19) In this method of manufacturing a semiconductor device,
The opening end is formed so as to overlap the semiconductor chip as a whole,
The plurality of electrodes are arranged in a plurality of rows along the first side,
In the alignment, the first side surface, which is the side surface facing the first side of the electrode in the row closest to the first side, is brought into contact with the opening end of the insulating film, and The second side surface, which is the side surface facing the second side of any one of the electrodes closest to the second side in each column, is aligned in the direction of 1, The third side surface, which is a side surface facing the third side of the electrodes in the row closest to the third side, is aligned with the second direction in contact with the opening end, Positioning in the third direction in contact with the opening end of the insulating film, facing the fourth side of any one of the electrodes closest to the fourth side in each row A fourth side surface which is a side surface is brought into contact with the opening end of the insulating film, and It may include performing the direction of alignment.
(20) In this method of manufacturing a semiconductor device,
The plurality of electrodes includes a first electrode forming a group arranged at intervals along the first side, and the first side along the first side than the first electrode. A second electrode that forms a group that is spaced apart at a distance from each other, and
The first and second electrodes are arranged in a staggered manner,
The opening end portion of the insulating film includes a comb shape, in which a plurality of convex portions are formed at intervals.
In the alignment, the comb shape may be arranged so that each convex portion passes between a pair of adjacent first electrodes and is adjacent to any one of the second electrodes. Good.
(21) In this method of manufacturing a semiconductor device,
The opening end portion of the insulating film includes a comb shape formed with a plurality of uneven portions,
In the alignment, the comb-shaped shape is arranged next to one group of electrodes arranged at intervals along the first side, and each convex portion is arranged between a pair of adjacent electrodes. In addition, any of the electrodes may be disposed adjacent to each other in the recesses.
(22) In this method of manufacturing a semiconductor device,
The plurality of electrodes include a pair of electrodes arranged along a straight line that obliquely intersects the first side,
In the alignment, the opening end portion of the insulating film may be arranged to be a convex portion protruding from a corner portion of the semiconductor chip in a direction between the pair of electrodes.

以下に、本発明の実施の形態を、図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（第１の実施の形態）
図１は、本発明を適用した第１の実施の形態に係るＣＯＦ用フィルムの平面図であり、図２は、本実施の形態に係るＣＯＦ型半導体装置の断面図であリ、図３は、本実施の形態に係る図２のIII−III線断面図である。 (First embodiment)
FIG. 1 is a plan view of a film for COF according to a first embodiment to which the present invention is applied, FIG. 2 is a sectional view of a COF type semiconductor device according to the present embodiment, and FIG. FIG. 3 is a sectional view taken along line III-III in FIG. 2 according to the present embodiment.

（基板について）
本実施の形態に係る半導体装置には、図１に示すＣＯＦ用フィルム（基板）１が使用される。ＣＯＦ用フィルム１は、少なくとも１つの半導体チップを搭載するためのインターポーザとして使用される。ＣＯＦ用フィルム１は、複数の配線パターン２の支持部材である。ＣＯＦ用フィルム１は、フレキシブル性を有し、厚さ１５μｍ（または、２０、２５、３８、４０μｍ）の薄膜のポリイミド樹脂で形成されることが多いが、それ以外の周知の材料を使用することができる。このＣＯＦ用フィルム１の表面に厚さ８μｍ（または、９、１２、１５、１８μｍ）の銅箔パターンが接着剤を介在させずに形成されている。銅箔パターンの表面には図示しない錫メッキまたは金メッキが施されている。銅箔パターンには、インナーリード(リード)３およびアウターリード(リード)４を含む配線パターン２が含まれる。図より明らかなように、隣り合う２つのインナーリード３の間の間隔は、広いところと狭いところがある。配線パターン２上には、搭載される半導体チップの電極に対応して電気的に接続される部分（接続部）つまりインナーリード３の先端部と、外部の端子（液晶パネルやプリント基板などに形成された端子）に接続されるアウターリード４とを除いて、絶縁膜（例えば、ソルダーレジスト）７が塗布されており、これにより絶縁状態が確保される。 (About the board)
In the semiconductor device according to the present embodiment, a COF film (substrate) 1 shown in FIG. 1 is used. The COF film 1 is used as an interposer for mounting at least one semiconductor chip. The COF film 1 is a support member for the plurality of wiring patterns 2. The COF film 1 has flexibility and is often formed of a thin film polyimide resin having a thickness of 15 μm (or 20, 25, 38, 40 μm), but other known materials should be used. Can do. A copper foil pattern having a thickness of 8 μm (or 9, 12, 15, 18 μm) is formed on the surface of the COF film 1 without an adhesive. The surface of the copper foil pattern is subjected to tin plating or gold plating (not shown). The copper foil pattern includes a wiring pattern 2 including an inner lead (lead) 3 and an outer lead (lead) 4. As is apparent from the figure, the distance between two adjacent inner leads 3 is wide and narrow. On the wiring pattern 2, a portion (connection portion) that is electrically connected corresponding to an electrode of a semiconductor chip to be mounted, that is, a tip portion of the inner lead 3, and an external terminal (formed on a liquid crystal panel or a printed board) An insulating film (for example, solder resist) 7 is applied except for the outer lead 4 connected to the terminal), thereby ensuring an insulating state.

ＣＯＦ用フィルム１には、各配線パターン２について１つの（全体では複数の）絶縁膜の開口８が形成されている。絶縁膜の開口８を介して、半導体チップと、それとの電気的接続部（例えば、インナーリード３）とのボンディングを行うことができる。絶縁膜の開口８の形状は特に限定されず、半導体チップを完全に収容できる大きさであっても、一部を収容するだけの大きさであってもよい。   The COF film 1 has one insulating film opening 8 for each wiring pattern 2. The semiconductor chip can be bonded to the electrical connection portion (for example, the inner lead 3) with the semiconductor chip through the opening 8 of the insulating film. The shape of the opening 8 of the insulating film is not particularly limited, and may be a size that can completely accommodate a semiconductor chip or a size that can accommodate only a part.

配線パターン２は、ＣＯＦ用フィルム１の長手方向に並んで形成されてもよいし、幅方向に並んで形成されてもよいし、マトリクス状に（長手方向及び幅方向に並んで）形成されてもよい。それぞれの配線パターン２は、同一の形状であることが多いが、異なる形状であってもよい。例えば、ｎ種類の形状をなすｎ個の配線パターン２が並んで構成される配線パターングループを、繰り返して形成してもよい。複数の配線パターン２は、電気メッキを行うために、図示しないメッキリードで電気的に接続されていてもよい。   The wiring pattern 2 may be formed side by side in the longitudinal direction of the COF film 1, may be formed side by side in the width direction, or may be formed in a matrix (side by side in the longitudinal direction and width direction). Also good. Each wiring pattern 2 is often the same shape, but may be a different shape. For example, a wiring pattern group constituted by n wiring patterns 2 having n types of shapes may be repeatedly formed. The plurality of wiring patterns 2 may be electrically connected by a plating lead (not shown) in order to perform electroplating.

インナーリード３は、絶縁膜の開口８内に突出している。インナーリード３同士は、平行に形成されており、ＣＯＦ用フィルム１の長手方向に延びて形成されていてもよい。インナーリード３は、半導体チップの電極に対応する間隔で形成される。インナーリード３は、半導体チップとの電気的接続部である。   The inner lead 3 protrudes into the opening 8 of the insulating film. The inner leads 3 are formed in parallel, and may be formed extending in the longitudinal direction of the COF film 1. The inner leads 3 are formed at intervals corresponding to the electrodes of the semiconductor chip. The inner lead 3 is an electrical connection portion with the semiconductor chip.

（半導体装置）
図２は、ＣＯＦ用フィルム１の幅方向に延びる直線に沿った断面図である。 (Semiconductor device)
FIG. 2 is a cross-sectional view along a straight line extending in the width direction of the COF film 1.

ＣＯＦ型半導体装置６０は、ＣＯＦ用フィルム１と、各配線パターン２に電気的に接続された複数の半導体チップ５とを有する。   The COF type semiconductor device 60 includes a COF film 1 and a plurality of semiconductor chips 5 electrically connected to each wiring pattern 2.

半導体チップ５の平面状は一般的には矩形であり、長方形であっても正方形であってもよい。半導体チップ５の一方の面に、複数の電極６が形成されている。電極６は、半導体チップ５の面の少なくとも１辺（多くの場合、２辺又は４辺）に沿って並んでいる。半導体チップ５の外形が長方形である場合には、例えば液晶駆動用ＩＣのように長手方向に電極６が配列されていてもよいし、短手方向に電極６が配列されていてもよい。また、電極６は、半導体チップ５の面の端部に並んでいる場合と、中央部に並んでいる場合がある。各電極６は、アルミニウムなどで薄く平らに形成されたパッドと、その上に形成されたバンプと、からなることが多い。バンプが形成されない場合は、パッドのみが電極６となる。電極６の少なくとも一部を避けて半導体チップ５には、パッシベーション膜（図示しない）が形成されている。パッシベーション膜は、例えば、ＳｉＯ２、ＳｉＮ、ポリイミド樹脂などで形成することができる。   The planar shape of the semiconductor chip 5 is generally rectangular, and may be rectangular or square. A plurality of electrodes 6 are formed on one surface of the semiconductor chip 5. The electrodes 6 are arranged along at least one side (in many cases, two sides or four sides) of the surface of the semiconductor chip 5. When the outer shape of the semiconductor chip 5 is rectangular, the electrodes 6 may be arranged in the longitudinal direction as in a liquid crystal driving IC, for example, or the electrodes 6 may be arranged in the short direction. The electrode 6 may be arranged at the end of the surface of the semiconductor chip 5 or may be arranged at the center. Each electrode 6 is often composed of a thin flat pad made of aluminum or the like and a bump formed thereon. When the bump is not formed, only the pad becomes the electrode 6. A passivation film (not shown) is formed on the semiconductor chip 5 avoiding at least a part of the electrode 6. The passivation film can be formed of, for example, SiO2, SiN, polyimide resin, or the like.

半導体チップ５の電極６は、配線パターン２のインナーリード３にフェイスダウンボンディングしてもよい。   The electrode 6 of the semiconductor chip 5 may be face-down bonded to the inner lead 3 of the wiring pattern 2.

ＣＯＦ型半導体装置６０は、封止部３０を有してもよい。封止部３０は、少なくとも半導体チップ５の電極６と配線パターン２との電気的接続部（例えば、インナーリード３）を封止するものである。封止部３０は、樹脂で形成されることが多い。   The COF type semiconductor device 60 may include the sealing unit 30. The sealing portion 30 seals at least an electrical connection portion (for example, the inner lead 3) between the electrode 6 of the semiconductor chip 5 and the wiring pattern 2. The sealing part 30 is often formed of a resin.

また、配線パターン２における絶縁膜７によって覆われる部分と覆われない部分との境界では、封止部３０は、絶縁膜７の端部と重複することが好ましい。こうすることで、配線パターン２が露出することを防止できる。封止部３０は、ポッティングによって設けてもよい。   Moreover, it is preferable that the sealing portion 30 overlaps the end portion of the insulating film 7 at the boundary between the portion covered with the insulating film 7 and the portion not covered with the wiring pattern 2. By doing so, it is possible to prevent the wiring pattern 2 from being exposed. The sealing part 30 may be provided by potting.

例えば、図３に示すように、半導体チップ５は、第１，２，３及び４の辺１４，１５，１６，１７を含む矩形の面に、複数の電極６が形成されている。複数の電極６は、第１の辺１４に沿って複数列をなすように配列されている。第１の辺１４と第３の辺１６、第２の辺１５と第４の辺１７は、向き合うように位置している。   For example, as shown in FIG. 3, the semiconductor chip 5 has a plurality of electrodes 6 formed on a rectangular surface including the first, second, third, and fourth sides 14, 15, 16, and 17. The plurality of electrodes 6 are arranged in a plurality of rows along the first side 14. The first side 14 and the third side 16, and the second side 15 and the fourth side 17 are positioned so as to face each other.

絶縁膜の開口端部９は、半導体チップ５とオーバーラップする領域内に半導体チップ５とＣＯＦ用フィルム１との位置決めのための第１，２，３及び４の部分１０，１１，１２，１３の部分を複数含んでいる。   The opening end 9 of the insulating film has first, second, third, and fourth portions 10, 11, 12, 13 for positioning the semiconductor chip 5 and the COF film 1 in a region overlapping the semiconductor chip 5. Contains multiple parts.

第１の部分１０は、第１の辺１４に沿って並ぶ第１のグループの電極２２の第１の方向（図３においては下方向）を向く第１の側面１８に対向するように位置している。また、第２の部分１１は、第２の辺１５に沿って並ぶ第２のグループの電極２３の第２の方向（図３においては左方向）を向く第２の側面１９に対向するように位置している。また、第３の部分１２は、第３の辺１６に沿って並ぶ第３のグループの電極２４の第３の方向（図３においては上方向）を向く第３の側面２０に対向するように位置している。さらに、第４の部分１３は、第４の辺１７に沿って並ぶ第４のグループの電極２５の第４の方向（図３においては右方向）を向く第４の側面２１に対向するように位置している。   The first portion 10 is positioned so as to face the first side surface 18 facing the first direction (downward in FIG. 3) of the first group of electrodes 22 arranged along the first side 14. ing. The second portion 11 faces the second side surface 19 facing the second direction (left direction in FIG. 3) of the second group of electrodes 23 arranged along the second side 15. positioned. Further, the third portion 12 faces the third side surface 20 facing the third direction (upward in FIG. 3) of the third group of electrodes 24 arranged along the third side 16. positioned. Further, the fourth portion 13 faces the fourth side surface 21 facing the fourth direction (right direction in FIG. 3) of the fourth group of electrodes 25 arranged along the fourth side 17. positioned.

さらに、絶縁膜の開口端部９は、第１の辺１４に最も近い列の電極６の第１の辺１４を向く第１の側面１８に隣接する第１の凸部２６を含んでいる。また、第２の辺１５に最も近い電極６の第２の辺１５を向く第２の側面１９に隣接する第２の凸部２７を含んでいる。また、第３の辺１６に最も近い列の電極６の第３の辺１６を向く第３の側面２０に隣接する第３の凸部２８を含んでいる。さらに、第４の辺１７に最も近い電極６の第４の辺１７を向く第４の側面２１に隣接する第４の凸部２９を含んでいる。   Further, the opening end 9 of the insulating film includes a first convex portion 26 adjacent to the first side face 18 facing the first side 14 of the electrode 6 in the column closest to the first side 14. Further, a second convex portion 27 adjacent to the second side surface 19 facing the second side 15 of the electrode 6 closest to the second side 15 is included. Further, it includes a third convex portion 28 adjacent to the third side surface 20 facing the third side 16 of the electrode 6 in the row closest to the third side 16. Furthermore, a fourth convex portion 29 adjacent to the fourth side surface 21 facing the fourth side 17 of the electrode 6 closest to the fourth side 17 is included.

本発明によれば、このようにして形成されたＣＯＦ型半導体装置６０は、インナーリード３と電極６との位置決め精度が向上する。これにより、インナーリード３が、接続対象の電極６以外の電極６とショートしにくい。したがって、絶縁膜７に第１，２，３及び４の部分１０，１１，１２，１３を形成しない従来の半導体装置に比べて、インナーリード３の電極６との接続不良及びインナーリード３と隣り合う電極６とのショートが発生しにくく、実装精度の向上したＣＯＦ型半導体装置を提供することができる。   According to the present invention, the positioning accuracy of the inner lead 3 and the electrode 6 is improved in the COF type semiconductor device 60 formed in this way. Thereby, the inner lead 3 is not easily short-circuited with the electrodes 6 other than the electrode 6 to be connected. Therefore, compared with the conventional semiconductor device in which the first, second, third and fourth portions 10, 11, 12, and 13 are not formed in the insulating film 7, the connection with the electrode 6 of the inner lead 3 and the inner lead 3 are adjacent to each other. It is possible to provide a COF type semiconductor device in which a short circuit with the matching electrode 6 hardly occurs and the mounting accuracy is improved.

（半導体装置の製造方法）
本実施の形態に係るＣＯＦ型半導体装置は上述のように構成されており、以下その製造方法について説明する。 (Method for manufacturing semiconductor device)
The COF type semiconductor device according to the present embodiment is configured as described above, and a manufacturing method thereof will be described below.

第１，２，３及び４の部分１０，１１，１２，１３を形成した絶縁膜７パターンを有するＣＯＦ用フィルム１は、例えば、ポリイミド系絶縁テープからなるベースに、リードとなる銅箔を形成し、形成した銅箔の表面にリードパターンのレジスト膜を形成し、前記レジスト膜をマスクとして銅箔をエッチングし、その後、銅に錫、半田、金等をメッキすることで得られる。続いて、例えば、スクリーン印刷法を用いて、第１，２，３及び４の部分１０，１１，１２，１３を有する絶縁膜７を形成する。   The COF film 1 having the insulating film 7 pattern in which the first, second, third and fourth portions 10, 11, 12, and 13 are formed, for example, a copper foil serving as a lead is formed on a base made of polyimide insulating tape. Then, a resist film of a lead pattern is formed on the surface of the formed copper foil, the copper foil is etched using the resist film as a mask, and then copper, tin, solder, gold or the like is plated. Subsequently, the insulating film 7 having the first, second, third, and fourth portions 10, 11, 12, and 13 is formed by using, for example, a screen printing method.

図４は、本発明を適用した本実施の形態に係るＣＯＦ用フィルム上のインナーリードと半導体チップ上のバンプとの位置決めの説明図である。   FIG. 4 is an explanatory diagram of positioning of the inner leads on the COF film and the bumps on the semiconductor chip according to the present embodiment to which the present invention is applied.

インナーリード３と電極６との位置決めは、例えば、図４に示すように、１台の画像認識装置３１を用いて、ＣＯＦ用フィルム１越しに絶縁膜７に付加した第１，２，３及び４の部分１０，１１，１２，１３と、それぞれに対向する半導体チップ５の電極６の第１，２，３及び４の側面１８，１９，２０，２１の画像を認識させることにより大体の位置合わせができる。さらに、第１，２，３及び４の部分１０，１１，１２，１３に第１，２，３及び４の側面１８，１９，２０，２１を嵌め込むことにより正確な位置合わせを行うことができる。   For example, as shown in FIG. 4, the inner lead 3 and the electrode 6 are positioned using the first, second, third, and third films added to the insulating film 7 over the COF film 1 using one image recognition device 31. 4 by recognizing the images of the first, second, third and fourth side surfaces 18, 19, 20, 21 of the electrode 6 of the semiconductor chip 5 facing each other. Can be combined. Further, accurate positioning can be performed by fitting the first, second, third, and fourth side surfaces 18, 19, 20, and 21 into the first, second, third, and fourth portions 10, 11, 12, and 13. it can.

例えば、図３に示すように、位置合わせは、第１の辺１４に最も近い列の電極６の第１の辺１４を向く側面である第１の側面１８を、絶縁膜の開口端部９の第１の凸部２６に接触させて、第１の方向（図３においては下方向）の位置合わせを行う。第２の辺１５に最も近い電極６の第２の辺１５を向く側面である第２の側面１９を、絶縁膜の開口端部９の第２の凸部２７に接触させて、第２の方向（図３においては左方向）の位置合わせを行う。第３の辺１６に最も近い列の電極６の第３の辺１６を向く側面である第３の側面２０を、絶縁膜の開口端部９の第３の凸部２８に接触させて、第３の方向（図３においては上方向）の位置合わせを行う。第４の辺１７に最も近い電極６の第４の辺１７を向く側面である第４の側面２１を、絶縁膜の開口端部９の第４の凸部２９に接触させて、第４の方向（図３においては右方向）の位置合わせを行う。   For example, as shown in FIG. 3, the alignment is performed such that the first side surface 18 that faces the first side 14 of the electrode 6 in the column closest to the first side 14 is formed on the opening end 9 of the insulating film. The first convex portion 26 is brought into contact with the first convex portion 26 to perform alignment in the first direction (downward in FIG. 3). The second side surface 19, which is the side surface facing the second side 15 of the electrode 6 closest to the second side 15, is brought into contact with the second convex portion 27 of the opening end portion 9 of the insulating film, so that the second side Alignment in the direction (left direction in FIG. 3) is performed. The third side surface 20, which is the side surface facing the third side 16 of the electrode 6 in the row closest to the third side 16, is brought into contact with the third convex portion 28 of the opening end 9 of the insulating film, and 3 is aligned (upward in FIG. 3). The fourth side surface 21, which is the side surface facing the fourth side 17 of the electrode 6 closest to the fourth side 17, is brought into contact with the fourth convex portion 29 of the opening end 9 of the insulating film, so that the fourth side Alignment in the direction (right direction in FIG. 3) is performed.

位置決めした半導体チップ５及びＣＯＦ用フィルム１は、高加熱したボンディングステーションのステージとボンディングヘッド３２のツール熱荷重にて一括ボンディングが行われる。   The semiconductor chip 5 and the COF film 1 that have been positioned are collectively bonded by the tool heat load applied to the stage of the bonding station and the bonding head 32 that are heated to high temperatures.

図５は、本発明を適用した本実施の形態に係るＣＯＦ型半導体装置の製造方法を説明する図である。   FIG. 5 is a diagram for explaining a method of manufacturing a COF type semiconductor device according to the present embodiment to which the present invention is applied.

ＣＯＦ型半導体装置６０は、図１に示したＣＯＦ用フィルム１の打ち抜き部分３３を図５に示すように、打ち抜くことにより形成される。   The COF type semiconductor device 60 is formed by punching the punched portion 33 of the COF film 1 shown in FIG. 1 as shown in FIG.

本発明によれば、半導体チップ５上の電極６のパターンに対応して、絶縁膜７に第１，２，３及び４の部分１０，１１，１２，１３を設けているので、それぞれに対応した半導体チップ５上の電極６を嵌め込むことにより、インナーリード３と半導体チップ５の電極６との位置決めが容易にできる。これにより、インナーリード３と半導体チップ５の電極６との位置決め方法を簡略化し、実装精度の高いＣＯＦ型半導体装置の製造方法を提供することができる。   According to the present invention, the first, second, third, and fourth portions 10, 11, 12, and 13 are provided in the insulating film 7 in correspondence with the pattern of the electrode 6 on the semiconductor chip 5, and therefore correspond to each. By fitting the electrode 6 on the semiconductor chip 5, the inner lead 3 and the electrode 6 of the semiconductor chip 5 can be easily positioned. Thereby, the positioning method of the inner lead 3 and the electrode 6 of the semiconductor chip 5 can be simplified, and a method for manufacturing a COF type semiconductor device with high mounting accuracy can be provided.

以上により、ＣＯＦ用フィルム１に形成されたインナーリード３と半導体チップ５上の電極６との位置決めが間接的に行われる。第１，２，３及び４の部分１０，１１，１２，１３は、例えば電極６の配置パターンを用いる。第１，２，３及び４の部分１０，１１，１２，１３は、それぞれ一箇所でもいいし複数箇所でもよい。また、半導体チップ５の表面に形成された電極６のパターンに限らず、十字や四角形等の特徴あるパターンを別に設けてもよい。   As described above, the positioning of the inner lead 3 formed on the COF film 1 and the electrode 6 on the semiconductor chip 5 is performed indirectly. For the first, second, third, and fourth portions 10, 11, 12, and 13, for example, an arrangement pattern of the electrodes 6 is used. Each of the first, second, third and fourth portions 10, 11, 12, and 13 may be provided at one place or a plurality of places. In addition to the pattern of the electrodes 6 formed on the surface of the semiconductor chip 5, a characteristic pattern such as a cross or a rectangle may be provided separately.

（回路基板）
図６は、本発明を適用した実施の形態に係る回路基板を示す図である。図６に示すように、回路基板６１には、上述したＣＯＦ型半導体装置６０が電気的に接続されている。回路基板６１は、例えば液晶パネルであってもよい。ＣＯＦ型半導体装置６０は、ＣＯＦ用フィルム１を、半導体チップ５を囲む輪郭で打ち抜いた形状をなす。 (Circuit board)
FIG. 6 is a diagram showing a circuit board according to an embodiment to which the present invention is applied. As shown in FIG. 6, the above-described COF type semiconductor device 60 is electrically connected to the circuit board 61. The circuit board 61 may be a liquid crystal panel, for example. The COF type semiconductor device 60 has a shape obtained by punching the COF film 1 with a contour surrounding the semiconductor chip 5.

図６に示すように、ＣＯＦ型半導体装置６０のＣＯＦ用フィルム１は、屈曲させて設けてもよい。例えば、回路基板６１の端部の回りにＣＯＦ用フィルム１を屈曲させてもよい。   As shown in FIG. 6, the COF film 1 of the COF type semiconductor device 60 may be bent and provided. For example, the COF film 1 may be bent around the end of the circuit board 61.

（電子機器）
本発明を適用したＣＯＦ型半導体装置を有する電子機器として、図７には、携帯電話６２が示されている。この携帯電話６２は、本発明を適用した回路基板６１（液晶パネル）も有する。図８には、本発明を適用したＣＯＦ型半導体装置（図示せず）を有するノート型パーソナルコンピュータ６３が示されている。 (Electronics)
As an electronic apparatus having a COF type semiconductor device to which the present invention is applied, a mobile phone 62 is shown in FIG. The mobile phone 62 also has a circuit board 61 (liquid crystal panel) to which the present invention is applied. FIG. 8 shows a notebook personal computer 63 having a COF type semiconductor device (not shown) to which the present invention is applied.

（第２の実施の形態）
図９は、本発明を適用した第２の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。本実施の形態では、複数の第１の部分３６は、第１の辺１４に沿って並ぶ第１のグループの電極２２に対向するように位置している。複数の第２の部分３７は、第２の辺１５に沿って並ぶ第２のグループの電極２３に対向するように位置している。複数の第３の部分３８は、第３の辺１６に沿って並ぶ第３のグループの電極２４に対向するように位置している。複数の第４の部分３９は、第４の辺１７に沿って並ぶ第４のグループの電極２５に対向するように位置している。 (Second Embodiment)
FIG. 9 is an explanatory diagram of positioning of the insulating film on the film for COF and the bump on the semiconductor chip according to the second embodiment to which the present invention is applied. In the present embodiment, the plurality of first portions 36 are positioned so as to oppose the first group of electrodes 22 arranged along the first side 14. The plurality of second portions 37 are positioned so as to face the second group of electrodes 23 arranged along the second side 15. The plurality of third portions 38 are positioned so as to face the third group of electrodes 24 arranged along the third side 16. The plurality of fourth portions 39 are positioned so as to face the fourth group of electrodes 25 arranged along the fourth side 17.

位置合わせは、第１の辺１４に沿って並ぶ第１のグループの電極２２を、複数の第１の部分３６に対向するように配置する。第２の辺１５に沿って並ぶ第２のグループの電極２３を、複数の第２の部分３７に対向するように配置する。第３の辺１６に沿って並ぶ第３のグループの電極２４を、複数の第３の部分３８に対向するように配置する。第４の辺１７に沿って並ぶ第４のグループの電極２５を、複数の第４の部分３９に対向するように配置する。   In the alignment, the first group of electrodes 22 arranged along the first side 14 is disposed so as to face the plurality of first portions 36. A second group of electrodes 23 arranged along the second side 15 is disposed so as to face the plurality of second portions 37. A third group of electrodes 24 arranged along the third side 16 is disposed so as to face the plurality of third portions 38. A fourth group of electrodes 25 arranged along the fourth side 17 is disposed so as to face the plurality of fourth portions 39.

さらに、絶縁膜の開口端部４０の全体を、半導体チップとオーバーラップする領域内に配置する。その他の構成及び製造方法については、第１の実施の形態で説明した内容を適用することができる。   Further, the entire opening end 40 of the insulating film is disposed in a region overlapping with the semiconductor chip. The contents described in the first embodiment can be applied to other configurations and manufacturing methods.

（第３の実施の形態）
図１０は、本発明を適用した第３の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。本実施の形態では、絶縁膜の開口端部４１の全体が半導体チップ５とオーバーラップする領域内に位置している。 (Third embodiment)
FIG. 10 is an explanatory view of positioning of the insulating film on the COF film and the bump on the semiconductor chip according to the third embodiment to which the present invention is applied. In the present embodiment, the entire opening end 41 of the insulating film is located in a region overlapping with the semiconductor chip 5.

絶縁膜の開口端部４１は、第１の辺１４に最も近い列の電極６の第１の辺１４を向く第１の側面４２に隣接するように形成されている。また、それぞれの列において最も第２の辺１５に近いいずれかの電極６の第２の辺１５を向く第２の側面４３に隣接するように形成されている。また、第３の辺１６に最も近い列の電極６の第３の辺１６を向く第３の側面４４に隣接するように形成されている。さらに、それぞれの列において最も第４の辺１７に近いいずれかの電極６の第４の辺１７を向く第４の側面４５に隣接するように形成されている。   The opening end 41 of the insulating film is formed so as to be adjacent to the first side face 42 facing the first side 14 of the electrode 6 in the column closest to the first side 14. In addition, each column is formed so as to be adjacent to the second side face 43 facing the second side 15 of any one of the electrodes 6 closest to the second side 15. Further, it is formed so as to be adjacent to the third side face 44 facing the third side 16 of the electrode 6 in the row closest to the third side 16. Furthermore, it is formed so as to be adjacent to the fourth side face 45 facing the fourth side 17 of any one of the electrodes 6 closest to the fourth side 17 in each row.

位置合わせは、第１の辺１４に最も近い列の電極６の第１の辺１４を向く側面である第１の側面４２を、絶縁膜の開口端部４１に接触させて、第１の方向（図１０においては下方向）の位置合わせを行う。それぞれの列において最も第２の辺１５に近いいずれかの電極６の第２の辺１５を向く側面である第２の側面４３を、絶縁膜の開口端部４１に接触させて、第２の方向（図１０においては左方向）の位置合わせを行う。第３の辺１６に最も近い列の電極６の第３の辺１６を向く側面である第３の側面４４を、絶縁膜の開口端部４１接触させて、第３の方向（図１０においては上方向）の位置合わせを行う。それぞれの列において最も第４の辺１７に近いいずれかの電極６の第４の辺１７を向く側面である第４の側面４５を、絶縁膜の開口端部４１に接触させて、第４の方向（図１０においては右方向）の位置合わせを行う。その他の構成及び製造方法については、第１の実施の形態で説明した内容を適用することができる。   The alignment is performed by bringing the first side surface 42, which is the side surface facing the first side 14 of the electrode 6 in the column closest to the first side 14, into contact with the opening end 41 of the insulating film in the first direction. Alignment (downward in FIG. 10) is performed. In each row, the second side surface 43, which is the side surface facing the second side 15 of any one of the electrodes 6 closest to the second side 15, is brought into contact with the opening end 41 of the insulating film, thereby Alignment in the direction (left direction in FIG. 10) is performed. The third side surface 44, which is the side surface facing the third side 16 of the electrode 6 in the row closest to the third side 16, is brought into contact with the opening end 41 of the insulating film, so that the third direction (in FIG. 10, Align in the upward direction. In each row, the fourth side surface 45, which is the side surface facing the fourth side 17 of any one of the electrodes 6 closest to the fourth side 17, is brought into contact with the opening end 41 of the insulating film, so that the fourth side Alignment in the direction (right direction in FIG. 10) is performed. The contents described in the first embodiment can be applied to other configurations and manufacturing methods.

（第４の実施の形態）
図１１は、本発明を適用した第４の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。本実施の形態では、複数の電極６は、第１の辺１４に沿って間隔をあけて並ぶ１つのグループをなす第１の電極３４を含んでいる。また、第１の辺１４に沿って第１の電極３４よりも第１の辺１４から離れた位置で間隔をあけて並ぶ１つのグループをなす第２の電極３５を含んでいる。第１，２の電極３４，３５は、千鳥状に配置されている。絶縁膜の開口端部４６は、複数の凸部が間隔をあけて形成されてなる、くし形形状を含んでいる。くし形形状は、それぞれの凸部が隣同士の一対の第１の電極３４の間を通って、いずれかの第２の電極３５に隣接するように形成されている。位置合わせは、くし形形状を、それぞれの凸部が隣同士の一対の第１の電極３４の間を通って、いずれかの第２の電極３５に隣接するように配置する。その他の構成及び製造方法については、第１の実施の形態で説明した内容を適用することができる。 (Fourth embodiment)
FIG. 11 is an explanatory diagram of positioning of the insulating film on the COF film and the bump on the semiconductor chip according to the fourth embodiment to which the present invention is applied. In the present embodiment, the plurality of electrodes 6 include a first electrode 34 that forms one group arranged at intervals along the first side 14. In addition, a second electrode 35 is included that forms a group along the first side 14 at a position farther from the first side 14 than the first electrode 34. The first and second electrodes 34 and 35 are arranged in a staggered manner. The opening end 46 of the insulating film includes a comb shape in which a plurality of convex portions are formed at intervals. The comb shape is formed such that each convex portion passes between a pair of adjacent first electrodes 34 and is adjacent to one of the second electrodes 35. In the alignment, the comb shape is arranged so that each convex portion passes between a pair of adjacent first electrodes 34 and is adjacent to one of the second electrodes 35. The contents described in the first embodiment can be applied to other configurations and manufacturing methods.

（第５の実施の形態）
図１２は、本発明を適用した第５の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。本実施の形態では、絶縁膜の開口端部４７は、複数の凹凸部が形成されてなる、くし形形状を含んでいる。くし形形状は、第１の辺１４に沿って間隔をあけて並ぶ１つのグループの電極６の隣に、それぞれの凸部が隣同士の一対の電極６の間に配置され、それぞれの凹部内に、いずれかの電極６が隣接するように形成されている。位置合わせは、くし形形状を、第１の辺１４に沿って間隔をあけて並ぶ１つのグループの電極６の隣に、それぞれの凸部が隣同士の一対の電極６の間に配置する。さらに、それぞれの凹部内に、いずれかの電極６が隣接するように配置する。その他の構成及び製造方法については、第１の実施の形態で説明した内容を適用することができる。 (Fifth embodiment)
FIG. 12 is an explanatory view of positioning of the insulating film on the COF film and the bump on the semiconductor chip according to the fifth embodiment to which the present invention is applied. In the present embodiment, the opening end portion 47 of the insulating film includes a comb shape in which a plurality of uneven portions are formed. In the comb shape, each convex portion is arranged between a pair of adjacent electrodes 6 next to one group of electrodes 6 arranged at intervals along the first side 14, and the inside of each concave portion is Further, one of the electrodes 6 is formed so as to be adjacent to each other. In the alignment, a comb-shaped shape is arranged next to one group of electrodes 6 arranged at intervals along the first side 14, and each convex portion is arranged between a pair of adjacent electrodes 6. Furthermore, it arrange | positions so that either electrode 6 may adjoin in each recessed part. The contents described in the first embodiment can be applied to other configurations and manufacturing methods.

（第６の実施の形態）
図１３は、本発明を適用した第６の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。本実施の形態では、複数の電極６は、第１の辺１４に対して斜めに交差する直線に沿って配列される一対の電極６を含んでいる。 (Sixth embodiment)
FIG. 13 is an explanatory view of positioning of the insulating film on the COF film and the bump on the semiconductor chip according to the sixth embodiment to which the present invention is applied. In the present embodiment, the plurality of electrodes 6 include a pair of electrodes 6 arranged along a straight line that obliquely intersects the first side 14.

絶縁膜の開口端部４８は、半導体チップ５の角部から、一対の電極６の間の方向に突出する凸部を有している。位置合わせは、絶縁膜の開口端部４８を、半導体チップ５の角部から、一対の電極６の間の方向に突出する凸部になるように配置する。その他の構成及び製造方法については、第１の実施の形態で説明した内容を適用することができる。   The opening end 48 of the insulating film has a protrusion that protrudes from the corner of the semiconductor chip 5 in the direction between the pair of electrodes 6. In the alignment, the opening end 48 of the insulating film is arranged so as to be a convex portion protruding from the corner of the semiconductor chip 5 in the direction between the pair of electrodes 6. The contents described in the first embodiment can be applied to other configurations and manufacturing methods.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。   The present invention is not limited to the above-described embodiments, and various modifications can be made.

例えば、図１４に示すように、第１，２の電極３４，３５は、千鳥状に配置されている。絶縁膜の開口端部４９は、複数の凸部５０が間隔をあけて形成されている、くし形形状を含んでいる。くし形形状は、それぞれの凸部５０が隣同士の一対の第１の電極３４の間を通って、いずれかの第２の電極３５に隣接するように形成されている。凸部５０は、先端に向かうに従って幅が大きくなるように形成されてもよい。すなわち、凸部５０は、突出方向において、先端側の部分の幅Ａが、基部側の部分の幅Ｂよりも大きくなるように形成されていてもよい。   For example, as shown in FIG. 14, the first and second electrodes 34 and 35 are arranged in a staggered manner. The opening end 49 of the insulating film includes a comb shape in which a plurality of convex portions 50 are formed at intervals. The comb shape is formed such that each convex portion 50 passes between a pair of adjacent first electrodes 34 and is adjacent to one of the second electrodes 35. The convex part 50 may be formed so that a width | variety becomes large as it goes to a front-end | tip. That is, the convex portion 50 may be formed such that the width A of the tip side portion is larger than the width B of the base side portion in the protruding direction.

また、図１５に示すように、第１，２の電極３４，３５は、千鳥状に配置されている。絶縁膜の開口端部５１は、複数の凸部５２が間隔をあけて形成されている、くし形形状を含んでいる。くし形形状は、それぞれの凸部５２が隣同士の一対の第１の電極３４の間を通って、いずれかの第２の電極３５に隣接するように形成されている。凸部５２は、先端に向かうに従って幅が小さくなるように形成されてもよい。すなわち、凸部５２は、突出方向において、先端側の部分の幅Ａが、基部側の部分の幅Ｂよりも小さくなるように形成されていてもよい。   Further, as shown in FIG. 15, the first and second electrodes 34 and 35 are arranged in a staggered manner. The opening end portion 51 of the insulating film includes a comb shape in which a plurality of convex portions 52 are formed at intervals. The comb shape is formed such that each convex portion 52 passes between a pair of adjacent first electrodes 34 and is adjacent to one of the second electrodes 35. The convex part 52 may be formed so that a width | variety becomes small as it goes to a front-end | tip. That is, the convex portion 52 may be formed so that the width A of the tip side portion is smaller than the width B of the base side portion in the protruding direction.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。さらに、本発明は、実施の形態で説明した技術的事項のいずれかを限定的に除外した内容を含む。あるいは、本発明は、上述した実施の形態から公知技術を限定的に除外した内容を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

第１の実施の形態に係るＣＯＦ用フィルムの平面図である。It is a top view of the film for COF which concerns on 1st Embodiment. 第１の実施の形態に係るＣＯＦ型半導体装置の断面図である。1 is a cross-sectional view of a COF type semiconductor device according to a first embodiment. 第１の実施の形態に係る図２のIII−III線断面図である。It is the III-III sectional view taken on the line of FIG. 2 which concerns on 1st Embodiment. 第１の実施の形態に係るＣＯＦ用フィルム上のインナーリードと半導体チップ上のバンプのボンディング部分の説明図である。It is explanatory drawing of the bonding part of the inner lead on the film for COF which concerns on 1st Embodiment, and the bump on a semiconductor chip. 第１の実施の形態に係るＣＯＦ型半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the COF type semiconductor device which concerns on 1st Embodiment. 第１の実施の形態に係る回路基板を示す図である。It is a figure which shows the circuit board which concerns on 1st Embodiment. 第１の実施の形態に係るＣＯＦ型半導体装置を有する電子機器を示す図である。It is a figure which shows the electronic device which has the COF type semiconductor device which concerns on 1st Embodiment. 第１の実施の形態に係るＣＯＦ型半導体装置を有する電子機器を示す図である。It is a figure which shows the electronic device which has the COF type semiconductor device which concerns on 1st Embodiment. 第２の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。It is explanatory drawing of positioning with the insulating film on the film for COF which concerns on 2nd Embodiment, and the bump on a semiconductor chip. 第３の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。It is explanatory drawing of positioning with the insulating film on the film for COF which concerns on 3rd Embodiment, and the bump on a semiconductor chip. 第４の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。It is explanatory drawing of positioning with the insulating film on the film for COF which concerns on 4th Embodiment, and the bump on a semiconductor chip. 第５の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。It is explanatory drawing of positioning with the insulating film on the film for COF which concerns on 5th Embodiment, and the bump on a semiconductor chip. 第６の実施の形態に係るＣＯＦ用フィルム上の絶縁膜と半導体チップ上のバンプとの位置決めの説明図である。It is explanatory drawing of positioning with the insulating film on the film for COF which concerns on 6th Embodiment, and the bump on a semiconductor chip. 本実施の形態の変形例を示す図である。It is a figure which shows the modification of this Embodiment. 本実施の形態の変形例を示す図である。It is a figure which shows the modification of this Embodiment.

符号の説明Explanation of symbols

１…ＣＯＦ用フィルム（基板） ２…配線パターン ３…インナーリード(リード) ４…アウターリード(リード) ５…半導体チップ ６…電極（バンプ） ７…絶縁膜（ソルダーレジスト） ８…絶縁膜の開口 ９…絶縁膜の開口端部 １０…第１の部分 １１…第２の部分 １２…第３の部分 １３…第４の部分 １４…第１の辺 １５…第２の辺 １６…第３の辺 １７…第４の辺 １８…第１の側面 １９…第２の側面 ２０…第３の側面 ２１…第４の側面 ２２…第1のグループの電極 ２３…第２のグループの電極 ２４…第３のグループの電極 ２５…第４のグループの電極 ２６…第１の凸部 ２７…第２の凸部 ２８…第３の凸部 ２９…第４の凸部 ３０…封止部 ３１…画像認識装置 ３２…ボンディングヘッド ３３…打ち抜き部分 ３４…第１の電極 ３５…第２の電極 ３６…第１の部分 ３７…第２の部分 ３８…第３の部分 ３９…第４の部分 ４０…絶縁膜の開口端部 ４１…絶縁膜の開口端部 ４２…第１の側面 ４３…第２の側面 ４４…第３の側面 ４５…第４の側面 ４６…絶縁膜の開口端部 ４７…絶縁膜の開口端部 ４８…絶縁膜の開口端部 ４９…絶縁膜の開口端部 ５０…凸部 ５１…絶縁膜の開口端部 ５２…凸部 ６０…ＣＯＦ型半導体装置 ６１…回路基板 ６２…携帯電話 ６３…ノート型パーソナルコンピュータ DESCRIPTION OF SYMBOLS 1 ... COF film (board | substrate) 2 ... Wiring pattern 3 ... Inner lead (lead) 4 ... Outer lead (lead) 5 ... Semiconductor chip 6 ... Electrode (bump) 7 ... Insulating film (solder resist) 8 ... Opening of insulating film DESCRIPTION OF SYMBOLS 9 ... Opening edge part of insulating film 10 ... 1st part 11 ... 2nd part 12 ... 3rd part 13 ... 4th part 14 ... 1st edge | side 15 ... 2nd edge | side 16 ... 3rd edge | side 17 ... 4th side 18 ... 1st side surface 19 ... 2nd side surface 20 ... 3rd side surface 21 ... 4th side surface 22 ... 1st group electrode 23 ... 2nd group electrode 24 ... 3rd Group electrode 25 ... fourth group electrode 26 ... first convex portion 27 ... second convex portion 28 ... third convex portion 29 ... fourth convex portion 30 ... sealing portion 31 ... image recognition device 32 ... Bonding head 33 ... Punched part 34 1st electrode 35 ... 2nd electrode 36 ... 1st part 37 ... 2nd part 38 ... 3rd part 39 ... 4th part 40 ... Opening edge part of insulating film 41 ... Opening edge part of insulating film DESCRIPTION OF SYMBOLS 42 ... 1st side surface 43 ... 2nd side surface 44 ... 3rd side surface 45 ... 4th side surface 46 ... Opening edge part of insulating film 47 ... Opening edge part of insulating film 48 ... Opening edge part of insulating film 49 ... Open end of insulating film 50... Projection 51. Open end of insulating film 52. Convex 60. COF type semiconductor device 61. Circuit board 62. Mobile phone 63.

Claims (22)

複数のリードが形成されてなる基板と、
開口を有し、前記開口内にそれぞれの前記リードの一部が配置されるように前記リードを覆う絶縁膜と、
複数の電極を有し、前記基板に搭載され、前記開口内で前記複数の電極と前記リードが対向して電気的に接続されてなる半導体チップと、
を有し、
前記絶縁膜の前記開口端部は、前記半導体チップとオーバーラップする領域内に位置する第１及び第２の部分を含み、
前記第１の部分は、いずれかの前記電極の第１の方向を向く第１の側面に対向するように位置し、
前記第２の部分は、いずれかの前記電極の前記第１の方向に交差する第２の方向を向く第２の側面に対向するように位置してなる半導体装置。 A substrate on which a plurality of leads are formed;
An insulating film having an opening and covering the leads so that a part of each of the leads is disposed in the opening;
A semiconductor chip having a plurality of electrodes, mounted on the substrate, and in which the plurality of electrodes and the leads are electrically connected to face each other;
Have
The opening end of the insulating film includes first and second portions located in a region overlapping with the semiconductor chip,
The first portion is located so as to face the first side face of the electrode in the first direction,
The semiconductor device, wherein the second portion is positioned so as to face a second side surface of any one of the electrodes facing a second direction intersecting the first direction. 請求項１記載の半導体装置において、
前記絶縁膜の前記開口端部は、前記半導体チップとオーバーラップする領域内に位置する第３及び第４の部分をさらに含み、
前記第３の部分は、いずれかの前記電極の前記第１の方向とは反対の第３の方向を向く第３の側面に対向するように位置し、
前記第４の部分は、いずれかの前記電極の前記第２の方向とは反対の第４の方向を向く第４の側面に対向するように位置する半導体装置。 The semiconductor device according to claim 1,
The opening end of the insulating film further includes third and fourth portions located in a region overlapping with the semiconductor chip,
The third portion is located so as to face a third side surface facing a third direction opposite to the first direction of any one of the electrodes,
The semiconductor device, wherein the fourth portion is positioned so as to face a fourth side surface of any one of the electrodes facing a fourth direction opposite to the second direction. 請求項２記載の半導体装置において、
前記複数の電極は、前記半導体チップの第１，２，３及び４の辺を含む矩形の面に設けられ、
前記第１の辺と前記第３の辺とは、向き合うように位置し、
前記第２の辺と前記第４の辺とは、向き合うように位置してなる半導体装置。 The semiconductor device according to claim 2,
The plurality of electrodes are provided on a rectangular surface including the first, second, third and fourth sides of the semiconductor chip,
The first side and the third side are positioned to face each other,
The semiconductor device, wherein the second side and the fourth side are positioned so as to face each other. 請求項３記載の半導体装置において、
前記第１，２，３及び４の部分は、それぞれ複数設けられ、
前記複数の第１の部分は、前記第１の辺に沿って並ぶ第１のグループの電極に対向するように位置し、
前記複数の第２の部分は、前記第２の辺に沿って並ぶ第２のグループの電極に対向するように位置し、
前記複数の第３の部分は、前記第３の辺に沿って並ぶ第３のグループの電極に対向するように位置し、
前記複数の第４の部分は、前記第４の辺に沿って並ぶ第４のグループの電極に対向するように位置してなる半導体装置。 The semiconductor device according to claim 3.
A plurality of the first, second, third and fourth portions are provided,
The plurality of first portions are positioned to face a first group of electrodes arranged along the first side,
The plurality of second portions are positioned to face a second group of electrodes arranged along the second side,
The plurality of third portions are located to face a third group of electrodes arranged along the third side,
The semiconductor device, wherein the plurality of fourth portions are positioned so as to face a fourth group of electrodes arranged along the fourth side. 請求項４記載の半導体装置において、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記絶縁膜の前記開口端部は、
前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面に隣接する第１の凸部と、
前記第２の辺に最も近い前記電極の前記第２の辺を向く側面である前記第２の側面に隣接する第２の凸部と、
前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面に隣接する第３の凸部と、
前記第４の辺に最も近い前記電極の前記第４の辺を向く側面である前記第４の側面に隣接する第４の凸部とを含む半導体装置。 The semiconductor device according to claim 4.
The plurality of electrodes are arranged in a plurality of rows along the first side,
The opening end of the insulating film is
A first convex portion adjacent to the first side surface that is a side surface facing the first side of the electrodes in the row closest to the first side;
A second convex portion adjacent to the second side surface, which is a side surface facing the second side of the electrode closest to the second side;
A third protrusion adjacent to the third side surface, which is a side surface facing the third side of the electrodes in the row closest to the third side;
A semiconductor device comprising: a fourth convex portion adjacent to the fourth side surface, which is a side surface facing the fourth side of the electrode closest to the fourth side. 請求項４記載の半導体装置において、
前記開口端部の全体が前記半導体チップとオーバーラップする領域内に位置してなる半導体装置。 The semiconductor device according to claim 4.
A semiconductor device in which the entire opening end is located in a region overlapping with the semiconductor chip. 請求項４記載の半導体装置において、
前記開口端部の全体が前記半導体チップとオーバーラップする領域内に位置し、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記絶縁膜の前記開口端部は、
前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面と、
それぞれの列において最も前記第２の辺に近いいずれかの前記電極の前記第２の辺を向く側面である前記第２の側面と、
前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面と、
それぞれの列において最も前記第４の辺に近いいずれかの前記電極の前記第４の辺を向く側面である第４の側面とに隣接するように形成されてなる半導体装置。 The semiconductor device according to claim 4.
The entire opening end is located in a region overlapping with the semiconductor chip,
The plurality of electrodes are arranged in a plurality of rows along the first side,
The opening end of the insulating film is
The first side that is the side facing the first side of the electrodes in the row closest to the first side;
The second side surface which is a side surface facing the second side of any one of the electrodes closest to the second side in each row;
The third side surface which is the side surface facing the third side of the electrodes in the row closest to the third side;
A semiconductor device formed so as to be adjacent to a fourth side surface which is a side surface facing the fourth side of any one of the electrodes closest to the fourth side in each row. 請求項３記載の半導体装置において、
前記複数の電極は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループをなす第１の電極と、前記第１の辺に沿って前記第１の電極よりも前記第１の辺から離れた位置で間隔をあけて並ぶ１つのグループをなす第２の電極と、
を含み、
前記第１及び第２の電極は、千鳥状に配置されてなり、
前記絶縁膜の前記開口端部は、複数の凸部が間隔をあけて形成されてなる、くし形形状を含み、
前記くし形形状は、それぞれの前記凸部が隣同士の一対の前記第１の電極の間を通って、いずれかの前記第２の電極に隣接するように形成されてなる半導体装置。 The semiconductor device according to claim 3.
The plurality of electrodes include a first electrode forming a group arranged at intervals along the first side, and the first side along the first side than the first electrode. A second electrode forming a group lined up at a distance away from each other;
Including
The first and second electrodes are arranged in a staggered manner,
The opening end portion of the insulating film includes a comb shape, in which a plurality of convex portions are formed at intervals.
The comb-shaped shape is a semiconductor device in which each of the convex portions passes between a pair of adjacent first electrodes and is adjacent to any one of the second electrodes. 請求項３記載の半導体装置において、
前記絶縁膜の前記開口端部は、複数の凹凸部が形成されてなる、くし形形状を含み、
前記くし形形状は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループの電極の隣に、それぞれの前記凸部が隣同士の一対の前記電極の間に配置され、それぞれの前記凹部内に、いずれかの前記電極が隣接するように形成されてなる半導体装置。 The semiconductor device according to claim 3.
The opening end portion of the insulating film includes a comb shape formed with a plurality of uneven portions,
The comb-shaped shape is arranged next to one group of electrodes arranged at intervals along the first side, and each of the convex portions is arranged between a pair of adjacent electrodes, A semiconductor device in which any one of the electrodes is formed adjacent to a recess. 請求項３記載の半導体装置において、
前記複数の電極は、前記第１の辺に対して斜めに交差する直線に沿って配列される一対の電極を含み、
前記絶縁膜の前記開口端部は、前記半導体チップの角部から、前記一対の電極の間の方向に突出する凸部を有する半導体装置。 The semiconductor device according to claim 3.
The plurality of electrodes include a pair of electrodes arranged along a straight line that obliquely intersects the first side,
The semiconductor device according to claim 1, wherein the opening end portion of the insulating film has a convex portion protruding in a direction between the pair of electrodes from a corner portion of the semiconductor chip. 請求項１から請求項１０のいずれかに記載の半導体装置が電気的に接続された回路基板。   A circuit board to which the semiconductor device according to claim 1 is electrically connected. 請求項１から請求項１０のいずれかに記載の半導体装置を有する電子機器。   An electronic apparatus comprising the semiconductor device according to claim 1. 半導体チップの複数の電極と、基板に形成された複数のリードと、を対向するように位置合わせすること、及び、
前記電極と前記リードを電気的に接続することを含み、
前記リードは、開口を有する絶縁膜によって、前記開口内にそれぞれの前記リードの一部が配置されるように覆われ、
前記絶縁膜の前記開口端部は、第１及び第２の部分を含み、
前記位置合わせは、
いずれかの前記電極の第１の方向を向く第１の側面を、前記第１の部分に接触させて、前記第１の方向及びその反対方向の位置合わせを行うこと、及び、
いずれかの前記電極の前記第１の方向に交差する第２の方向を向く第２の側面を、前記第２の部分に接触させて、前記第２の方向及びその反対方向の位置合わせを行うことを含む半導体装置の製造方法。 Aligning the plurality of electrodes of the semiconductor chip and the plurality of leads formed on the substrate so as to face each other; and
Electrically connecting the electrode and the lead;
The leads are covered with an insulating film having an opening so that a part of each of the leads is disposed in the opening,
The opening end of the insulating film includes first and second portions;
The alignment is
A first side surface of any one of the electrodes facing the first direction is brought into contact with the first portion to perform alignment in the first direction and the opposite direction; and
A second side surface of any one of the electrodes facing a second direction intersecting the first direction is brought into contact with the second portion to perform alignment in the second direction and the opposite direction. A method of manufacturing a semiconductor device. 請求項１３記載の半導体装置の製造方法において、
前記絶縁膜の前記開口端部は、第３及び第４の部分をさらに含み、
前記位置合わせは、
いずれかの前記電極の前記第１の方向とは反対の第３の方向を向く第３の側面を、前記第３の部分に接触させて、前記第３の方向の位置合わせを行うこと、及び、
いずれかの前記電極の前記第２の方向とは反対の第４の方向を向く第４の側面を、前記第４の部分に接触させて、前記第４の方向の位置合わせを行うことを含む半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 13,
The opening end of the insulating film further includes third and fourth portions,
The alignment is
Aligning the third direction by bringing a third side surface of any one of the electrodes facing a third direction opposite to the first direction into contact with the third portion; and ,
Including aligning the fourth direction by bringing a fourth side surface of any one of the electrodes facing a fourth direction opposite to the second direction into contact with the fourth portion. A method for manufacturing a semiconductor device. 請求項１４記載の半導体装置の製造方法において、
前記複数の電極は、前記半導体チップの第１，２，３及び４の辺を含む矩形の面に設けられ、
前記第１の辺と前記第３の辺とは、向き合うように位置し、
前記第２の辺と前記第４の辺とは、向き合うように位置してなる半導体装置の製造方法。 15. The method of manufacturing a semiconductor device according to claim 14,
The plurality of electrodes are provided on a rectangular surface including the first, second, third and fourth sides of the semiconductor chip,
The first side and the third side are positioned to face each other,
The method for manufacturing a semiconductor device, wherein the second side and the fourth side are positioned so as to face each other. 請求項１５記載の半導体装置の製造方法において、
前記第１，２，３及び４の部分は、それぞれ複数設けられ、
前記位置合わせで、
前記第１の辺に沿って並ぶ第１のグループの電極を、前記複数の第１の部分に対向するように配置し、
前記第２の辺に沿って並ぶ第２のグループの電極を、前記複数の第２の部分に対向するように配置し、
前記第３の辺に沿って並ぶ第３のグループの電極を、前記複数の第３の部分に対向するように配置し、
前記第４の辺に沿って並ぶ第４のグループの電極を、前記複数の第４の部分に対向するように配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 15,
A plurality of the first, second, third and fourth portions are provided,
In the alignment,
Arranging a first group of electrodes arranged along the first side so as to face the plurality of first portions;
Arranging a second group of electrodes arranged along the second side so as to face the plurality of second portions;
Arranging a third group of electrodes arranged along the third side so as to face the plurality of third portions;
A method of manufacturing a semiconductor device, wherein a fourth group of electrodes arranged along the fourth side is arranged to face the plurality of fourth portions. 請求項１６記載の半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記位置合わせは、
前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面を、前記絶縁膜の前記開口端部の第１の凸部に接触させて、前記第1の方向の位置合わせを行うこと、
前記第２の辺に最も近い前記電極の前記第２の辺を向く側面である前記第２の側面を、前記絶縁膜の前記開口端部の第２の凸部に接触させて、前記第２の方向の位置合わせを行うこと、
前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面を、前記絶縁膜の前記開口端部の第３の凸部に接触させて、前記第３の方向の位置合わせを行うこと、及び、
前記第４の辺に最も近い前記電極の前記第４の辺を向く側面である前記第４の側面を、前記絶縁膜の前記開口端部の第４の凸部に接触させて、前記第４の方向の位置合わせを行うことを含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
The plurality of electrodes are arranged in a plurality of rows along the first side,
The alignment is
The first side surface, which is the side surface facing the first side of the electrode in the row closest to the first side, is brought into contact with the first convex portion of the opening end of the insulating film, and Performing alignment in the first direction,
The second side surface, which is the side surface facing the second side of the electrode closest to the second side, is brought into contact with the second convex portion of the opening end portion of the insulating film, so that the second Align the direction of
The third side surface, which is the side surface facing the third side of the electrode in the row closest to the third side, is brought into contact with the third convex portion of the opening end of the insulating film, and Performing alignment in a third direction; and
The fourth side surface, which is the side surface facing the fourth side of the electrode closest to the fourth side, is brought into contact with the fourth convex portion of the opening end portion of the insulating film, so that the fourth A method for manufacturing a semiconductor device, comprising performing alignment in the direction of the semiconductor device. 請求項１６記載の半導体装置の製造方法において、
前記位置合わせで、
前記開口端部の全体を、前記半導体チップとオーバーラップする領域内に配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
In the alignment,
A method of manufacturing a semiconductor device, wherein the entire opening end is disposed in a region overlapping with the semiconductor chip. 請求項１６記載の半導体装置の製造方法において、
前記開口端部は、全体が前記半導体チップとオーバーラップするように形成され、
前記複数の電極は、前記第１の辺に沿って複数列をなすように配列されてなり、
前記位置合わせは、
前記第１の辺に最も近い列の前記電極の前記第１の辺を向く側面である前記第１の側面を、前記絶縁膜の前記開口端部に接触させて、前記第１の方向の位置合わせを行うこと、
それぞれの列において最も前記第２の辺に近いいずれかの前記電極の前記第２の辺を向く側面である前記第２の側面を、前記絶縁膜の前記開口端部に接触させて、前記第２の方向の位置合わせを行うこと、
前記第３の辺に最も近い列の前記電極の前記第３の辺を向く側面である前記第３の側面を、前記絶縁膜の前記開口端部に接触させて、前記第３の方向の位置合わせを行うこと、
それぞれの列において最も前記第４の辺に近いいずれかの前記電極の前記第４の辺を向く側面である第４の側面を、前記絶縁膜の前記開口端部に接触させて、前記第４の方向の位置合わせを行うことを含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 16,
The opening end is formed so as to overlap the semiconductor chip as a whole,
The plurality of electrodes are arranged in a plurality of rows along the first side,
The alignment is
The first side surface, which is the side surface facing the first side of the electrode in the row closest to the first side, is brought into contact with the opening end of the insulating film, and the position in the first direction Do the matching,
The second side surface, which is a side surface facing the second side of any one of the electrodes closest to the second side in each row, is brought into contact with the opening end of the insulating film, so that the first side Align the two directions,
The third side surface, which is the side surface facing the third side of the electrode in the row closest to the third side, is brought into contact with the opening end portion of the insulating film, so that the position in the third direction is reached. Do the matching,
A fourth side surface, which is a side surface facing the fourth side of any one of the electrodes closest to the fourth side in each row, is brought into contact with the opening end of the insulating film, so that the fourth A method for manufacturing a semiconductor device, comprising performing alignment in the direction of the semiconductor device. 請求項１５記載の半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に沿って間隔をあけて並ぶ１つのグループをなす第１の電極と、前記第１の辺に沿って前記第１の電極よりも前記第１の辺から離れた位置で間隔をあけて並ぶ１つのグループをなす第２の電極と、を含み、
前記第１及び第２の電極は、千鳥状に配置されてなり、
前記絶縁膜の前記開口端部は、複数の凸部が間隔をあけて形成されてなる、くし形形状を含み、
前記位置合わせで、
前記くし形形状を、それぞれの前記凸部が隣同士の一対の前記第１の電極の間を通って、いずれかの前記第２の電極に隣接するように配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 15,
The plurality of electrodes includes a first electrode forming a group arranged at intervals along the first side, and the first side along the first side than the first electrode. A second electrode that forms a group that is spaced apart at a distance from each other, and
The first and second electrodes are arranged in a staggered manner,
The opening end portion of the insulating film includes a comb shape, in which a plurality of convex portions are formed at intervals.
In the alignment,
A method of manufacturing a semiconductor device, wherein the comb shape is arranged so that each of the convex portions passes between a pair of adjacent first electrodes and is adjacent to any one of the second electrodes. 請求項１５記載の半導体装置の製造方法において、
前記絶縁膜の前記開口端部は、複数の凹凸部が形成されてなる、くし形形状を含み、
前記位置合わせで、
前記くし形形状を、前記第１の辺に沿って間隔をあけて並ぶ１つのグループの電極の隣に、それぞれの前記凸部が隣同士の一対の前記電極の間に配置し、それぞれの前記凹部内に、いずれかの前記電極が隣接するように配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 15,
The opening end portion of the insulating film includes a comb shape formed with a plurality of uneven portions,
In the alignment,
The comb-shaped shape is arranged next to one group of electrodes arranged at intervals along the first side, and each of the convex portions is arranged between a pair of adjacent electrodes, A method of manufacturing a semiconductor device, wherein one of the electrodes is disposed adjacent to a recess. 請求項１５記載の半導体装置の製造方法において、
前記複数の電極は、前記第１の辺に対して斜めに交差する直線に沿って配列される一対の電極を含み、
前記位置合わせで、
前記絶縁膜の前記開口端部を、前記半導体チップの角部から、前記一対の電極の間の方向に突出する凸部になるように配置する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 15,
The plurality of electrodes include a pair of electrodes arranged along a straight line that obliquely intersects the first side,
In the alignment,
A method of manufacturing a semiconductor device, wherein the opening end portion of the insulating film is arranged to be a convex portion protruding from a corner portion of the semiconductor chip in a direction between the pair of electrodes.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900229B1 (en) 2006-12-01 2009-06-02 주식회사 하이닉스반도체 Fine-pitch ball grid array package
JP2014229664A (en) * 2013-05-20 2014-12-08 オリンパス株式会社 Semiconductor device and method and device for positioning semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900229B1 (en) 2006-12-01 2009-06-02 주식회사 하이닉스반도체 Fine-pitch ball grid array package
JP2014229664A (en) * 2013-05-20 2014-12-08 オリンパス株式会社 Semiconductor device and method and device for positioning semiconductor device
US10446501B2 (en) 2013-05-20 2019-10-15 Olympus Corporation Semiconductor device, method of positioning semiconductor device, and positioning apparatus for semiconductor device

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