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JP2005183925A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005183925A
JP2005183925A JP2004227884A JP2004227884A JP2005183925A JP 2005183925 A JP2005183925 A JP 2005183925A JP 2004227884 A JP2004227884 A JP 2004227884A JP 2004227884 A JP2004227884 A JP 2004227884A JP 2005183925 A JP2005183925 A JP 2005183925A
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semiconductor device
substrate
semiconductor
terminal
region
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JP4681260B2 (en
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Hitoshi Kawaguchi
均 川口
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Sumitomo Bakelite Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where a semiconductor element and passive element can be efficiently mounted and to provide its manufacturing method. <P>SOLUTION: The semiconductor device is equipped with an output terminal 3 electrically connected to an external line of a multipurpose connector, a circuit element which is electrically connected to the output terminal 3 and includes semiconductor elements 5 having predetermined function and passive components 2, and a printed wiring board 1 having a terminal area with the output terminal 3 located. The semiconductors elements 5 and the passive components 2 are mounted on an area located on the back of the terminal area of the printed wiring board 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体チップと受動部品をひとつのパッケージに搭載した半導体装置に関するものであり、特に、小型・軽量化及び高機能・大容量化を目的とする半導体チップの実装技術に係わるものである。   The present invention relates to a semiconductor device in which a semiconductor chip and a passive component are mounted in one package, and more particularly to a semiconductor chip mounting technique for the purpose of miniaturization, weight reduction, high functionality, and large capacity. .

近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、また、半導体パッケージを含めた電子部品を実装する、実装用基板も小型化してきている。さらには電子機器への収納性を高めるため、３次元積層技術も使われるようになってきている。   With recent demands for higher functionality and lighter, thinner and smaller electronic devices, electronic components have been increasingly integrated and densely packaged. Semiconductor packages used in these electronic devices have been reduced in size and increased in pin count, and mounting substrates on which electronic components including the semiconductor package are mounted have also been reduced in size. Furthermore, a three-dimensional stacking technique is also being used in order to improve the storage property in electronic equipment.

半導体パッケージはその小型化に伴って、従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきているため、最近では回路基板上にチップを実装したものとして、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）や、ＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）と言った、エリア実装型の新しいパッケージ方式が提案されている。   With the miniaturization of semiconductor packages, the conventional package using a lead frame has a limit on miniaturization. Therefore, recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid) is used. Array) and a new area mounting type package system such as CSP (Chip Scale Package) have been proposed.

これらの半導体パッケージにおいて、半導体チップの電極と従来型半導体パッケージのリードフレームの機能を有する、半導体パッケージ用基板と呼ばれる、プラスチックやセラミックス等各種材料を使って構成される、サブストレートの端子との電気的接続方法として、ワイヤーボンディング方式やＴＡＢ（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）方式、さらにはＦＣ（Ｆｒｉｐ Ｃｈｉｐ）方式などが知られているが、最近では、半導体パッケージの小型化に有利なＦＣ接続方式を用いた、ＢＧＡやＣＳＰの構造が盛んに提案されている。
特開２０００−１２７６９号公報 特開平８−１６２６０８号公報 In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate, which is made of various materials such as plastics and ceramics, called the semiconductor package substrate, has the function of the lead frame of the conventional semiconductor package. As a general connection method, a wire bonding method, a TAB (Tape Automated Bonding) method, an FC (Flip Chip) method, and the like are known. BGA and CSP structures have been actively proposed.
JP 2000-12769 A JP-A-8-162608

しかしながら、上記工法では半導体パッケージ内部の半導体素子の周辺に受動素子を配置する方法（特許文献１）や半導体素子上に受動素子を形成する方法（特許文献２）が提案されているが、搭載できる素子の小型化や受動素子数に限界あるという問題を抱えている。   However, in the above method, a method of arranging passive elements around the semiconductor elements inside the semiconductor package (Patent Document 1) and a method of forming passive elements on the semiconductor elements (Patent Document 2) are proposed, but can be mounted. There is a problem that there is a limit to the miniaturization of elements and the number of passive elements.

さらに、半導体素子及び受動素子が搭載された従来の半導体パッケージは、何らかの手法で外部との電気的接触のために端子群を備えているが、そのエリアには半導体素子及び受動素子の実装はされておらず、端子群のエリアが電子機器の更なる小型化のためには大きな制約となっていた。   Furthermore, a conventional semiconductor package on which a semiconductor element and a passive element are mounted has a terminal group for electrical contact with the outside by some method, but the semiconductor element and the passive element are mounted in the area. However, the area of the terminal group has been a major limitation for further downsizing of electronic devices.

特に、汎用のコネクタの外部ラインに電気的に接続する端子を有する半導体装置にあっては、汎用のコネクタとの嵌合部は、コネクタとの接続の機能のみに使用され、その機械的強度については考慮されていたが、嵌合部の空き領域に半導体素子を含む回路素子を搭載するという発想はなかった。   In particular, in a semiconductor device having a terminal that is electrically connected to an external line of a general-purpose connector, the fitting portion with the general-purpose connector is used only for the function of connection with the connector, and its mechanical strength However, there was no idea of mounting a circuit element including a semiconductor element in the empty area of the fitting portion.

本発明は、従来のこのような問題点を解決するためになされたもので、その目的とするところは、半導体パッケージの容積を抑えたまま半導体素子及び受動素子を多数内蔵した半導体パッケージを効率よく製造する方法を提供することにある。   The present invention has been made in order to solve the above-described conventional problems, and an object of the present invention is to efficiently provide a semiconductor package containing a large number of semiconductor elements and passive elements while suppressing the volume of the semiconductor package. It is to provide a method of manufacturing.

発明者らは種々検討の結果、外部に接続される端子部と半導体素子及び受動部品が搭載される回路部を統合する回路設計により、外部との接続を目的とする端子が配設された基板エリアの裏面部に半導体素子及び受動部品を搭載できる技術を発明し、その製品の動作と接続端子の二つの機能を兼ね備える半導体装置を発明した。   As a result of various investigations, the inventors have designed a circuit in which a terminal portion connected to the outside and a circuit portion on which a semiconductor element and passive components are mounted, and a substrate on which terminals intended for connection to the outside are arranged. Invented a technology capable of mounting semiconductor elements and passive components on the back surface of the area, and invented a semiconductor device having both functions of the product and connection terminals.

本発明によれば、汎用のコネクタの外部ラインに電気的に接続する端子と、前記端子に電気的に接続され、所定の機能を有する回路素子と、前記端子が配設された端子領域を有する基板と、を備え、前記基板の前記端子領域の裏側に位置する領域に前記回路素子が搭載されることを特徴とする半導体装置が提供される。   According to the present invention, a terminal electrically connected to an external line of a general-purpose connector, a circuit element electrically connected to the terminal and having a predetermined function, and a terminal region in which the terminal is disposed And a substrate, wherein the circuit element is mounted in a region located on the back side of the terminal region of the substrate.

ここで、回路素子は、半導体素子および受動素子を含む。受動素子は、供給された電力を消費、蓄積、放出し、増幅、整流などの能動動作を行わない素子であり、たとえば、抵抗、インダクタンス、コンデンサなどを含む。この半導体装置の基板の一面には端子が配設され、汎用のコネクタの外部ラインと電気的に接続可能な構成を有する。   Here, the circuit element includes a semiconductor element and a passive element. The passive element is an element that consumes, stores, and discharges supplied power and does not perform active operations such as amplification and rectification, and includes, for example, a resistor, an inductance, a capacitor, and the like. A terminal is disposed on one surface of the substrate of the semiconductor device, and has a configuration that can be electrically connected to an external line of a general-purpose connector.

ここで、汎用のコネクタとは、その仕様が一般に公開されているもので、たとえば、ＵＳＢ（Universal Serial Bus）、ＩＥＥＥ１３９４（Institute of Electrical and Electronic Engineers 1394）、ＳＣＳＩ（Small Computer System Interface）、ＡＴＡ（AT Attachment）などの各種標準規格に対応したもの、あるいは、たとえば、ＲＪ−１１、ＲＪ−４５と呼ばれるコネクタなどである。   Here, general-purpose connectors are those whose specifications are publicly disclosed. For example, USB (Universal Serial Bus), IEEE 1394 (Institute of Electrical and Electronic Engineers 1394), SCSI (Small Computer System Interface), ATA ( AT Attachment) and other standards, or connectors called RJ-11 and RJ-45, for example.

この発明によれば、半導体装置の基板の端子領域の裏側に位置する領域に回路素子を搭載することができるので、従来は汎用のコネクタとの電気的および機械的な接続機能としてのみ使用されていた領域を、回路素子によって実現される別の機能に有効活用することができ、半導体装置の小型化を図ることができる。   According to the present invention, since the circuit element can be mounted in the area located behind the terminal area of the substrate of the semiconductor device, it has been conventionally used only as an electrical and mechanical connection function with a general-purpose connector. This area can be effectively used for another function realized by the circuit element, and the semiconductor device can be miniaturized.

上記半導体装置において、前記汎用のコネクタと嵌合する嵌合部と、前記回路素子を封止する封止樹脂部と、を含むことができ、前記嵌合部の少なくとも一部が前記封止樹脂部によって構成されることができる。   The semiconductor device may include a fitting portion that is fitted to the general-purpose connector and a sealing resin portion that seals the circuit element, and at least a part of the fitting portion is the sealing resin. Can be configured by parts.

ここで、封止樹脂部は、基板上に搭載された半導体素子を含む回路素子の上を封止樹脂により覆い構成される。封止樹脂は、たとえば、エポキシ樹脂である。   Here, the sealing resin portion is configured by covering the circuit element including the semiconductor element mounted on the substrate with the sealing resin. The sealing resin is, for example, an epoxy resin.

この構成によれば、半導体装置の基板に搭載された回路素子を封止樹脂で封止すると同時に、汎用のコネクタに嵌合させる嵌合部を構成することができるので、封止樹脂によって回路素子を電気的および化学的に保護し、機械的強度を増して、半導体装置の信頼性を向上させるとともに、半導体装置の回路素子が搭載された領域を汎用のコネクタとの接続部として機能させることが可能となり、半導体装置の小型化を図ることができる。   According to this configuration, the circuit element mounted on the substrate of the semiconductor device can be sealed with the sealing resin, and at the same time, the fitting portion can be configured to be fitted to the general-purpose connector. Can be electrically and chemically protected to increase the mechanical strength, improve the reliability of the semiconductor device, and function the area where the circuit elements of the semiconductor device are mounted as a connection part with a general-purpose connector. This makes it possible to reduce the size of the semiconductor device.

上記半導体装置において、前記回路素子を複数積層して前記基板上に搭載することができる。この構成によれば、複数の回路素子が積層して基板上に搭載されるので、基板の素子領域をさらに有効活用でき、半導体装置の小型化を図ることができる。   In the semiconductor device, a plurality of the circuit elements can be stacked and mounted on the substrate. According to this configuration, since the plurality of circuit elements are stacked and mounted on the substrate, the element region of the substrate can be further effectively utilized, and the semiconductor device can be reduced in size.

上記半導体装置において、前記基板の前記端子領域の裏側の領域に、半導体素子を搭載することができる。   In the semiconductor device, a semiconductor element can be mounted in a region on the back side of the terminal region of the substrate.

本発明によれば、汎用のコネクタの外部ラインに電気的に接続する端子を基板の一方の面の端子領域に配設する工程と、前記基板の前記端子領域の裏側に位置する領域に回路素子を搭載する工程と、前記回路素子を封止樹脂によって封止し、封止樹脂部を構成する工程と、を含み、前記汎用のコネクタと嵌合する嵌合部の少なくとも一部が前記封止樹脂部によって構成されることを特徴とする半導体装置の製造方法が提供される。   According to the present invention, the step of disposing a terminal electrically connected to an external line of a general-purpose connector in a terminal region on one side of the substrate, and a circuit element in a region located on the back side of the terminal region of the substrate And a step of sealing the circuit element with a sealing resin to form a sealing resin portion, and at least a part of a fitting portion to be fitted to the general-purpose connector is the sealing A method for manufacturing a semiconductor device, characterized by comprising a resin portion, is provided.

この発明によれば、半導体装置の基板の端子領域の裏側に位置する領域にも回路素子を搭載することができるので、従来は汎用のコネクタとの電気的および機械的な接続機能としてのみ使用されていた領域を、回路素子によって実現される別の機能に有効活用することができ、半導体装置の小型化を図ることができる。   According to the present invention, since the circuit element can be mounted also in the region located behind the terminal region of the substrate of the semiconductor device, it has been conventionally used only as an electrical and mechanical connection function with a general-purpose connector. This area can be effectively used for another function realized by the circuit element, and the semiconductor device can be miniaturized.

上記半導体装置の製造方法において、前記回路素子を前記基板上に複数積層して搭載する工程を含むことができる。   The method for manufacturing a semiconductor device may include a step of stacking and mounting a plurality of the circuit elements on the substrate.

本発明によれば、半導体パッケージに半導体素子および受動素子を効率よく実装することが可能となる半導体装置及びその製造方法が提供される。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can mount a semiconductor element and a passive element in a semiconductor package efficiently, and its manufacturing method are provided.

本発明は、まず第一のステップとして外部に接続される端子部と半導体素子及び受動部品が搭載される回路部を統合する回路設計により外部との接続を目的とする端子が配設された基板エリアの裏面部に半導体素子及び受動部品を搭載できる技術を発明し、その製品の動作と接続端子の二つの機能を兼ね備える半導体装置を発明した。   In the present invention, as a first step, a board on which terminals intended for connection to the outside are arranged by circuit design that integrates a terminal part connected to the outside and a circuit part on which semiconductor elements and passive components are mounted. Invented a technology capable of mounting semiconductor elements and passive components on the back surface of the area, and invented a semiconductor device having both functions of the product and connection terminals.

半導体素子及び受動部品の実装の方法としては、半田を用いた従来の表面実装技術を用いることが可能であり、そのほかには、導電ペーストを用いる方法、スタッドバンプを用いる方法などいかなる既存の方法も適用可能である。   As a method for mounting semiconductor elements and passive components, it is possible to use a conventional surface mounting technique using solder, and in addition, any existing method such as a method using a conductive paste or a method using a stud bump can be used. Applicable.

次のステップでは、全ての半導体素子及び受動部品を基板と接続した後、封止樹脂により封止されることにより半導体装置となる。また、外部に接続される端子面の端子部を除いた部分も、封止樹脂で封止することも可能である。   In the next step, after all the semiconductor elements and passive components are connected to the substrate, the semiconductor device is formed by sealing with a sealing resin. Moreover, it is also possible to seal the part except the terminal part of the terminal surface connected to the outside with a sealing resin.

次のステップでは、その封止樹脂により封止された回路素子が搭載された領域は外部との接続時の接続に関する補助的な機能も可能である。   In the next step, the area on which the circuit element sealed with the sealing resin is mounted can also have an auxiliary function related to connection when connected to the outside.

上記の発明を用いて、半導体素子と受動素子を効率よく実装できるとともに、半導体パッケージの小型化が容易である。   Using the above invention, the semiconductor element and the passive element can be efficiently mounted, and the semiconductor package can be easily downsized.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
（第一の実施の形態）
本発明の実施の形態の半導体装置を、汎用のＵＳＢコネクタのシリーズＡと呼ばれるタイプのものに適用した場合を例として以下に説明する。本実施の形態の半導体装置は、ＵＳＢコネクタのオス側を例として説明するが、これに限定されない。本実施の形態の半導体装置は、ＵＳＢコネクタのメス側およびオス側いずれにも適用可能である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
(First embodiment)
An example in which the semiconductor device according to the embodiment of the present invention is applied to a type of general-purpose USB connector called Series A will be described below. The semiconductor device of the present embodiment will be described by taking the male side of the USB connector as an example, but is not limited to this. The semiconductor device of this embodiment is applicable to both the female side and the male side of the USB connector.

図１は、本実施の形態の半導体装置の基板の例を示す断面図である。図２は、図１の半導体装置の基板の上面図である。図３は、図１の半導体装置を封止樹脂で被覆する前の基板の裏面図である。図４は、図１の半導体装置の基板の裏面図である。   FIG. 1 is a cross-sectional view showing an example of a substrate of the semiconductor device of the present embodiment. FIG. 2 is a top view of the substrate of the semiconductor device of FIG. FIG. 3 is a back view of the substrate before the semiconductor device of FIG. 1 is covered with a sealing resin. 4 is a back view of the substrate of the semiconductor device of FIG.

図１に示すように、本実施の形態の半導体装置は、プリント配線板１と、汎用のＵＳＢコネクタの外部ラインに電気的に接続する出力端子３と、出力端子３に電気的に接続される半導体素子５および受動部品２を含む回路素子と、を備える。   As shown in FIG. 1, the semiconductor device of the present embodiment is electrically connected to a printed wiring board 1, an output terminal 3 that is electrically connected to an external line of a general-purpose USB connector, and the output terminal 3. A circuit element including the semiconductor element 5 and the passive component 2.

半導体素子５および受動部品２は、所定の機能を実現する。プリント配線板１は、出力端子３が配設された端子領域７ａ（図２参照）を有する一方の面１ａと、他方の面１ｂと、を有する。プリント配線板１の他方の面１ｂは、端子領域７ａの裏側に位置する領域７ｂ（図３参照）を有し、半導体素子５および受動部品２を有する回路素子は、領域７ｂを含む領域に搭載される。   The semiconductor element 5 and the passive component 2 realize a predetermined function. The printed wiring board 1 has one surface 1a having a terminal region 7a (see FIG. 2) on which the output terminals 3 are disposed, and the other surface 1b. The other surface 1b of the printed wiring board 1 has a region 7b (see FIG. 3) located on the back side of the terminal region 7a, and the circuit element having the semiconductor element 5 and the passive component 2 is mounted in a region including the region 7b. Is done.

このように、本実施の形態の半導体装置によれば、半導体装置のプリント配線板１の端子領域７ａの裏側に位置する領域７ｂにも回路素子を搭載することができるので、従来は汎用のコネクタとの電気的および機械的な接続機能としてのみ使用されていた領域７ｂを、回路素子によって実現される別の機能に有効活用することができ、半導体装置の小型化を図ることができる。   As described above, according to the semiconductor device of the present embodiment, the circuit element can be mounted also in the region 7b located on the back side of the terminal region 7a of the printed wiring board 1 of the semiconductor device. The region 7b used only as an electrical and mechanical connection function can be effectively used for another function realized by the circuit element, and the semiconductor device can be miniaturized.

また、図１および図４に示すように、本実施の形態の半導体装置において、プリント配線板１の他方の面１ｂを封止樹脂６で覆い、半導体素子５を封止することができる。ここで、封止樹脂６は、たとえば、エポキシ樹脂などである。   As shown in FIGS. 1 and 4, in the semiconductor device of the present embodiment, the other surface 1 b of the printed wiring board 1 can be covered with a sealing resin 6 to seal the semiconductor element 5. Here, the sealing resin 6 is, for example, an epoxy resin.

この構成によれば、半導体装置のプリント配線板１に搭載された回路素子の上を封止樹脂６で覆うことができるので、回路素子を電気的および化学的に保護するとともに、機械的強度を増すことができ、半導体装置の信頼性が向上する。   According to this configuration, the circuit element mounted on the printed wiring board 1 of the semiconductor device can be covered with the sealing resin 6, so that the circuit element is electrically and chemically protected and mechanical strength is increased. This can increase the reliability of the semiconductor device.

また、本実施の形態において、封止樹脂６は、プリント配線板１の他方の面１ｂ上に厚さｄを有する層を構成する。この厚さｄは、汎用のＵＳＢコネクタのメス側との嵌合部の形状に合わせて決定され、たとえば、１．５ｍｍである。本実施の形態の嵌合部の形状は、図１および図２のように、厚さ２ｍｍ、幅１１．３７ｍｍとなる。   In the present embodiment, the sealing resin 6 forms a layer having a thickness d on the other surface 1 b of the printed wiring board 1. This thickness d is determined in accordance with the shape of the fitting portion of the general-purpose USB connector with the female side, and is 1.5 mm, for example. The shape of the fitting part of this Embodiment becomes thickness 2mm and width 11.37mm like FIG. 1 and FIG.

このように、本実施の形態によれば、封止樹脂６によって半導体装置を保護すると同時に、汎用のＵＳＢコネクタの形状に合わせてプリント配線板１を構成することができる。すなわち、本実施の形態の半導体装置を汎用のＵＳＢコネクタのソケット部とのプラグ部として構成することが可能となる。したがって、プリント配線板１上の領域７ｂを、さらに外部との機械的な接続を実現させる嵌合部として機能させることができる。   Thus, according to the present embodiment, the printed wiring board 1 can be configured in accordance with the shape of a general-purpose USB connector while simultaneously protecting the semiconductor device with the sealing resin 6. That is, the semiconductor device of this embodiment can be configured as a plug portion with a socket portion of a general-purpose USB connector. Therefore, the region 7b on the printed wiring board 1 can further function as a fitting portion that realizes mechanical connection with the outside.

以上説明したように、本実施の形態の半導体装置によれば、半導体装置のプリント配線板１の端子領域７ａの裏側に位置する領域７ｂにも回路素子を搭載することができるので、従来は汎用のコネクタとの電気的および機械的な接続機能としてのみ使用されていた領域７ｂを、回路素子によって実現される別の機能に有効活用することができ、半導体装置の小型化を図ることができる。
（第二の実施の形態）
図５は、本実施の形態の半導体装置の基板の例を示す断面図である。図６は、図５の半導体装置の基板の上面図である。図７は、図５の半導体装置を封止樹脂で被覆する前の基板の裏面図である。図８は、図５の半導体装置の基板の裏面図である。図９は、図５の半導体装置を使用したＵＳＢコネクタの正面図である。 As described above, according to the semiconductor device of the present embodiment, circuit elements can be mounted also in the region 7b located on the back side of the terminal region 7a of the printed wiring board 1 of the semiconductor device. The region 7b used only as an electrical and mechanical connection function with the connector can be effectively used for another function realized by the circuit element, and the semiconductor device can be miniaturized.
(Second embodiment)
FIG. 5 is a cross-sectional view showing an example of the substrate of the semiconductor device of this embodiment. FIG. 6 is a top view of the substrate of the semiconductor device of FIG. FIG. 7 is a back view of the substrate before the semiconductor device of FIG. 5 is covered with a sealing resin. FIG. 8 is a back view of the substrate of the semiconductor device of FIG. FIG. 9 is a front view of a USB connector using the semiconductor device of FIG.

本実施の形態の半導体装置は、汎用のＵＳＢコネクタのシリーズ・ミニＢと呼ばれるタイプのものに適用した場合の例である。本実施の形態において、ＵＳＢコネクタのオス側を例として説明するが、これに限定されない。本実施の形態の半導体装置は、ＵＳＢコネクタのメス側およびオス側いずれにも適用可能である。   The semiconductor device of the present embodiment is an example when applied to a type of general-purpose USB connector called a series mini-B. In the present embodiment, the male side of the USB connector will be described as an example, but the present invention is not limited to this. The semiconductor device of this embodiment is applicable to both the female side and the male side of the USB connector.

本実施の形態の半導体装置は、図１に示した上記実施の形態の半導体装置とは、形状およびサイズが異なる。   The semiconductor device of this embodiment is different in shape and size from the semiconductor device of the above-described embodiment shown in FIG.

半導体素子５および受動部品２は、所定の機能を実現する。プリント配線板１は、出力端子３が配設された端子領域７ａ（図６参照）を有する一方の面１ａと、他方の面１ｂと、を有する。プリント配線板１の他方の面１ｂは、端子領域７ａの裏側に位置する領域７ｂ（図７参照）を有し、半導体素子５が領域７ｂを含む領域に搭載される。   The semiconductor element 5 and the passive component 2 realize a predetermined function. The printed wiring board 1 has one surface 1a having a terminal region 7a (see FIG. 6) on which the output terminal 3 is disposed, and the other surface 1b. The other surface 1b of the printed wiring board 1 has a region 7b (see FIG. 7) located on the back side of the terminal region 7a, and the semiconductor element 5 is mounted in a region including the region 7b.

このように、本実施の形態の半導体装置によれば、半導体装置のプリント配線板１の端子領域７ａの裏側に位置する領域７ｂにも回路素子を搭載することができるので、従来は汎用のコネクタとの電気的および機械的な接続機能としてのみ使用されていた領域７ｂを、回路素子によって実現される別の機能に有効活用することができ、半導体装置の小型化を図ることができる。   As described above, according to the semiconductor device of the present embodiment, the circuit element can be mounted also in the region 7b located on the back side of the terminal region 7a of the printed wiring board 1 of the semiconductor device. The region 7b used only as an electrical and mechanical connection function can be effectively used for another function realized by the circuit element, and the semiconductor device can be miniaturized.

本実施の形態において、封止樹脂６は、プリント配線板１の他方の面１ｂを覆い、半導体素子５を封止することができる。封止樹脂６は、汎用のＵＳＢコネクタのメス側との嵌合部の形状に合わせて決定される。本実施の形態では、図９のように、嵌合部の形状は、厚さ０．５ｍｍ、幅５．０ｍｍとなる。   In the present embodiment, the sealing resin 6 covers the other surface 1 b of the printed wiring board 1 and can seal the semiconductor element 5. The sealing resin 6 is determined according to the shape of the fitting portion with the female side of a general-purpose USB connector. In the present embodiment, as shown in FIG. 9, the shape of the fitting portion is 0.5 mm thick and 5.0 mm wide.

このように構成された本実施の形態の半導体装置は、図９に示すように、ＵＳＢコネクタのハウジング８に収容される。   The semiconductor device of the present embodiment configured as described above is housed in a housing 8 of a USB connector as shown in FIG.

また、プリント配線板１の形状は特に限定されず、図１０に示すような形状であってもよい。図１０（ａ）は、本実施の形態の半導体装置の基板の上面図である。図１０（ｂ）は、図１０（ａ）の半導体装置を封止樹脂で被覆する前の基板の裏面図である。図１０（ｃ）は、図１０（ａ）の半導体装置の基板の裏面図である。   Moreover, the shape of the printed wiring board 1 is not specifically limited, A shape as shown in FIG. 10 may be sufficient. FIG. 10A is a top view of the substrate of the semiconductor device of the present embodiment. FIG. 10B is a back view of the substrate before the semiconductor device of FIG. 10A is covered with a sealing resin. FIG. 10C is a back view of the substrate of the semiconductor device of FIG.

本実施の形態の半導体装置のプリント配線板１は、図５乃至図９の上記実施の形態の半導体装置のプリント配線板１に比較して、さらに小さいサイズになっている。この実施の形態においても、上記実施の形態と同様な効果が得られる。   The printed wiring board 1 of the semiconductor device according to the present embodiment is smaller in size than the printed wiring board 1 of the semiconductor device according to the above-described embodiment shown in FIGS. Also in this embodiment, the same effect as in the above embodiment can be obtained.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。   As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

すなわち本発明は、以下の態様も含むことができる。
［１］ 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されることを特徴とする半導体装置。
［２］ 請求項１の半導体装置が外部との接続時にその半導体装置の一部を接続使用の目的に用いることを特徴とする方法。
［３］ 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されている部分を接続目的に保護することを特徴とする製造方法。
［４］ 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されている部分とそれ以外を同一成型することを特徴とする製造方法。 That is, this invention can also include the following aspects.
[1] A semiconductor device, wherein a semiconductor element and a passive element are mounted on a back surface portion of a substrate area on which a terminal intended for connection to the outside is formed.
[2] The method of claim 1, wherein a part of the semiconductor device is used for connection purpose when connected to the outside.
[3] A manufacturing method characterized in that a portion where a semiconductor element and a passive element are mounted on a back surface portion of a substrate area on which a terminal intended for connection to the outside is formed is protected for the purpose of connection.
[4] A manufacturing method, wherein a portion where a semiconductor element and a passive element are mounted is formed on the back surface portion of a substrate area on which a terminal intended for connection to the outside is formed, and the other part is molded in the same manner.

さらに、汎用のコネクタとして、上記実施の形態では、ＵＳＢコネクタの場合を例として説明したが、これに限定されない。汎用のコネクタは、仕様が一般に公開されているもので、たとえば、ＩＥＥＥ１３９４、ＳＣＳＩ、ＡＴＡなどの各種標準規格に対応したもの、あるいは、たとえば、ＲＪ−１１、ＲＪ−４５と呼ばれるコネクタなどであってもよい。   Furthermore, in the above-described embodiment, the case of a USB connector has been described as an example of a general-purpose connector, but the present invention is not limited to this. General-purpose connectors are those whose specifications are publicly available, such as those corresponding to various standards such as IEEE 1394, SCSI, ATA, etc., or connectors called RJ-11, RJ-45, etc. Also good.

また、上記実施の形態において、半導体素子５および受動部品２を含む回路素子は、プリント配線板１上に一層搭載した構成について説明したが、これに限定されない。たとえば、回路素子は、プリント配線板１上に複数積層して搭載することもできる。   Moreover, in the said embodiment, although the circuit element containing the semiconductor element 5 and the passive component 2 demonstrated the structure mounted one layer on the printed wiring board 1, it is not limited to this. For example, a plurality of circuit elements can be stacked and mounted on the printed wiring board 1.

この構成によれば、複数の回路素子を積層してプリント配線板１上に搭載するので、プリント配線板１の素子領域をさらに有効活用でき、半導体装置の小型化を図ることができる。   According to this configuration, since a plurality of circuit elements are stacked and mounted on the printed wiring board 1, the element region of the printed wiring board 1 can be further effectively utilized, and the semiconductor device can be miniaturized.

また、上記実施の形態において、プリント配線板１に配設された端子が、出力端子３である場合について説明したが、これに限定されない。プリント配線板１に配設される端子は、入力端子であってもよいし、入力端子および出力端子の両方であってもよい。   Moreover, although the said embodiment demonstrated the case where the terminal arrange | positioned at the printed wiring board 1 was the output terminal 3, it is not limited to this. The terminal disposed on the printed wiring board 1 may be an input terminal, or both an input terminal and an output terminal.

また、本発明の半導体装置は、たとえば、携帯型のＵＳＢメモリなどに適用することができる。この場合、たとえば、プリント配線板１を識別するＩＤを半導体素子に記憶させるとともに、半導体素子に、ＵＳＢメモリの使用時にコネクタ同士で認識処理を行わせることができる。
（実施例） The semiconductor device of the present invention can be applied to, for example, a portable USB memory. In this case, for example, an ID for identifying the printed wiring board 1 can be stored in the semiconductor element, and the semiconductor element can be made to perform recognition processing between the connectors when the USB memory is used.
(Example)

以下に、本発明の実施形態の一例を詳細に説明する。なお、本発明は、これにより限定されるものではない。   Hereinafter, an example of an embodiment of the present invention will be described in detail. In addition, this invention is not limited by this.

プラスチック基板を用いて作成されるプリント配線は外部に接続される端子部と半導体素子及び受動部品が搭載される回路部を統合する回路設計上において外部に接続される端子部をプリント基板の片面の一部（図２の端子領域７ａ）に配置し、他のエリアは半導体素子及び受動部品が搭載できるように設計される。   The printed wiring created using the plastic substrate is connected to the externally connected terminal portion on the one side of the printed circuit board in the circuit design integrating the circuit portion on which the semiconductor element and the passive component are mounted. Arranged in a part (terminal region 7a in FIG. 2), the other areas are designed so that semiconductor elements and passive components can be mounted.

次に、外部に接続される端子部が配設されているエリア（図２の端子領域７ａ）の裏面部（図３の領域７ｂ）は外部との接続時においてその補助的機能を果たすことが可能な設計にする。   Next, the back surface portion (region 7b in FIG. 3) of the area (terminal region 7a in FIG. 2) in which the terminal portion connected to the outside is disposed can fulfill its auxiliary function when connected to the outside. Make the design possible.

次にワイヤーボンディングの手法により、半導体素子及び受動部品をプリント配線板に接続した後、外部に接続される端子部が配設されているエリアの裏面部（図３の領域７ｂ）は外部との接続時においてその補助的機能を果たすために、トランスファーモールドの手法により封止樹脂で封止した。   Next, after the semiconductor element and the passive component are connected to the printed wiring board by the wire bonding method, the back surface portion (region 7b in FIG. 3) of the area where the terminal portion to be connected to the outside is disposed is connected to the outside. In order to perform the auxiliary function at the time of connection, it was sealed with a sealing resin by a transfer molding method.

このようにして得られた、外部との接続を目的とする端子が配設された基板エリアの裏面部（図３の領域７ｂ）に半導体素子及び受動部品を搭載できる半導体装置は動作確認試験に供せられ半導体装置としての動作に何の問題のないことが確認された。
（比較例１） The thus obtained semiconductor device in which the semiconductor element and the passive component can be mounted on the back surface portion (region 7b in FIG. 3) of the substrate area on which the terminal for connection with the outside is disposed is used for the operation confirmation test. It was confirmed that there was no problem in the operation as a semiconductor device.
(Comparative Example 1)

図１１乃至図１３に、従来の技術で回路素子を実装した基板を有する半導体装置の構造を示す。比較例の半導体装置は、ＵＳＢコネクタのシリーズＡに適用した例である。図１１は、従来の技術で半導体素子および受動部品を実装した基板上面の例を示す概略図である。図１２は、従来の技術で半導体素子および受動部品を実装した基板裏面の例を示す概略図である。図１３は、従来の技術で半導体素子および受動部品を実装した基板断面の例を示す概略図である。   11 to 13 show the structure of a semiconductor device having a substrate on which circuit elements are mounted by conventional techniques. The semiconductor device of the comparative example is an example applied to a series A of USB connectors. FIG. 11 is a schematic view showing an example of the upper surface of a substrate on which a semiconductor element and passive components are mounted by a conventional technique. FIG. 12 is a schematic view showing an example of the back surface of a substrate on which a semiconductor element and passive components are mounted by a conventional technique. FIG. 13 is a schematic view showing an example of a cross section of a substrate on which a semiconductor element and a passive component are mounted by a conventional technique.

図１１乃至図１３に示すように、従来の半導体装置においては、出力端子１３は、プリント配線板１１の一方の面１１ａ上の端子領域１７ａに配設される。一方、プリント配線板１１の他方の面１１ｂ上の領域１７ｂには、スペーサ１４が設けられている。この半導体装置の嵌合部の形状は汎用のＵＳＢコネクタのメス側との嵌合部の形状に合わせて、スペーサ１４の厚さは１．２ｍｍで、プリント配線板１１の厚さは０．８ｍｍ、幅は１１．３７ｍｍとなる。   As shown in FIGS. 11 to 13, in the conventional semiconductor device, the output terminal 13 is disposed in the terminal region 17 a on the one surface 11 a of the printed wiring board 11. On the other hand, a spacer 14 is provided in the region 17 b on the other surface 11 b of the printed wiring board 11. The shape of the fitting portion of this semiconductor device matches the shape of the fitting portion with the female side of a general-purpose USB connector, the thickness of the spacer 14 is 1.2 mm, and the thickness of the printed wiring board 11 is 0.8 mm. The width is 11.37 mm.

半導体素子１５および受動部品１２を含む回路素子は、プリント配線板１１の端子領域１７ａおよび領域１７ｂ以外の領域に搭載される。このように従来の半導体装置をＵＳＢコネクタに適用した場合、嵌合部はＵＳＢコネクタのメス側と嵌合する機能にのみ使用される。このため、図１乃至図３の本発明の実施の形態の半導体装置に比較して、プリント配線板１および装置全体のサイズが大きくなる。
（比較例２） The circuit element including the semiconductor element 15 and the passive component 12 is mounted in an area other than the terminal area 17a and the area 17b of the printed wiring board 11. Thus, when the conventional semiconductor device is applied to a USB connector, the fitting portion is used only for the function of fitting with the female side of the USB connector. For this reason, the printed wiring board 1 and the entire size of the device are larger than those of the semiconductor device according to the embodiment of the present invention shown in FIGS.
(Comparative Example 2)

図１４乃至図１６に、従来の技術で回路素子を実装した基板を有する半導体装置の構造を示す。比較例の半導体装置は、ＵＳＢコネクタのシリーズ・ミニＢに適用した例である。図１４は、従来の技術で半導体素子および受動部品を実装した基板上面の例を示す概略図である。図１５は、従来の技術で半導体素子および受動部品を実装した基板裏面の例を示す概略図である。図１６は、従来の技術で半導体素子および受動部品を実装した基板断面の例を示す概略図である。   14 to 16 show a structure of a semiconductor device having a substrate on which circuit elements are mounted by a conventional technique. The semiconductor device of the comparative example is an example applied to the series mini B of the USB connector. FIG. 14 is a schematic view showing an example of the upper surface of a substrate on which a semiconductor element and passive components are mounted by a conventional technique. FIG. 15 is a schematic diagram showing an example of the back surface of a substrate on which a semiconductor element and passive components are mounted by a conventional technique. FIG. 16 is a schematic view showing an example of a cross section of a substrate on which a semiconductor element and passive components are mounted by a conventional technique.

図１４乃至図１６に示すように、従来の半導体装置は、プリント配線板１１の一端にＵＳＢコネクタのメス側との嵌合部を構成するハウジング１８を備えている。ハウジング１８内には、出力端子１３がその一面に配設される樹脂製の嵌合部１９が形成される。出力端子１３は、嵌合部１９からプリント配線板１１上に延在し、プリント配線板１１上の半導体素子１５および受動部品１２と電気的に接続される。   As shown in FIGS. 14 to 16, the conventional semiconductor device includes a housing 18 that constitutes a fitting portion with the female side of the USB connector at one end of the printed wiring board 11. A resin fitting portion 19 in which the output terminal 13 is disposed on one surface thereof is formed in the housing 18. The output terminal 13 extends from the fitting portion 19 onto the printed wiring board 11 and is electrically connected to the semiconductor element 15 and the passive component 12 on the printed wiring board 11.

図１４乃至図１６の従来の半導体装置において、ＵＳＢコネクタのメス側との嵌合部１９は、プリント配線板１１と別途設けられた構成であり、嵌合部１９は、ＵＳＢコネクタのメス側と嵌合する機能にのみ使用される。このため、図５乃至図９の本発明の実施の形態の半導体装置に比較して、装置全体のサイズが大きくなる。   In the conventional semiconductor device of FIGS. 14 to 16, the fitting portion 19 on the female side of the USB connector is provided separately from the printed wiring board 11, and the fitting portion 19 is connected to the female side of the USB connector. Used only for mating functions. Therefore, the overall size of the device is larger than the semiconductor device according to the embodiment of the present invention shown in FIGS.

本発明によれば、半導体チップと受動部品をひとつのパッケージに搭載した半導体装置を作製することができるという効果を有し、小型・軽量化及び高機能・大容量化を目的とする半導体チップの実装技術等として有用である。   According to the present invention, there is an effect that a semiconductor device in which a semiconductor chip and a passive component are mounted in one package can be manufactured, and a semiconductor chip intended for miniaturization, weight reduction, high function, and large capacity is provided. This is useful as a mounting technique.

本発明の実施の形態に係る半導体装置の基板の断面の例を示す概略図である。It is the schematic which shows the example of the cross section of the board | substrate of the semiconductor device which concerns on embodiment of this invention. 図１の半導体装置の基板の上面を示す概略図である。FIG. 2 is a schematic view showing an upper surface of a substrate of the semiconductor device of FIG. 1. 図１の半導体装置の封止樹脂で封止する前の基板の裏面を示す概略図である。It is the schematic which shows the back surface of the board | substrate before sealing with the sealing resin of the semiconductor device of FIG. 図１の半導体装置の基板の裏面を示す概略図である。It is the schematic which shows the back surface of the board | substrate of the semiconductor device of FIG. 本発明の実施の形態に係る半導体装置の基板の断面の例を示す概略図である。It is the schematic which shows the example of the cross section of the board | substrate of the semiconductor device which concerns on embodiment of this invention. 図５の半導体装置の基板の上面を示す概略図である。FIG. 6 is a schematic view showing an upper surface of a substrate of the semiconductor device of FIG. 5. 図５の半導体装置の封止樹脂で封止する前の基板の裏面を示す概略図である。It is the schematic which shows the back surface of the board | substrate before sealing with the sealing resin of the semiconductor device of FIG. 図５の半導体装置の基板の裏面を示す概略図である。FIG. 6 is a schematic view showing a back surface of a substrate of the semiconductor device of FIG. 5. 図５の半導体装置を使用したコネクタの正面図である。FIG. 6 is a front view of a connector using the semiconductor device of FIG. 5. 本発明の他の実施の形態に係る半導体装置の基板の例を示す概略図である。It is the schematic which shows the example of the board | substrate of the semiconductor device which concerns on other embodiment of this invention. 従来の技術で半導体素子および受動部品を実装した基板上面の例を示す概略図である。It is the schematic which shows the example of the board | substrate upper surface which mounted the semiconductor element and the passive component by the prior art. 図１１の従来の基板の裏面の例を示す概略図である。It is the schematic which shows the example of the back surface of the conventional board | substrate of FIG. 図１１の従来の基板の断面の例を示す概略図である。It is the schematic which shows the example of the cross section of the conventional board | substrate of FIG. 従来の技術で半導体素子および受動部品を実装した基板上面の他の例を示す概略図である。It is the schematic which shows the other example of the board | substrate upper surface which mounted the semiconductor element and the passive component by the prior art. 図１４の従来の基板の裏面の例を示す概略図である。It is the schematic which shows the example of the back surface of the conventional board | substrate of FIG. 図１４の従来の基板の断面の例を示す概略図である。It is the schematic which shows the example of the cross section of the conventional board | substrate of FIG.

符号の説明Explanation of symbols

１ プリント配線板
２ 受動部品
３ 出力端子
５ 半導体素子
６ 封止樹脂
７ａ 端子領域
７ｂ 領域
８ ハウジング DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Passive component 3 Output terminal 5 Semiconductor element 6 Sealing resin 7a Terminal area | region 7b Area | region 8 Housing

Claims (6)

汎用のコネクタの外部ラインに電気的に接続する端子と、
前記端子に電気的に接続され、所定の機能を有する回路素子と、
前記端子が配設された端子領域を有する基板と、
を備え、
前記基板の前記端子領域の裏側に位置する領域に前記回路素子が搭載されることを特徴とする半導体装置。 A terminal that is electrically connected to an external line of a general-purpose connector;
A circuit element electrically connected to the terminal and having a predetermined function;
A substrate having a terminal region in which the terminals are disposed;
With
A semiconductor device, wherein the circuit element is mounted in a region located on the back side of the terminal region of the substrate. 請求項１に記載の半導体装置において、
前記汎用のコネクタと嵌合する嵌合部と、
前記回路素子を封止する封止樹脂部と、を含み、
前記嵌合部の少なくとも一部が前記封止樹脂部によって構成されることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A fitting portion for fitting with the general-purpose connector;
A sealing resin portion for sealing the circuit element,
At least a part of the fitting portion is constituted by the sealing resin portion. 請求項１または２に記載の半導体装置において、
前記回路素子は、複数積層して前記基板上に搭載されることを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
A plurality of the circuit elements are stacked and mounted on the substrate. 請求項１乃至３いずれかに記載の半導体装置において、
前記基板の前記端子領域の裏側の領域に、半導体素子が搭載されることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device, wherein a semiconductor element is mounted in a region on the back side of the terminal region of the substrate. 汎用のコネクタの外部ラインに電気的に接続する端子を基板の一方の面の端子領域に配設する工程と、
前記基板の前記端子領域の裏側に位置する領域に回路素子を搭載する工程と、
前記回路素子を封止樹脂によって封止し、封止樹脂部を構成する工程と、を含み、
前記汎用のコネクタと嵌合する嵌合部の少なくとも一部が前記封止樹脂部によって構成されることを特徴とする半導体装置の製造方法。 Arranging a terminal electrically connected to an external line of a general-purpose connector in a terminal region on one side of the substrate;
Mounting a circuit element in a region located on the back side of the terminal region of the substrate;
Sealing the circuit element with a sealing resin, and forming a sealing resin portion,
A method of manufacturing a semiconductor device, wherein at least a part of a fitting portion to be fitted to the general-purpose connector is constituted by the sealing resin portion. 請求項５に記載の半導体装置の製造方法において、
前記回路素子を前記基板上に複数積層して搭載する工程を含むことを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, comprising a step of stacking and mounting a plurality of the circuit elements on the substrate.
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