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JP2005167057A5 - - Google Patents

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Publication number
JP2005167057A5
JP2005167057A5 JP2003405622A JP2003405622A JP2005167057A5 JP 2005167057 A5 JP2005167057 A5 JP 2005167057A5 JP 2003405622 A JP2003405622 A JP 2003405622A JP 2003405622 A JP2003405622 A JP 2003405622A JP 2005167057 A5 JP2005167057 A5 JP 2005167057A5
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doped
thin film
film transistor
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JP2003405622A
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JP2005167057A (en
JP4253245B2 (en
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Publication of JP2005167057A5 publication Critical patent/JP2005167057A5/ja
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基板上に形成された非単結晶の結晶性シリコン膜を島状領域とし、それぞれソース・ドレイン領域、該ソース・ドレイン領域間にＬＤＤ領域を介して設定されるチャネル領域及び該チャネル領域上に絶縁膜を介して配置されたゲートを有する薄膜トランジスタであって、
前記ＬＤＤ領域の上層部に所定の濃度にドープされた領域を設け、その下層部に、相対的に高濃度にドープされた領域を設けたことを特徴とする薄膜トランジスタ。 A non-single crystalline crystalline silicon film formed on a substrate is used as an island-shaped region, and a source / drain region, a channel region set between the source / drain regions via an LDD region, and insulation on the channel region, respectively. A thin film transistor having a gate disposed through a film,
A thin film transistor comprising a region doped with a predetermined concentration in an upper layer portion of the LDD region and a region doped with a relatively high concentration in a lower layer portion thereof. 前記ゲートが前記ＬＤＤ領域を少なくとも部分的に覆うことを特徴とする請求項１に記載の薄膜トランジスタ。   The thin film transistor of claim 1, wherein the gate at least partially covers the LDD region. 基板上に形成された非単結晶の結晶性シリコン膜を島状領域とし、それぞれソース・ドレイン領域、該ソース・ドレイン領域間にＬＤＤ領域を介して設定されるチャネル領域及び該チャネル領域上に絶縁膜を介して配置されたゲートを有する薄膜トランジスタの製造方法であって、
前記ＬＤＤ領域に対するドーピングを、比較的高ドーズ・高加速により行い、前記ＬＤＤ領域の上層部に所定の濃度にドープされた領域を設け、その下層部に、相対的に高濃度にドープされた領域を設けたことを特徴とする薄膜トランジスタの製造方法。 A non-single crystalline crystalline silicon film formed on a substrate is used as an island-shaped region, and a source / drain region, a channel region set between the source / drain regions via an LDD region, and insulation on the channel region, respectively. A method of manufacturing a thin film transistor having a gate disposed through a film,
Doping of the LDD region is performed at a relatively high dose and high acceleration, a region doped at a predetermined concentration is provided in the upper layer portion of the LDD region, and a relatively highly doped region is formed in the lower layer portion thereof A method of manufacturing a thin film transistor , comprising: 基板上に形成された非単結晶の結晶性シリコン膜を島状領域とし、それぞれソース・ドレイン領域、該ソース・ドレイン領域間にＬＤＤ領域を介して設定されるチャネル領域及び該チャネル領域上に絶縁膜を介して配置されたゲートを有する薄膜トランジスタの製造方法であって、
前記ＬＤＤ領域に対するドーピングを、高加速及び低加速により、２段階に分けて行なうことにより、前記ＬＤＤ領域の上層部に所定の濃度にドープされた領域を設け、その下層部に、相対的に高濃度にドープされた領域を設けたことを特徴とする薄膜トランジスタの製造方法。 A non-single crystalline crystalline silicon film formed on a substrate is used as an island-shaped region, and a source / drain region, a channel region set between the source / drain regions via an LDD region, and insulation on the channel region, respectively. A method of manufacturing a thin film transistor having a gate disposed through a film,
The LDD region is doped in two stages by high acceleration and low acceleration, thereby providing a region doped at a predetermined concentration in the upper layer portion of the LDD region, and relatively lower in the lower layer portion. A method of manufacturing a thin film transistor , characterized in that a region doped in concentration is provided. 基板上に形成された非単結晶の結晶性シリコン膜を島状領域とし、それぞれソース・ドレイン領域、該ソース・ドレイン領域間にＬＤＤ領域を介して設定されるチャネル領域及び該チャネル領域上に絶縁膜を介して配置されたゲートを有する薄膜トランジスタの製造方法であって、
前記ＬＤＤ領域に対するドーピングを、軽重２種のイオンを用いて行い、前記ＬＤＤ領域の上層部に所定の濃度にドープされた領域を設け、その下層部に、相対的に高濃度にドープされた領域を設けたことを特徴とする薄膜トランジスタの製造方法。 A non-single crystalline crystalline silicon film formed on a substrate is used as an island-shaped region, and a source / drain region, a channel region set between the source / drain regions via an LDD region, and insulation on the channel region, respectively. A method of manufacturing a thin film transistor having a gate disposed through a film,
The LDD region is doped using two types of light ions, a region doped at a predetermined concentration is provided in the upper layer portion of the LDD region, and a relatively highly doped region is provided in the lower layer portion. A method of manufacturing a thin film transistor , comprising:
JP2003405622A 2003-12-04 2003-12-04 Thin film transistor manufacturing method Expired - Fee Related JP4253245B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003405622A JP4253245B2 (en) 2003-12-04 2003-12-04 Thin film transistor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003405622A JP4253245B2 (en) 2003-12-04 2003-12-04 Thin film transistor manufacturing method

Publications (3)

Publication Number Publication Date
JP2005167057A JP2005167057A (en) 2005-06-23
JP2005167057A5 true JP2005167057A5 (en) 2006-04-06
JP4253245B2 JP4253245B2 (en) 2009-04-08

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JP2003405622A Expired - Fee Related JP4253245B2 (en) 2003-12-04 2003-12-04 Thin film transistor manufacturing method

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JP (1) JP4253245B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142082A (en) * 2005-11-17 2007-06-07 Hitachi Displays Ltd Display device, and method of manufacturing same
JP5196470B2 (en) * 2007-07-31 2013-05-15 独立行政法人産業技術総合研究所 Double insulated gate field effect transistor

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