JP5196470B2 - Double insulated gate field effect transistor - Google Patents

Description

  The present invention relates to an improved structure of a double insulated gate MOS transistor.

  FIG. 1 is a block diagram of a conventional double gate field effect transistor. A conventional double gate field effect transistor shown in FIG. 1 includes a source region 1 and a drain region 2 into which a high-concentration impurity of the first conductivity type is introduced, a channel region 3 interposed between and in contact with each other, a channel region A second gate insulator 8 on a second surface 7 opposite to the first surface of the channel region 3 and a first gate electrode 6 in contact with the first surface 4 of the third through a first gate insulator 5. A second gate electrode 9 in contact with each other via, for example, known as “double-gate field-effect transistor” in Patent Document 1 and “double-gate transistor and manufacturing method thereof” in Patent Document 2 Yes.

  These double insulated gate field effect transistors have a so-called short channel effect (the conventional structure was almost constant in the thickness direction (Y direction) of the high concentration impurity distribution in the source or drain region. A high electric field is likely to occur near the drain region of the region, and an increase in drain current (GIDL) was observed due to the band-to-band tunneling phenomenon.

  Degradation of electrical characteristics that becomes apparent as the gate length (and channel length) decreases. As the source and drain approach, the drain effect reaches the source. Specifically, the gate threshold voltage decreases, the drain current rises (S-slope increases), and the standby. Fatal problems arise in integrated circuits such as increased leakage current. ) Is known as a promising structure. Note that the source region and the drain region are usually arranged symmetrically with respect to the channel region so that the same electrical characteristics can be obtained even if their roles are switched.

  In FIG. 1, for convenience of explanation, the direction from the source region to the drain region is the X direction, the direction from the first gate electrode to the second gate electrode is the Y direction, and the plane is formed by the X direction and the Y direction. The vertical direction is the Z direction. The double insulated gate field effect transistor of FIG. 1 is fabricated on a substrate, but the X, Y, and Z directions with respect to the substrate may be arbitrary.

  Hereinafter, for convenience of explanation, it is assumed that the substrate surface is parallel to the XY plane. The length of the channel region in the Z direction is the channel width (W), the length in the X direction is the channel length (LC), the length of the channel region 3 in the Y direction is the channel thickness (TS), and the gate electrode is the channel region. The length in the X direction of the portion in contact with the gate insulating film is referred to as a gate length (LG).

  The gate electrode material is preferably a metal or polysilicon having a high concentration of impurities, such as extremely low electrical conductivity, and may not necessarily be the same material, and the first gate electrode and the second gate electrode are different. Materials may be used.

  Furthermore, although the gate insulating film thicknesses for each are To1 and To2, this value may not necessarily be the same. Further, normally, the high concentration impurity distribution in the source region and the drain region is substantially uniform in the Y and Z directions, and in the X direction, a certain distribution function, for example, a Gaussian distribution or an error function distribution is directed toward the channel region. is decreasing. Therefore, although usually LC is smaller than LG, it is difficult to define clearly.

The double insulated gate field effect transistor as described above is recognized as suitable for fine structure, but when the channel length LC (which may be referred to as the gate length LG) is shortened, the transistor operation is in the off state. The increase in drain leakage current becomes obvious.
This point is regarded as important as a problem to be solved from the viewpoint of power consumption reduction, and various proposals have been made for the solution.

The increase in the drain leakage current is due to the potential of the drain and gate electrodes in the off state, in addition to the increase in drain current in the so-called subthreshold region caused by the decrease in the threshold voltage to cope with the lower power supply voltage. increasing the electric field near the drain is caused a so-called band-to-band tunneling phenomenon (abbreviated as BBT) can, carriers are generated in the channel region, an excessive drain current flows (GIDL, called G ate I nduced D rain L eakage There is a cause.

  In particular, when the channel region is in an electrically floating state like a double insulated gate MOS transistor, a carrier 2 having a conductivity type opposite to that of the carrier 1 for carrying a normal current is accumulated in the channel region, so that the source region The increase phenomenon is more serious than that of a normal field effect transistor due to an increase in the injection of the carrier 1 from. In order to reduce the excessive increase in drain current due to GIDL, the strength of the electric field in the vicinity of the drain in the off state may be reduced.

As one of the methods, the following non-patent documents 1 to 4 suggest that the gate electrode end and the impurity introduction end to the source or drain are separated by a certain distance (Lu) as shown in FIG. Has been.
FIG. 2 is a schematic view of the source region 1, the channel region 3, and the drain region 2 of FIG. 1 as viewed in the X direction, and is a conceptual diagram of an underlap structure in a conventional double gate field effect transistor.

  That is, by separating the high impurity concentration introduction hole end of the drain region from the gate electrode end to which a low potential is applied by an underlap length Lu (usually having the same structure in the source region), a potential substantially equal to the power supply voltage is obtained. When is applied to the drain, the electric field under the gate electrode in the vicinity of the drain region can be reduced.

FIG. 3 is a diagram showing the effect of reducing the underlap GIDL when the conventional source or drain impurity concentration distribution is applied to the double gate field effect transistor.
FIG. 3 is an example of gate voltage (V) vs. drain current (A / μm, ampere / micrometer) characteristics by two-dimensional device simulation. However, the same potential is applied to the first gate electrode and the second gate electrode. Due to the characteristics, there is a problem with the drain current value when the gate voltage is between 0.0 and 0.1.

Japanese Patent No. 3543117 JP 2003-163356 A Y. -K. Choi, D. Ha, T. -J. King and J. Bokor: “Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices”, Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 2073-2076. V. Trivedi, J. G. Fossum, and M. M. Chowdhury: “Nanoscale FinFETs With Gate-Source / Drain Underlap”, IEEE Trans. On Electron Devices, Vol.52, No.1, 2005, pp.56-62. K. Tanaka, K. Takeuchi, and M. Hane: “Practical FinFET Design Considering GIDL for LSTP (Low Standby Power) Devices”, IEDM 2005, pp.1001-1004. K. Tanaka, K. Takeuchi, and M. Hane: “Source / Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices”, IEICE, Electron, Vol.E90-C, No. 4 April, 2007, pp. 842-847.

  As shown in FIG. 3, when the drain voltage Vd is equal to the power supply voltage (1V in the case of FIG. 3), when the gate voltage is lowered, the drain current Id becomes an exponential function at a threshold voltage (about 0.3V) or less. However, the gate voltage is rapidly increased near the off potential (0 V). This phenomenon is the GIDL effect. This phenomenon occurs when the gate potential is such that the double insulated gate field effect transistor is turned off with the drain at a high potential even when different potentials are applied to the first gate electrode and the second gate electrode. Also occurs.

  FIG. 3 shows the gate voltage (v) -drain current (A / um) characteristics when Lu (nm) is 0, 5, 10, and 15. As shown in FIG. 3, the increase in drain leakage current due to GIDL decreases as Lu increases, but the increase in source or drain parasitic resistance and the controllability of drain current due to the gate electrode may decrease. For this reason, there is a drawback that the on-current is reduced. Therefore, it is desirable to reduce the drain leakage current due to GIDL while suppressing the decrease in on-current with the smallest possible Lu. That is, an element structure that can reduce the GIDL phenomenon from the conventional method even with the same Lu is desired.

  In view of the above problems, an object of the present invention is to provide an element structure that reduces the increase in drain leakage current when the double insulated gate field effect transistor is turned off with a high potential applied to the drain as compared with the conventional method. Is to provide.

The present invention, in order to achieve the above object, a source region and a drain region into which impurities are introduced at a high concentration, respectively, a channel region is interposed in contact between them source and drain regions, the source region And a film-like first gate insulator provided in contact with one of the opposing surfaces including the same direction as the first direction from the source region to the drain region of the rectangular parallelepiped portion comprising the drain region and the channel region A film-like second gate insulator provided in contact with the other surface of the opposing surfaces, and the first and second gate insulators in a second direction orthogonal to the first direction. A double insulated gate field effect transistor having first and second gate electrodes respectively provided via
The concentration characteristics of the impurities in the source region and the drain region are as follows. The concentration of the impurity is in the second direction from the first gate insulator to the second gate insulator. As the distance from the inside of the region to the surface in contact with the first and second gate insulators decreases, the highest concentration end position of the impurity in the source region and the drain region is reduced from the source region to the drain. In the first direction toward the region, the first gate electrode and the second gate electrode are located away from the channel region corresponding to the end portions of the first gate electrode and the second gate electrode.

In order to achieve the above object, according to the present invention, the concentration characteristics in the source region and the drain region are such that the second direction from the first gate insulator toward the second gate insulator is It is characterized in that the peak of the highest concentration is located in the central part inside the source region and the drain region.

  In the double insulated gate field effect transistor of the present invention, the source electrode and the drain region are formed with regions in which the concentration characteristics of the impurity gradually increase as they move away from the surface in contact with the gate insulator. In addition, a structure in which the impurity concentration of the portion where the drain electrode and the drain electrode are opposed to each other can be gradually reduced, and an electric field can be prevented from concentrating on the electrode ends.

Further, since the peak concentration end position of the impurity in the source region and the drain region is formed to be separated by a predetermined Lu from the gate electrode end position, an increase in drain leakage current due to GIDL is suppressed, and the source or drain It is possible to suppress an increase in parasitic resistance, improve controllability of the drain current by the gate electrode, and suppress a so-called decrease in on-current.
Since the present invention is configured as described above, the GIDL phenomenon can be reduced from the conventional method even if the underlap length Lu is the same.

  Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 11 is an explanatory diagram of a double insulated gate field effect transistor of the present invention.
FIG. 11A shows a configuration diagram of an embodiment of the double insulated gate field effect transistor of the present invention , and the basic configuration is the same as that of the conventional double insulated gate field effect transistor of FIG . A film-like shape provided in contact with one of the opposing surfaces including the same direction as the first direction from the source region 1 to the drain region 2 of the rectangular parallelepiped portion comprising the source region 1, the drain region 2, and the channel region 3 The first gate insulator 5, the film-like second gate insulator 8 provided in contact with the other of the opposing surfaces, and the first and second gate insulators in a second direction orthogonal to the first direction. First and second gate electrodes 6 and 9 are provided through second gate insulators 5 and 8, respectively.
The double insulated gate field effect transistor of the present invention has the above basic configuration in the Y direction (from the first gate insulator 5 to the second gate insulation ) in the source region 1 and the drain region 2 of FIG. As shown by the solid lines in FIG. 11B, the impurity concentration distribution in the second direction toward the object 8 is from the inside of the source region 1 and the drain region 2 to the first and second gate insulators 5, 8 and It is characterized by a distribution that becomes lower as it gets closer to the contacting surface.

FIG. 11 (b), the source region 1 and drain region 2 shown FIG. 11 (a), the impurity concentration distribution characteristic of the conventional invention definitive in the Y direction is shown. That is, the impurity concentration distribution in the Y direction of the conventional source region 1 and drain region 2 is substantially constant as shown by the dotted line in FIG. On the other hand, the impurity concentration distribution in the Y direction of the source region 1 and the drain region 2 of the present invention has a characteristic that becomes lower as the distance from the inside of the source region 1 and the drain region 2 to the surface in contact with the gate insulators 5 and 8 becomes closer. The Specifically, the impurity concentration distribution in the Y direction of the source region 1 and the drain region 2 of the present embodiment is highest at the center of the source region 1 and the drain region 2 as shown by a solid line in FIG. The concentration peak position is shown, and gradually decreases exponentially from the central peak (highest) concentration region toward both gate electrodes 6 and 9 (surfaces in contact with the gate insulators 5 and 8) .

Further, as shown in FIG. 4, the highest concentration end position of the impurity within the source region 1 and drain region 2 (peak concentration end position in FIG. 4) is the direction from the source region 1 to the drain region 2 (X-direction) in, Ru is the first position of the channel region 3 corresponding to the end portion of the gate electrode 6 and the second gate electrode 9 (gate electrode end position of FIG. 4) than by Lu away.

4, a source in a double insulated gate field effect transistor in FIG. 11 of the present invention (a), an impurity concentration line of impurity distribution in the drain region, a view expressed on X-Y plane shown in FIG. 11 (a) is there.
The continuous dotted line and wavy line in FIG. 4 indicate the contour lines of the impurity distribution inside the double insulated gate field effect transistor (a set of points having the same impurity concentration is indicated by a line).

  In FIG. 4, the gate length LG (the length between both gate electrode end positions) is 100 nm, and the gate insulating film (both outside the solid line with vertical axis ± 0.005 (not shown)) thicknesses To1 and To2 are 2 nm. The channel thickness Ts (in the figure, the length between the solid lines of the vertical axis ± 0.005) was 10 nm. The high concentration impurity distribution in the source and drain regions is a Gaussian distribution, and the characteristic length (the distance from the peak concentration position to the point where the concentration is about 0.1 times) is 10 nm.

  In FIG. 4, the isoimpurity concentration line in the region e inside both solid lines d indicating the gate electrode end position is the vertical axis from the positions a and c where the isoimpurity concentration line closest to the solid line d is ± 0.005 on the vertical axis. As represented by the fact that the center position b of 0 is slightly curved so as to be further away from the solid line, it is slightly curved so as to be separated from the solid line d as a whole.

  As shown in FIG. 5, the impurity concentration characteristic at a position parallel to both solid lines d indicating the gate electrode end position in FIG. 4 is a logarithmic impurity concentration value at both end positions in the source region Y direction (horizontal axis direction). On the other hand, the logarithmic impurity concentration value at the center position in the source region Y direction is large. That is, the impurity concentration characteristics in the source region Y direction in FIG. 5 are curved so that the central portion protrudes upward. As a result, the impurity concentration at the end of the source region facing the gate electrode is lower than that at other portions of the source region, and the concentration of the electric field is suppressed.

  The drain region also has the same Y-direction impurity concentration characteristics as the source region. The drain region end facing the gate electrode has a lower impurity concentration than other portions of the drain region, and the concentration of the electric field is suppressed.

Further, as shown in FIG. 4, for example, the impurity concentration characteristics of the source region and the drain region are such that the central position in the Y direction (position where the vertical axis is 0) of each region is a linear peak concentration (10 ²⁰ cm ^{− 3} ). The end of the linear peak concentration is separated from the isoimpurity concentration line representing the maximum value of the impurity concentration characteristics of the channel region (see the peak concentration end position). This indicates that the high concentration impurity regions of the source region and the drain region are separated from the end of the channel region. Thereby, the concentration of the electric field between the gate region end and the source region end and the drain region end can be reduced.

  From the above description, if the isoimpurity concentration lines are summarized so as to be continuous values, the isoimpurity concentration characteristics gradually decrease in the vertical direction along the vertical axis with the vertical axis 0 in FIG. 4 as the center. As shown in FIG. 4, the impurity concentration characteristics in the source region Y direction facing the gate electrode end are curved so that the central portion protrudes upward.

FIG. 5 is a view showing the impurity distribution in the YZ section of the source or drain region of the double gate field effect transistor according to the present invention. FIG. 5 shows the Y-direction distribution of the impurity distribution in the drain region (or source region).
As a result, the impurity concentration at the end of the source region facing the gate electrode is lower than that at other portions of the source region, and the concentration of the electric field is suppressed.

Furthermore, the impurity concentration characteristics of the source region, channel region, and drain region in the X direction in FIG. 4 are as shown in FIG.
Figure 6 shows the impurity concentration distribution in the double-insulated-gate field-effect transistor from the source region of the data in the X direction along the central portion of the channel leading to the drain region X-Z cross section in the present invention. As shown in FIG. 6, the impurity concentration characteristics of the connection portion between the channel region and the source and drain regions on both sides thereof are rounded so as not to cause sharp corners. Thereby, the concentration of the electric field at the opposite region ends can be suppressed.

  As a result, as shown in FIG. 5, the position of the minimum value of the impurity distribution characteristics of the source region and the drain region is set as the both end positions in the source region Y direction, and the peak position is a position that coincides with the center of the channel thickness (cut in the Y direction In the figure, it is placed at substantially the center of the source region and the drain region, and is further separated by Lu from the gate electrode end in the X direction. The distribution decreases in the Y direction toward the channel surface and also in the X direction toward the channel interior.

  Then, even if the underlap length Lu is zero, the impurity concentration in the vicinity of the gate electrode end decreases, and the electric field strength in the vicinity thereof can be reduced. Further, if Lu is provided, the effect of suppressing the electric field can be made larger than that of the conventional structure, and the effect of suppressing the GIDL effect can be further increased.

FIG. 7 shows the GIDL mitigation effect of the double gate field effect transistor of the present invention.
Actually, as a result of device simulation, the result is a result of drain current versus gate voltage in the case of a conventional structure (element dimensions are the same as in FIG. 4), that is, when the impurity distribution in the source region and the drain region is substantially uniform in the Y direction. 7 and the case of the structure of the present invention are compared with the case of FIG. 7 which is the simulation result under the same bias condition, it can be seen that the present invention further reduces GIDL at the same Lu. That is, the drain current characteristic in the characteristic curve of FIG. 7 from the gate voltage of 0.0 V to around 0.2 V is lower than the characteristic of the conventional example of FIG.

In other words, when the drain leakage current at the off time is defined, the present invention shows that the value can be realized with a smaller Lu, and it is possible to suppress an increase in parasitic resistance and to reduce the controllability of the drain current by the gate electrode. It can be said that it can be reduced. The impurity concentration of the original channel region is uniform and is N-type and 10 ¹⁷ / cm ³ , but may be P-type or no impurity concentration. If the value of the concentration is less than this level, the channel thickness Ts is thin, so the influence on the characteristics is small. Furthermore, as the characteristic length of the high-concentration impurity distribution increases to 10 nm or more, it approaches the conventional structure, so the distribution is set so that the concentration is significantly lower than the peak value at a position away from the peak position by Ts / 2. It is desirable to do.

  FIG. 8 shows the impurity distribution of the source and drain regions in the embodiment of the present invention when the characteristic length (distance from the peak concentration position to the point where the concentration becomes about 0.1 times when Gaussian distribution is assumed) is 5 nm. FIG. 12 is a diagram illustrating an isoimpurity concentration line on the XY plane of FIG. 11. In the description of FIG. 8, the formation region of the isoimpurity concentration line of the impurity distribution in the source and drain regions is shifted to the source region and the drain region in the ± X direction as compared with that in FIG. 4. As a result, an impurity concentration distribution as typified by an isoimpurity concentration line g is obtained. For this reason, the concentration of the electric field at the gate electrode end and at the source region end and the drain region end is suppressed more than in the case of FIG.

  FIG. 9 shows the Y-direction distribution of the impurity distribution in the drain region (or source region) in FIG. It can be seen that the impurity concentration in both side portions is lower than that in the central portion as compared with FIG.

FIG. 10 is a diagram showing the GIDL mitigation effect of the double gate field effect transistor when the source / drain impurity distribution having a characteristic length of 5 nm is used in the present invention.
FIG. 10 shows a simulation result under a bias condition similar to FIG. The reduction effect of GIDL is greater than that in FIG. However, even in a structure where both side portions of the source or drain region have a peak concentration as usual, GIDL is reduced if the characteristic length of the impurity concentration distribution is small.

However, it can be said that the effect of the present invention is greater as in the comparison of the drain current rising characteristics of FIGS. Note that in the source or drain region, the portion sufficiently separated from the end of the gate electrode may be uniformly increased in concentration to further reduce the parasitic resistance.
Furthermore, the present invention can be applied to a so-called fin-type double insulated gate field effect transistor in which the first gate electrode and the second gate electrode are integrally formed, for example, Patent 1875548 “Field Effect Semiconductor Device”, and the same effect can be obtained. Can be obtained.

11 (b) is a diagram for explaining the present invention and the conventional example impurity concentration distribution.
As shown by a dotted line in FIG. 11B, in the conventional double insulated gate field effect transistor , the impurity concentration characteristics of the source region 1 or the drain region 2 are substantially constant in the thickness direction (Y direction). Therefore, a high electric field was generated in the vicinity of the drain region 2 of the channel region 3 at the ends of both gate electrodes 6 and 9, and an increase in drain current (GIDL) was observed due to the band-to-band tunneling phenomenon.

In contrast, in the double insulated gate field effect transistor of the present embodiment, as shown by the solid line in FIG. 11B and as shown in FIGS. The impurity concentration characteristic shows the peak position of the highest concentration in the central portion in the thickness direction (Y direction) of the source region 1 and the drain region 2, and the peak (highest) concentration region in the central portion leads to the gate insulators 5 and 8. It gradually decreases, for example, exponentially toward the contact surface, and reaches a minimum concentration on the surfaces in contact with the gate insulators 5 and 8. Therefore, generation of a high electric field in the vicinity of the drain region 2 of the channel region 3 at the ends of both the gate electrodes 6 and 9 can be suppressed, and hence the GIDL phenomenon can be suppressed .

  The impurity distribution shape in which the concentration peak of the first high-concentration impurity in the source region and the drain region decreases exponentially from the central portion toward both gate electrodes is symmetrical with respect to the central portion. It is preferable to do.

In the figure, there is only one maximum value of concentration, but the point is that it is sufficient to provide a region where the concentration gradually increases as it goes inward from the surface in contact with the gate insulator. For example, there are two maximum values. Even in this case, the GIDL reduction effect can be provided.
Furthermore, the same effect can be obtained even when applied to the structure disclosed in Japanese Patent No. 3543117, that is, the structure in which the thickness of the source and drain regions in the Y direction is thicker than that of the channel region. I can do it.

  The manufacturing method of the structure of the present invention is arbitrary. For example, the impurity distribution shown in the present invention can be formed in the source and drain regions of the present invention by using a conventional ion implantation method. That is, an etching mask for determining the XY cross-sectional shape of the source, channel and drain regions, for example, a thin film made of silicon oxide and a thin film made of silicon nitride are deposited on the channel. Using a material such as polysilicon, whose shape has been determined as an electrode, as a mask for ion implantation, the central part becomes the node peak from the oblique direction toward both sides of the silicon layer that becomes the exposed source and drain regions. This can be realized by adjusting the ion implantation energy and performing ion implantation. A silicon oxide film or the like is deposited in advance on the side surface of the gate electrode or the side surface of the source / drain region, and the position of the concentration peak and the underlap distance can be adjusted.

It is a block diagram of an example of the conventional double insulated gate field effect transistor. It is the schematic which looked at the source region 1, the channel region 3, and the drain region 2 of FIG. 1 in the X direction cross section, and is the conceptual diagram of the underlap structure in the conventional double insulated gate field effect transistor. It is the figure which showed the mitigation effect of the underlap GIDL when the conventional source or drain impurity concentration distribution is applied to the double insulated gate field effect transistor. Source in double-insulated-gate field-effect transistor of the present invention, the impurity concentration line of the impurity concentration distribution of the X-Y plane of the drain region is a diagram obtained by the table. It is the figure which showed the impurity concentration distribution of the YZ cross section of the source | sauce or drain region of the double insulated gate field effect transistor in this invention. It is the figure which showed the impurity concentration distribution of the XZ cross section from the source region which passes along the center part of the channel of the double insulated gate field effect transistor in this invention to a drain region. It is the figure which showed the GIDL mitigation effect of the double insulated gate field effect transistor of this invention. It is the figure which showed the impurity concentration line in 5 nm of characteristic length of the impurity concentration distribution of the source region of the double insulated gate field effect transistor in this invention, and a drain region. It is the figure which showed the impurity concentration distribution in the characteristic length 5nm of the YZ cross section of the source | sauce or drain region of the double insulated gate field effect transistor in this invention. In the present invention, it is the figure which showed the GIDL mitigation effect of the double insulated gate field effect transistor when the source / drain impurity concentration distribution of characteristic length 5nm is used. It is a block diagram of one Embodiment of the double insulated gate field effect transistor of this invention, and a figure explaining the impurity concentration distribution of this invention in the Y direction of a source and a drain region, and a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Source electrode 2 Drain 3 Channel 4 1st surface 5 1st gate insulator 6 1st gate electrode 7 2nd surface 8 2nd gate insulator 9 2nd gate electrode

Claims (2)

A source region and a drain region impure product is introduced at a high concentration, respectively, a channel region is interposed in contact between them source and drain regions, the rectangular parallelepiped portion made from the source region, the drain region and the channel region A film-like first gate insulator provided in contact with one of the opposing surfaces including the same direction as the first direction from the source region toward the drain region, and in contact with the other surface of the opposing surfaces And a first gate and a second gate provided in the second direction perpendicular to the first direction via the first and second gate insulators, respectively. In a double insulated gate field effect transistor having an electrode ,
Density characteristics of the impurities in the source region and the drain region, the concentration of the impurity in the second direction toward the second gate insulator from the first gate insulator, the source region and the The lower the distance from the inside of the drain region to the surfaces in contact with the first and second gate insulators, the highest concentration end positions of the impurities in the source region and the drain region are In the first direction toward the drain region, the second gate electrode and the second gate electrode are located away from the channel region corresponding to the end portions of the first gate electrode and the second gate electrode. Heavy insulated gate field effect transistor. Dark Dotoku of the source region and the drain region is in the second direction toward the second gate insulator from the first gate insulator, the center of the interior of the source region and the drain region double-insulated-gate field-effect transistor of claim 1, wherein the peak of maximum concentration was the characteristic located part.

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