JP2005033008A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of decreasing a contact resistance without decreasing a throughput and preventing the occurrence of cracks. <P>SOLUTION: The method for manufacturing the semiconductor device has a line pattern 17, alignment patterns 8a to 8c, auxiliary patterns such as marks 15a, 15b for inspection, and a contact 7. Further, the method comprises the steps of forming interlayer insulating layers 9a to 9c on the semiconductor substrate 10, opening the contact holes 14a to 14d for forming the conatct 7 in the layers 9a to 9c, injecting an imputiry on the substrate 10 through the holes 14a to 14d, heating the subtrate 10 to electrically activate the injected impurity, and after the heating, opening grooves 14e to 14f for forming the auxiliary pattern in the layers 9a to 9c. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of preventing the occurrence of cracks.
[0002]
[Prior art]
In the manufacture of a semiconductor device, elements, wirings, and the like are formed by performing predetermined processing on the surface of a wafer in the state of a semiconductor substrate (wafer). When all the processes to be performed in the state of the wafer are completed, the wafer is diced along dicing lines and cut out as individual semiconductor chips.
[0003]
For this reason, the semiconductor substrate before being cut out as individual semiconductor chips has a semiconductor chip region that becomes a semiconductor chip after being diced, and a dicing line region that becomes a margin for dicing. A wiring pattern or the like is formed in the semiconductor chip region, and an auxiliary pattern is formed in the dicing line region. Here, the auxiliary pattern is a line pattern formed along a dicing line, an alignment pattern at the time of photolithography, an inspection symbol, and the like. Conventionally, these wiring patterns and auxiliary patterns have been formed by the following method.
[0004]
First, an interlayer insulating layer is formed on a semiconductor substrate. Then, a contact hole is opened in the interlayer insulating layer in the semiconductor chip region by a normal photolithography technique and etching technique. As a result, the semiconductor substrate is exposed at the bottom of the contact hole. Further, a groove for forming an auxiliary pattern is opened in the interlayer insulating layer in the dicing line region by the same process as that for forming the contact hole. Next, impurities are implanted into the surface of the semiconductor substrate through the contact holes. Subsequently, the semiconductor substrate is heated. As a result, the impurity atoms implanted into the surface of the semiconductor substrate move to a stable position in the crystal lattice of the semiconductor substrate, become electrically active, and generate carriers. Then, a barrier metal layer and a conductive layer are formed by CVD (Chemical Vapor Deposition) or the like so as to fill in the contact hole and the groove, and an extra barrier metal layer and conductive layer on the interlayer insulating layer are formed by CMP (Chemical Mechanical Polish). Removed by law. As a result, a contact is formed in the contact hole portion, and an auxiliary pattern is formed in the groove portion. At this time, as a result of the ohmic contact between the impurity-implanted region and the barrier metal layer formed in the contact hole, the contact resistance is reduced. Subsequently, a conductive layer is laminated on the interlayer insulating layer, and a wiring pattern is formed on a portion where the contact is formed by a normal photolithography technique and etching technique. At the same time, a conductive layer is formed on the conductive layer filling the trench, thereby forming an auxiliary pattern.
[0005]
Japanese Patent Laid-Open No. 2002-299203 (Patent Document 1) discloses a solution to the problem that a crack occurs in a mask dimension mark formed in each interlayer film due to a stress generated between the stacked interlayer films. Is described.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-299203
[Problems to be solved by the invention]
In a conventional method of manufacturing a semiconductor device, after a contact hole and a groove for forming an auxiliary pattern are formed in an interlayer insulating layer, heating for electrically activating implanted impurities is performed. It is. This heating is usually performed at 750 ° C. or higher. For this reason, the interlayer insulating layer expands and contracts due to heat, and thermal stress is generated in the interlayer insulating layer. As a result, there is a problem that a crack is generated in the groove in which the auxiliary pattern is formed. When the crack generated in the groove extends to the semiconductor chip region, a defect occurs in the semiconductor chip. Furthermore, if the barrier metal layer and the conductive layer are buried in the crack extending to the wiring pattern in the semiconductor chip region by a subsequent process, there is a problem that a short circuit occurs between the wiring pattern and the auxiliary pattern.
[0008]
Here, in order to suppress the occurrence of cracks in the groove, a method of lowering the heating temperature below 750 degrees is also conceivable. However, if the heating temperature is lowered, it becomes difficult for the impurity atoms to move to a stable position on the lattice of the semiconductor substrate (it is difficult to become electrically active), so the region into which the impurity is implanted and the barrier metal layer are in ohmic contact. No longer. Therefore, if the impurity implantation amount is increased in order to reduce the contact resistance, the time for implanting the impurity increases, resulting in a significant decrease in throughput.
[0009]
The method described in Patent Document 1 increases the area where the lower interlayer film and the mask dimension mark are in contact with each other by changing the position where the mask dimension mark is formed depending on each interlayer film. The stress generated between the lower interlayer film and the mask dimension inspection mark is suppressed, and the generation of cracks is suppressed. In this method, since the mask dimension detection mark is still affected by the thermal stress of the interlayer film, it is considered that the generation of cracks cannot be sufficiently suppressed.
[0010]
Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce contact resistance without reducing throughput and that can prevent the occurrence of cracks.
[0011]
[Means for Solving the Problems]
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an auxiliary pattern and a contact, and includes a step of forming an insulating layer on a semiconductor substrate, and a contact hole for forming the contact in the insulating layer. A step of opening the semiconductor substrate, injecting impurities into the surface of the semiconductor substrate through the contact holes, a heating step of heating the semiconductor substrate to electrically activate the impurities, and forming an auxiliary pattern after the heating step And a step of opening a groove for opening in the insulating layer.
[0012]
In this specification, a contact is a conductive layer having a circular shape or a plane shape close to a circular shape for electrically connecting an impurity region formed on the surface of a semiconductor substrate and a conductive layer formed on an insulating layer. Means. Further, in this specification, the auxiliary pattern means a layer formed for the purpose other than electrical connection, for example, a line pattern formed along a dicing line, an alignment pattern at the time of photolithography. And a symbol for inspection.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
[0015]
Referring to FIG. 1, in the semiconductor device of the present embodiment, wiring pattern 2 is formed in semiconductor chip region 18 surrounded by line pattern 17. Each of the conductive layers 20a to 20d constituting the wiring pattern 2 extends in the vertical direction in the drawing, and electrically connects each of the contacts 7. The pitch d ₁ between the contacts 7 is, for example, 0.3 μm to 0.8 μm, and the diameter d _{2 of the} contact 7 is, for example, 0.20 μm to 0.40 μm. A region other than the semiconductor chip region 18 is a dicing line region 19, and the semiconductor substrate (wafer) is diced along the dicing line region 19. In the dicing line area 19, for example, alignment patterns 8 a to 8 c at the time of photolithography having a planar shape such as a rectangle or three lines, or inspection symbols 15 a and 15 b having a planar shape such as a cross or a number, for example. An auxiliary pattern such as is formed.
[0016]
FIG. 2 is a sectional view taken along line II-II in FIG.
Referring to FIG. 2, n channel MOS transistor 11 and p channel MOS transistor 12 are formed on the surface of semiconductor substrate 10 electrically isolated by field oxide film 13. N channel MOS transistor 11 has n type diffusion regions 3a and 3b, a gate insulating layer 11b, and a gate electrode layer 11c. The n-type diffusion regions 3a and 3b have an LDD (Lightly Doped Drain) structure and are arranged at a predetermined distance from each other. Each of n ⁺ diffusion regions 4a and 4b is formed inside each of n-type diffusion regions 3a and 3b. The gate electrode layer 11c is formed on the region sandwiched between the n-type diffusion regions 3a and 3b via the gate insulating layer 11b. The periphery of the gate electrode layer 11c is covered with an insulating layer 11a and a salicide layer 11d. The salicide layer 11d is formed to reduce the resistance of the gate electrode layer 11c and the n-type diffusion regions 3a and 3b.
[0017]
Similarly, the p-channel MOS transistor 12 has p-type diffusion regions 3c and 3d, a gate insulating layer 12b, and a gate electrode layer 12c. The p-type diffusion regions 3c and 3d have an LDD structure and are arranged at a predetermined distance from each other. Each of p ⁺ diffusion regions 4c and 4d is formed inside each of p-type diffusion regions 3c and 3d. The gate electrode layer 12c is formed on the region sandwiched between the p-type diffusion regions 3c and 3d via the gate insulating layer 12b. The periphery of the gate electrode layer 12c is covered with an insulating layer 12a and a salicide layer 12d.
[0018]
Interlayer insulating layer 9a is formed on semiconductor substrate 10 so as to cover n channel MOS transistor 11 and p channel MOS transistor 12, and interlayer insulating layer 9b and interlayer insulating layer 9c are formed thereon. Interlayer insulating layers 9 a to 9 c have contact holes 14 a and 14 b reaching each of n ⁺ diffusion regions 4 a and 4 b, contact holes 14 c and 14 d reaching each of p ⁺ diffusion regions 4 c and 4 d, and semiconductor substrate 10. Grooves 14e and 14f are opened. Barrier metal layers 5a-5f and conductive layers 6a-6f are buried in contact holes 14a-14d and grooves 14e, 14f, respectively. Thereby, a contact 7 is formed in each of the holes 14a to 14d. Conductive layers 20a to 20d are formed on the barrier metal layers 5a to 5d and the conductive layers 6a to 6d, respectively. The conductive layer 20a to 20d constitutes the wiring pattern 2. A conductive layer 20e is formed on the barrier metal layer 5e and the conductive layer 6e. A line pattern 17 is constituted by the barrier metal layer 5e, the conductive layer 6e, and the conductive layer 20e. Furthermore, a conductive layer 20f is formed on the barrier metal layer 5f and the conductive layer 6f. The alignment pattern 8a is constituted by the barrier metal layer 5f, the conductive layer 6f, and the conductive layer 20f.
[0019]
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.
3 to 9 are cross-sectional views showing a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of steps.
[0020]
Referring to FIG. 3, n channel MOS transistor 11 and p channel MOS transistor 12 are formed on the surface of semiconductor substrate 10 made of, for example, silicon as follows. That is, a layer to be gate insulating layers 11b and 12b made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 10, and a layer to be the gate electrode layers 11c and 12c and a salicide layer 11d and 12d are formed on this layer. After the layers are formed by lamination, they are patterned by a normal photolithography technique and etching technique. As a result, layers that become the gate insulating layers 11b and 12b, the gate electrode layers 11c and 12c, and the salicide layers 11d and 12d are formed. The gate electrode layers 11c and 12c are made of, for example, a polycrystalline silicon layer into which impurities are introduced. By implanting impurities into the semiconductor substrate 10 using the gate electrode layers 11c and 12c as a mask, relatively low concentration n-type diffusion regions 3a and 3b and p-type diffusion regions 3c and 3d are formed.
[0021]
Sidewall spacer-like insulating layers 11a and 12a made of, for example, a silicon oxide film are formed so as to cover the side walls of the gate electrode layers 11c and 12c. Thereafter, by implanting impurities onto the semiconductor substrate 10 using the gate electrode layers 11c and 12c and the insulating layers 11a and 12a as a mask, relatively high concentration n-type diffusion regions 3a and 3b and p-type diffusion regions 3c, 3d is formed. The relatively high concentration impurity region and the above-described relatively low concentration impurity region form n-type diffusion regions 3a and 3b and p-type diffusion regions 3c and 3d having an LDD structure. As described above, n channel MOS transistor 11 and p channel MOS transistor 12 are formed.
[0022]
Referring to FIG. 4, interlayer insulating layers 9 a to 9 c are formed so as to cover n channel MOS transistor 11, p channel MOS transistor 12 and field oxide film 13 thus formed. The interlayer insulating layer 9a is made of, for example, PTEOS (Phospho Tetra Ethyl Ortho Silicate). PTEOS is a silicon oxide film formed to have P (phosphorus) using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. The interlayer insulating layer 9b is made of, for example, BPTEOS, PSG (Phospho Silicate Glass), or TEOS. BPTEOS is a silicon oxide film formed so as to have B (boron) and P using TEOS as a raw material. Interlayer insulating layer 9c is made of, for example, PTEOS or PSiO. PSiO is SiO (silicon oxide) formed by plasma CVD. Interlayer insulating layer 9a is stacked with a thickness of, for example, 30 to 100 nm, interlayer insulating layer 9b is stacked with a thickness of, for example, 200 to 800 nm, and interlayer insulating layer 9c is stacked with a thickness of, for example, 100 to 400 nm. . Next, the photoresist 16 is patterned on the interlayer insulating layer 9c so as to cover portions other than the portions where the contact holes 14a to 14d are opened.
[0023]
Referring to FIG. 5, contact holes 14a-14d are opened by etching interlayer insulating layers 9a-9c using photoresist 16 as a mask. After the photoresist 16 is removed and the contact holes 14a to 14d are cleaned, impurities such as P and Sb (antimony) are ion-implanted into the semiconductor substrate 10 through the contact holes 14a and 14b. Thus, n ⁺ diffusion regions 4 a and 4 b are formed on the surface of the semiconductor substrate 10. Further, impurities such as B (boron) and BF ₂ (boron fluoride) are ion-implanted into the semiconductor substrate 10 through the contact holes 14c and 14d, whereby the p ⁺ diffusion region 4c, 4d is formed. Subsequently, the semiconductor substrate 10 is heated to, for example, 750 degrees. As a result, the impurity atoms implanted into the surface of the semiconductor substrate 10 move to a stable position in the crystal lattice in the semiconductor substrate 10 and become electrically active, generating carriers.
[0024]
Referring to FIG. 6, the photoresist is formed on interlayer insulating layer 9c so as to cover the portion other than the portion where groove 14e for forming line pattern 17 and groove 14f for forming alignment pattern 8a are opened. The interlayer insulating layers 9a to 9c are etched using the photoresist as a mask to open the grooves 14e and 14f. Then, the photoresist is removed, and the inside of the grooves 14e and 14f is cleaned. In addition, although two grooves 14f are shown in the right part in FIG. 6, referring to FIG. 1, this has a planar shape in which the alignment pattern 8a goes around along a rectangular side. Because. That is, these two grooves 14f are connected.
[0025]
Referring to FIG. 7, barrier metal layer 5 and conductive layer 6 are formed so as to cover the side walls and bottom portions of contact holes 14a-14d and grooves 14e, 14f and the upper portion of interlayer insulating layer 9c. Barrier metal layer 5 is made of, for example, TiN (titanium nitride), and conductive layer 6 is made of, for example, W (tungsten). The barrier metal layer 5 and the conductive layer 6 are formed by forming a film by, for example, a CVD method or a sputtering method.
[0026]
Referring to FIG. 8, barrier metal layer 5 and conductive layer 6 located above interlayer insulating layer 9c are removed by, eg, CMP. Thereby, barrier metal layers 5a-5f and conductive layers 6a-6f are formed. Here, in FIG. 5, since the impurity implanted into the surface of the semiconductor substrate 10 is active, the n ⁺ diffusion regions 4a and 4b and the p ⁺ diffusion regions 4c and 4d and the barrier metal layers 5a to 5d are ohmic. Contact. Thereby, the contact resistance can be reduced.
[0027]
Referring to FIG. 9, conductive layer 20 is formed to cover barrier metal layers 5a-5f, conductive layers 6a-6f, and interlayer insulating layer 9c. Conductive layer 20 is formed by depositing Al (aluminum) by sputtering, for example.
[0028]
Referring to FIG. 2, a photoresist is patterned on conductive layer 20, and conductive layer 20 is etched using this photoresist as a mask, thereby forming conductive layers 20a to 20f and removing the photoresist. Of the conductive layers 20a to 20f, the wiring pattern 2 is configured by the conductive layers 20a to 20d. Further, the line pattern 17 is constituted by the conductive layer 20e, the barrier metal layer 5e, and the conductive layer 6e. Furthermore, alignment pattern 8a is constituted by conductive layer 20f, barrier metal layer 5f, and conductive layer 6f. With the above method, the semiconductor device in the present embodiment is manufactured.
[0029]
Here, in the conventional semiconductor device, it is presumed that the crack is generated by the following principle. FIG. 10 is a plan view schematically showing a conventional semiconductor device.
[0030]
Referring to FIG. 10, a wiring pattern 22, a line pattern 24, and an alignment pattern 25 in a conventional semiconductor device are schematically shown. Cracks 26 a are generated at the corners of the line pattern 24. In addition, cracks 26 b are generated at the corners of the alignment pattern 25. The cracks 26 a and 26 b reach the wiring pattern 22. Such cracks 26a and 26b become defects in the semiconductor chip. Further, when the barrier metal layer 4 and the conductive layer 5 are formed, if the barrier metal layer 4 and the conductive layer 5 are embedded in the cracks 26 a and 26 b, the space between the wiring pattern 22, the line pattern 24, and the alignment pattern 25. It will be shorted.
[0031]
FIGS. 11A to 11C are schematic diagrams for explaining the principle of occurrence of cracks. Referring to FIG. 11A, when the semiconductor substrate is heated to electrically activate the impurity atoms implanted into the surface of the semiconductor substrate, the interlayer insulating layer expands and contracts due to heat, and the interlayer insulating layer is heated. Thermal stress is generated in the layer. Accordingly, it is considered that tensile forces in the vertical direction and the horizontal direction in the drawing are applied to the grooves 29 in which the line patterns 24 are formed. When such a tensile force is applied to the groove 29, the tensile force in the vertical direction and the horizontal direction is concentratedly applied to the corner portion 29a of the groove 29. As a result, it is presumed that cracks 26 a are generated at the corners 29 a of the grooves 29.
[0032]
Similarly, referring to FIG. 11B, since the tensile force in the vertical and horizontal directions is concentrated on the corner 27a of the groove 27 where the alignment pattern 25 is formed, the corner of the groove 27 is It is estimated that the crack 26b occurs in the portion 27a.
[0033]
On the other hand, referring to FIG. 11C, the contact hole 23a in which the contact 23 is formed has a circular planar shape. It is considered that the contact hole 23a receives a uniform tensile force in all directions due to the thermal stress generated in the interlayer insulating layer. As a result, since there is no portion where the tensile force is concentrated, it is presumed that no cracks are generated in the contact hole 23a.
[0034]
Therefore, the inventors of the present application provide auxiliary patterns such as line patterns, alignment patterns, and inspection symbols after the step of heating the semiconductor substrate to electrically activate the impurities implanted into the surface of the semiconductor substrate. It has been found that if the grooves for forming the openings are opened, it is possible to prevent the generation of cracks in the grooves for forming the auxiliary pattern.
[0035]
According to the method for manufacturing the semiconductor device of the present embodiment, after the grooves 14e and 14f for forming the auxiliary patterns are formed in the interlayer insulating layers 9a to 9c, the impurities are electrically activated. There is no heating. For this reason, the thermal stress generated in the interlayer insulating layers 9a to 9c is not applied to the grooves 14e and 14f due to the heating for electrically activating the impurities, so that the grooves 14e and 14f are prevented from being cracked. Is done. Further, when heating the semiconductor substrate 10 to electrically activate the impurities, it is not necessary to lower the heating temperature in order to suppress the generation of cracks, so that the contact resistance can be reduced without reducing the throughput. Can be small.
[0036]
The method for manufacturing a semiconductor device according to the present embodiment further includes a step of filling contact holes 14a to 14d and grooves 14e and 14f with barrier metal layer 5 and conductive layer 6.
[0037]
As a result, the barrier metal layer 5 and the conductive layer 6 are not embedded in the crack, so that the problem of short-circuiting between the wiring pattern 2 and the auxiliary pattern such as the alignment pattern 5b is prevented.
[0038]
In the method of manufacturing a semiconductor device in the present embodiment, the insulating layer on the semiconductor substrate 10 is composed of a plurality of interlayer insulating layers 9a to 9c.
[0039]
When the insulating layer on the semiconductor substrate is composed of a plurality of insulating layers, cracks are particularly likely to occur between the insulating layers due to the difference in thermal expansion coefficient between the insulating layers. However, according to the method of manufacturing a semiconductor device in the present embodiment, the generation of cracks can be prevented, and therefore, interlayer insulating layers 9a to 9c corresponding to the respective suitability are laminated without considering the generation of cracks. be able to.
[0040]
In the present embodiment, a method for manufacturing the contact 7 for electrically connecting the impurity region formed in the semiconductor substrate 10 and the wiring pattern 2 formed on the interlayer insulating layer 9c is shown. . However, in an actual semiconductor device, for example, a contact for electrically connecting a base electrode of a transistor and a wiring pattern also exists. The contact holes for forming such contacts may be opened simultaneously with the contact holes 14a to 14d in the present embodiment, or may be opened simultaneously with the grooves 14e and 14f.
[0041]
In the present embodiment, the case where the n-channel MOS transistor 11 and the p-channel MOS transistor 12 are formed has been described. However, the present invention is limited to the method of manufacturing the semiconductor device having such a configuration. Instead, the present invention can be applied to a manufacturing method for semiconductor devices having auxiliary patterns and contacts.
[0042]
The embodiment disclosed above should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above embodiments but by the scope of claims, and is intended to include all modifications and variations within the scope and meaning equivalent to the scope of claims.
[0043]
【The invention's effect】
As described above, according to the method for manufacturing a semiconductor device of the present invention, after the trench for forming the auxiliary pattern is formed in the interlayer insulating layer, heating for electrically activating the impurity is performed. I can't. For this reason, since the thermal stress generated in the interlayer insulating layer due to the heating for electrically activating the impurities is not applied to the groove, the generation of cracks in the groove is prevented. Further, when heating the semiconductor substrate to electrically activate the impurities, it is not necessary to lower the heating temperature in order to suppress the occurrence of cracks, so that the contact resistance is reduced without reducing the throughput. can do.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
FIG. 3 is a cross-sectional view showing a first step of a method of manufacturing a semiconductor device in an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a second step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 5 is a cross sectional view showing a third step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a sixth step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a seventh step of the method of manufacturing a semiconductor device in one embodiment of the present invention.
FIG. 10 is a plan view schematically showing a conventional semiconductor device.
FIG. 11A is a schematic diagram for explaining the principle that cracks occur in a line pattern. (B) It is a schematic diagram for demonstrating the principle that a crack generate | occur | produces in the alignment pattern. (C) It is a schematic diagram for demonstrating the principle which a crack does not generate | occur | produce in a contact hole.
[Explanation of symbols]
2,22 wiring pattern, 3a, 3b n-type diffusion region, 3c, 3d p-type diffusion region, 4a, 4b n ⁺ diffusion region, 4c, 4d p ⁺ diffusion region, 5a to 5f barrier metal layer, 6a to 6f conductive layer 7, 23 contacts, 8a-8c, 25 alignment pattern, 9a-9c interlayer insulation layer, 10 semiconductor substrate, 11 n-channel MOS transistor, 11a, 12a insulation layer, 11b, 12b gate insulation layer, 11c, 12c gate electrode Layer, 11d, 12d salicide layer, 12p channel MOS transistor, 13 field oxide film, 14a-14d, 23a contact hole, 14e, 14f, 27, 29 groove, 15a, 15b inspection symbol, 16 photoresist, 17, 24 lines Pattern, 18 Semiconductor chip area, 19 Dicing line area, 20, 2 0a to 20f conductive layer, 26a, 26b crack, 27a, 29a corners.

Claims (3)

A method of manufacturing a semiconductor device comprising an auxiliary pattern and a contact,
Forming an insulating layer on the semiconductor substrate;
Opening a contact hole in the insulating layer for forming the contact;
Injecting impurities into the semiconductor substrate surface through the contact holes;
A heating step of heating the semiconductor substrate to electrically activate the impurities;
And a step of opening a groove for forming the auxiliary pattern in the insulating layer after the heating step. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of filling the contact hole and the groove with a conductive layer. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer includes a plurality of layers.

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