JP2004319592A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can suppress the fall of an on-current, an increase in junction leak, the variation of characteristics of a transistor caused by the abnormal growth of a metal silicide film, and so on, and to provide a method of manufacturing the device. <P>SOLUTION: After a source/drain region 4 is formed in a p-type MOS region by using a p-type impurity, an Ni monosilicide film 5 having highly uniform film quality and a film thickness is formed in a region in which an Ni silicide film is formed by suppressing the phase transition and agglomeration of an Ni silicide by injecting Ge into the region. Consequently, the occurrence of a junction leak can be suppressed by increasing the on-current by reducing parasitic resistance and improving the flatness of the Ni silicide film. In addition, the deterioration of a gate insulating film or the retreat of a diffusion layer is suppressed by improving the uniformity of gate resistance by improving the uniformity of characteristics of p- and n-type MOSs by equally controlling silicide reactions of the MOSs and in addition, suppressing the abnormal growth of a gate electrode or the Ni silicide film at the end of the source/drain region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which a metal silicide film is formed near the surface of a gate electrode and source and drain regions and a method of manufacturing the same.
[0002]
[Prior art]
With the miniaturization of semiconductor devices, a problem arises in that the so-called short channel effect caused by the spread of a depletion layer in the channel direction around the drain diffusion region increases the leakage current when the transistor is off. In order to suppress this short channel effect, an offset gate layer having a low impurity concentration is conventionally formed between a gate and a source / drain region (hereinafter, referred to as a source / drain region) to provide a gradient in the impurity concentration. (Lightly Doped Drain) structure is widely used. In order to cope with further miniaturization of semiconductor devices, there is also a structure in which source and drain regions are formed shallow near the substrate surface. In this structure, since the sheet resistance of the impurity diffusion layer increases, A metal silicide film, which is a compound of silicon and a metal, is partially formed to reduce parasitic resistance.
[0003]
Here, a method of manufacturing a general MOS transistor having a metal silicide film near the surface of the gate electrode and the source / drain regions will be described with reference to FIGS. First, as shown in FIG. 13A, an element isolation insulating film 2 is formed on a semiconductor substrate 1 by using a LOCOS method, a trench method, or the like. Next, a P-type impurity and an N-type impurity are implanted into each region partitioned by the element isolation insulating film 2 to form a P-well region 3a and an N-well region 3b. Then, after a gate insulating film 8 made of a silicon oxide film is formed by a thermal oxidation method or the like, polysilicon is deposited by a low pressure CVD method or the like, and a gate electrode 9 is formed by a known photolithography technique and a dry etching technique. Form.
[0004]
Next, as shown in FIG. 13B, a low concentration N-type impurity such as phosphorus (P) or arsenic (As) is implanted into the N-MOS region by ion implantation using the gate electrode 9 as a mask. Low concentration boron (B) or BF in the MOS region ₂ The LDD region 7 is formed by implanting a P-type impurity such as Next, as shown in FIG. 13C, a silicon oxide film is deposited on the entire surface of the substrate by a low pressure CVD method or the like, and the silicon oxide film is etched back by anisotropic dry etching. The wall 10 is formed. Then, as shown in FIG. 14A, using the gate electrode 9 and the side wall 10 as a mask, a high-concentration N-type impurity such as P or As is applied to the N-MOS region and a high-concentration B Or BF ₂ Then, a source / drain region 4 is formed by implanting a P-type impurity or the like and performing an activation heat treatment of the implanted impurity.
[0005]
Next, as shown in FIG. 14B, a metal film 14 of Ti, Co, or the like is deposited on the entire surface of the substrate, and the metal film 14 reacts with silicon near the surface of the gate electrode 9 and the source / drain region 4 by heat treatment. Thus, a metal silicide film 15 is formed. Next, as shown in FIG. 14 (c), the unreacted metal film 14 is removed by wet etching, and thereafter, an insulating film such as a silicon oxide film is deposited, and the gate electrode 9 and the source / drain region 4 are formed. A contact is formed, a predetermined wiring is formed, and a semiconductor device is completed.
[0006]
In the semiconductor device having the above structure, the characteristics of the semiconductor device fluctuate depending on the state of the metal silicide film 15. Therefore, it is required to form the metal silicide film 15 having a low resistance and a uniform thickness with a uniform thickness. It is important to use various kinds of metals and to form the metal silicide film 15 under what conditions. For example, when Ti is used as the metal film 14, there is a problem that a temperature at which a silicide reaction occurs is high. In recent years, attention has been paid to Ni which can form the metal silicide film 15 at a low temperature.
[0007]
However, when Ni is used, there is a problem that unevenness is likely to occur at the interface between the Ni silicide film and the substrate. Therefore, Japanese Patent Application Laid-Open No. 7-38104 discloses a method for forming a concave-convex insulating film by reacting a metal film with oxygen to form an insulating film having at least one of Ni, Co and Pt. A step of forming a first film, a step of depositing a second film made of a metal compound on the first metal film, and a step of annealing a silicon substrate to cause a reaction between the first metal and silicon to form a film on the gate electrode. Forming a metal silicide on a diffusion layer serving as a source and a drain, and removing an unreacted first film and a second film on the first film. Is disclosed.
[0008]
As described in the above publication, when forming a Ni silicide film on a diffusion layer, an insulating film made of Ni and oxygen is formed, the Ni silicide film becomes uneven, and the resistance on the diffusion layer only increases. However, there is a problem that a part of the Ni silicide film penetrates through the diffusion layer, thereby causing a junction leak. However, in the above-described method, since the second film made of the metal compound is formed on Ni, the silicide reaction occurs. It is stated that the reaction between Ni and oxygen is suppressed during the annealing for the above, and the problem that an uneven insulating film is formed can be avoided.
[0009]
[Patent Document 1]
JP-A-7-38104 (page 4-5, FIG. 1)
[0010]
[Problems to be solved by the invention]
However, the problem when Ni is used as the metal film is not only the problem of the reaction between Ni and oxygen but also the problem of the structure of the Ni silicide film itself. That is, the Ni silicide film is not a film having a single structure, ₂ Si, NiSi, NiSi ₂ There are three types of structures, which are Ni → Ni with increasing temperature. ₂ Si → NiSi → NiSi ₂ It is known that a phase transition occurs. Among the above structures, NiSi (hereinafter referred to as Ni monosilicide) is a low-resistance and flat film. ₂ (Hereinafter, referred to as Ni disilicide) is a film having a higher specific resistance and a larger irregularity than Ni monosilicide. Also, NiSi → NiSi ₂ It is known that phase transition does not occur during the transition of NiSi, but there is a process in which NiSi aggregates, and this aggregation also causes unevenness.
[0011]
Therefore, when forming a Ni silicide film, the reaction must be controlled so that a uniform Ni monosilicide is formed with a uniform film thickness, but the critical temperature at which phase transition occurs depends on the state of the base (for example, (The amount of impurities, impurity species, crystal state, etc.). Therefore, it is difficult to form low-resistance, small-uniform Ni monosilicide for both the P-MOS transistor and the N-MOS transistor having different impurity amounts and impurity types.
[0012]
For example, if the silicide reaction is controlled on the basis of the N-MOS transistor into which As is implanted, the silicide reaction is promoted in the P-MOS transistor, and the Ni disilicide is formed deep as shown on the left side of FIG. As a result, the parasitic resistance of the P-MOS transistor increases, and the on-current of the transistor decreases. In addition, since Ni disilicide is a film having large irregularities, Si in the source / drain region 4 is partially eroded in some cases, causing a problem that junction leakage increases.
[0013]
In addition, if the structure and thickness of the Ni silicide film become non-uniform on the gate electrode, the resistance also varies. If the Ni silicide film further grows abnormally, the Ni silicide film reaches the gate insulating film and Ni is diffused. Deteriorates. If the abnormal growth occurs at the end of the source / drain region 4 (for example, at the boundary between the source / drain region 4 and the sidewall 10), the diffusion layer recedes, and the transistor characteristics fluctuate. Such a problem is prominent in a fine semiconductor device having a narrow gate electrode.
[0014]
The present invention has been made in view of the above problems, and a main object of the present invention is to increase parasitic resistance in a semiconductor device having a structure in which a metal silicide film is formed near the surfaces of a gate electrode and source / drain regions. To provide a semiconductor device and a method for manufacturing the same, which can suppress a decrease in on-current due to the above, increase in junction leak due to unevenness of the metal silicide film, fluctuation in transistor characteristics due to abnormal growth of the metal silicide film, and the like. .
[0015]
[Means to solve the problem]
In order to achieve the above object, a semiconductor device according to the present invention includes a first impurity diffusion region formed in a self-aligned manner with respect to a gate electrode, a sidewall insulating film provided on the gate electrode and a side wall of the gate electrode. A semiconductor device comprising at least a second impurity diffusion region formed in a self-aligned manner with respect to the gate electrode and a metal silicide film formed near the surface of the gate electrode and the second impurity diffusion region. Ge is implanted in a region where the film is formed.
[0016]
Further, the semiconductor device of the present invention is characterized in that the first impurity diffusion region formed in a self-aligned manner with respect to the gate electrode is self-aligned with the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode. A semiconductor including a P-MOS transistor and an N-MOS transistor including at least a second impurity diffusion region formed in a static manner, and a metal silicide film formed near the surface of the gate electrode and the second impurity diffusion region. In the device, the second impurity diffusion region of the N-MOS transistor is formed by implanting an N-type impurity containing As or As, and in a region where the metal silicide film of the P-MOS transistor is formed, Ge is implanted.
[0017]
Further, the semiconductor device of the present invention is characterized in that the first impurity diffusion region formed in a self-aligned manner with respect to the gate electrode is self-aligned with the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode. A semiconductor including a P-MOS transistor and an N-MOS transistor including at least a second impurity diffusion region formed in a static manner, and a metal silicide film formed near the surface of the gate electrode and the second impurity diffusion region. In the device, the second impurity diffusion region of the N-MOS transistor is formed by implanting P-type or N-type impurities including P, and the metal silicide films of the P-MOS transistor and the N-MOS transistor are formed. Ge is implanted in a region to be formed.
[0018]
In the present invention, the Ge may be implanted to a position deeper than the metal silicide film, and the Ge has an implantation energy of about 5 KeV and an implantation dose of about 1E15 to 3E15 cm. ^-2 It is preferable to perform the injection under the following conditions.
[0019]
In the present invention, it is preferable that the metal silicide film is a monosilicide film formed using Ni or Pt.
[0020]
Further, in the manufacturing method of the present invention, a step of forming a first impurity diffusion region using a gate electrode as a mask, and a step of forming a second impurity diffusion region using the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode as a mask Forming a region, implanting Ge into the gate electrode and the second impurity diffusion region, and forming a metal silicide film near the surface of the gate electrode and the second impurity diffusion region. At least it has.
[0021]
The manufacturing method according to the present invention is a method for manufacturing a semiconductor device including a P-MOS transistor and an N-MOS transistor, wherein an N-type impurity is implanted into the N-MOS transistor formation region using a gate electrode as a mask. Forming a first impurity diffusion region by injecting a P-type impurity into the P-MOS transistor formation region; and forming the first impurity diffusion region by using the gate electrode and a sidewall insulating film provided on sidewalls of the gate electrode as a mask. Implanting As or an N-type impurity containing As into a MOS transistor formation region and implanting a P-type impurity into the P-MOS transistor formation region to form a second impurity diffusion region; Implanting Ge into the gate electrode and the second impurity diffusion region in the formation region; In the vicinity of the surface region and the gate electrode and the second impurity diffusion region of the N-MOS transistor forming region, and has at least a step of forming a metal silicide film.
[0022]
The manufacturing method according to the present invention is a method for manufacturing a semiconductor device including a P-MOS transistor and an N-MOS transistor, wherein an N-type impurity is implanted into the N-MOS transistor formation region using a gate electrode as a mask. Forming a first impurity diffusion region by injecting a P-type impurity into the P-MOS transistor formation region; and forming the first impurity diffusion region by using the gate electrode and a sidewall insulating film provided on sidewalls of the gate electrode as a mask. Implanting an N-type impurity containing P or P into a MOS transistor formation region and implanting a P-type impurity into the P-MOS transistor formation region to form a second impurity diffusion region; Injecting Ge into the gate electrode and the second impurity diffusion region of the formation region and the N-MOS transistor formation region When, in the vicinity of the surface of the P-MOS transistor forming region and the gate electrode and the second impurity diffusion region of the N-MOS transistor forming region, and has at least a step of forming a metal silicide film.
[0023]
As described above, the present invention relates to B or BF ₂ After the source and drain regions are formed in the P-MOS transistor by implanting P-type impurities such as Ge, a Ge is implanted into a region where a metal silicide film (for example, a Ni silicide film) is formed under predetermined implantation conditions. By suppressing the phase transition and aggregation of Ni silicide, it is possible to form a Ni monosilicide film having excellent film quality and film thickness uniformity, thereby reducing parasitic resistance and increasing on-current. In addition, the flatness of the junction interface of the Ni silicide film can be improved, and the junction leakage can be suppressed.
[0024]
Further, by injecting Ge into the P-MOS transistor, the silicide reaction between the P-MOS transistor and the N-MOS transistor into which As has been implanted can be controlled equally. -Uniformity of characteristics of a semiconductor device in which MOS transistors are mixed can be improved.
[0025]
Further, due to the effect of suppressing the silicide reaction by Ge, abnormal growth of the Ni silicide film at the end of the gate electrode or the source / drain region can be suppressed, thereby increasing the uniformity of the gate resistance and deteriorating the gate insulating film. And the retreat of the diffusion layer can be suppressed.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
As described in the related art, a silicide film is formed to reduce the sheet resistance of the diffusion layer. However, when Ni is used as a metal for silicidation, the parasitic resistance increases when Ni disilicide is formed. As a result, there arises a problem that the on-state current of the transistor is reduced, and that the Ni silicide film penetrates the diffusion layer due to the unevenness of the Ni disilicide, thereby increasing the junction leakage.
[0027]
Therefore, it is necessary to control the silicide reaction so that Ni monosilicide is formed. This phase transition and aggregation are caused not only by the temperature but also by the amount of impurities, the kind of impurities, the crystal state, and the stress caused by the structure of the semiconductor device. Change. For example, the amount and type of impurities implanted in the source / drain regions differ between an N-MOS transistor and a P-MOS transistor. As a result, a difference occurs in the silicide reaction between the N-MOS transistor and the P-MOS transistor. . Specifically, in an N-MOS transistor, the phase transition is suppressed by As implanted as an impurity, whereas in a P-MOS transistor, the phase transition is not suppressed. Therefore, Ni disilicide is formed in the P-MOS transistor. Would.
[0028]
In recent fine semiconductor devices, a large stress is easily applied locally due to the difference in the coefficient of thermal expansion of various structures, and stress concentrates particularly on a thinly formed gate electrode, and this stress promotes a silicide reaction. I know it will be done. Therefore, the thickness of the Ni silicide film of the gate electrode becomes non-uniform, and the gate resistance varies. If the Ni silicide film grows abnormally, the Ni reaches the gate insulating film and Ni diffuses, thereby deteriorating the gate insulating film. Resulting in. Further, if the abnormal growth of the Ni silicide film occurs at the boundary between the source / drain region and the sidewall, the diffusion layer recedes, which causes a problem that the variation in transistor characteristics increases.
[0029]
Such a problem is caused by the fact that the phase transition of Ni silicide easily occurs and the silicide reaction is difficult to control, and a method of suppressing the silicide reaction without affecting other processes is desired. In view of the above, the present invention solves the above-mentioned problem by injecting an element for suppressing a silicide reaction into a region where a silicide is to be formed, thereby suppressing disilicidation and aggregation. Specifically, Ge is used as a reaction-suppressing element, and when As is implanted into an N-MOS transistor, Ge is implanted into a P-MOS transistor so that the silicide reaction of both transistors is controlled to be equal. Further, when P is implanted into the N-MOS transistor, Ge is implanted into both the N-MOS transistor and the P-MOS transistor to suppress the silicide reaction, so that uniform Ni monosilicide is formed. I have to.
[0030]
Although the mechanism for suppressing the reaction of Ge is not necessarily clear, it is considered that the bonding force between Ni and Si in Ni disilicide is weaker than that in Ni monosilicide, and Ni is more stable when bonded to Ge. Although Ge is known as an impurity, when Ge is implanted, another impurity cannot be implanted at a deep position due to the effect of suppressing the reaction of Ge, which is suitable for a semiconductor device in which deep source / drain regions are formed. Absent. However, in the present invention, by using a method of implanting Ge under predetermined implantation conditions after implanting impurities into the source / drain regions, silicide is not affected without affecting impurity implantation for forming the source / drain regions. It is possible to suppress the reaction.
[0031]
【Example】
In order to describe the above-described embodiment of the present invention in more detail, an embodiment of the present invention will be described with reference to the drawings.
[0032]
[Example 1]
First, a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment, and FIGS. 2 to 5 are cross-sectional views showing the steps of a method for manufacturing the semiconductor device. 6 to 9 are diagrams showing experimental results for determining Ge implantation conditions in the method of manufacturing a semiconductor device according to the present embodiment.
[0033]
First, the structure of the semiconductor device of the present embodiment will be described with reference to FIG. The semiconductor device of the present embodiment includes an N-MOS transistor and a P-MOS transistor separated by an element isolation insulating film 2, and N-type impurities are implanted into the N-MOS region using the gate electrode 9 as a mask. An LDD region 7 is formed, and a source / drain region 4 is formed by implanting an N-type impurity containing at least As such as As or As + P using the gate electrode 9 and the sidewall 10 as a mask. An LDD region 7 formed by implanting a P-type impurity using the gate electrode 9 as a mask; a source / drain region 4 formed by implanting a P-type impurity using the gate electrode 9 and the side wall 10 as a mask; And a Ge implantation region 6 formed by implanting Ge into the source / drain region 4 under predetermined implantation conditions to be described later. And on P-MOS region both of the gate electrode 9 and the source / drain region of 4, Ni silicide film 5 of the monosilicide structure formed in a uniform thickness is formed.
[0034]
If the Ge implantation region 6 is formed in a part of the Ni silicide film formation region, it is possible to suppress the disilicidation or the aggregation reaction. However, in order to more reliably control the silicide reaction, As shown by the hatched portion in the enlarged view of FIG. 1, it is preferable to form the Ni silicide film formation region so as to cover it. In FIG. 1, the diffusion layer is composed of the LDD region 7 and the source / drain region 4, but is located inside the source / drain region 4 and has a junction shallower than the source / drain region 4. Alternatively, a configuration including a pocket diffusion layer located below the extension diffusion layer may be employed.
[0035]
A method for manufacturing the semiconductor device having the above structure will be described with reference to the process sectional views of FIGS. As a MOS transistor, a transistor with a low driving voltage in which a gate insulating film is formed thinly, a transistor in which the off-state current of the transistor is suppressed in order to achieve low power consumption, and a gate insulating film for a high withstand voltage I / O are used. Although there are transistors of various performances such as transistors, a case where two types of P-MOS transistors and N-MOS transistors are formed without distinguishing between them will be described.
[0036]
First, as shown in FIG. 2A, an element isolation insulating film 2 for forming a field region is formed on a semiconductor substrate 1 such as a P-type silicon substrate by STI (Shallow Trench Isolation). Is used to form a sacrificial layer (not shown) on the entire surface of the substrate. Next, as shown in FIG. 2B, the P-MOS region and the N-MOS region are alternately covered with a resist pattern, and B, BF ₂ After implanting a P-type impurity such as P or an N-type impurity such as P or As to form a P-well region 3a and an N-well region 3b, annealing for diffusing and activating the impurity is performed.
[0037]
Next, after the sacrificial layer is removed by wet etching, as shown in FIG. 2C, a silicon oxide film is formed using a CVD method or the like, and nitrogen is added to the silicon oxide film by plasma nitridation, annealing, implantation, or the like. To form a gate insulating film 8 having a desired thickness. The thickness of the gate insulating film 8 can be appropriately adjusted according to the type of the transistor.
[0038]
Next, as shown in FIG. 3A, after depositing or growing polycrystalline silicon, amorphous silicon, or the like serving as a gate electrode, a resist pattern (not shown) is formed using a known lithography technique. The gate electrode 9 is formed by etching the silicon material and the gate insulating film 8 using a known dry etching technique. After depositing or growing polycrystalline silicon, amorphous silicon, or the like, ions may be implanted into the gate electrode 9 by implanting a P-type impurity into the P-MOS region.
[0039]
Next, as shown in FIG. 3B, a resist pattern 11a is formed on the P-MOS region, and an N-type impurity such as As or As + P is implanted using the gate electrode 9 in the N-MOS region as a mask. The resist pattern 11a is removed, and annealing is performed at 800 to 1000 ° C. for about 0 to 10 seconds in a nitrogen atmosphere or a nitrogen + oxygen atmosphere to activate impurities in the N-MOS region and to form the LDD region 7 in the N-MOS region. Form. Note that a pocket diffusion layer or an extension diffusion layer may be formed instead of or in addition to the LDD region 7. The reason that the annealing time is set to 0 second is that the annealing time usually indicates the holding time after the target temperature is reached, but the temperature is lowered immediately after the target temperature is reached (such annealing is performed by spike annealing). ) May be used.
[0040]
Next, as shown in FIG. 3C, a resist pattern 11b is formed on the N-MOS region, and B and BF are formed using the gate electrode 9 in the P-MOS region as a mask. ₂ The LDD region 7 is formed by implanting a P-type impurity such as Here, similarly to the N-MOS region, a pocket diffusion layer or an extension diffusion layer may be formed in addition to or instead of the LDD region 7. Further, fluorine may be implanted for improving the reliability of the P-MOS transistor.
[0041]
Next, as shown in FIG. 3D, a silicon oxide film / nitride film or the like is deposited on the entire surface of the semiconductor substrate 1 and then etched back to form sidewalls 10 on the side surfaces of the gate electrode 9. The steps up to this point are the same as those of a general MOS transistor manufacturing method, the order of forming the well region and the LDD region in the P-MOS region and the N-MOS region, the implantation conditions of the N-type impurity and the P-type impurity, The type of the material, the manufacturing method, and the like can be appropriately changed.
[0042]
Next, as shown in FIG. 4A, a resist pattern 11c is formed on the P-MOS region, and N-type impurities such as As and As + P are removed using the gate electrode 9 and the sidewall 10 in the N-MOS region as a mask. Implantation is performed to form source / drain regions 4 in which N-type impurities are implanted at a high concentration in the N-MOS region.
[0043]
Next, after removing the resist pattern 11c, as shown in FIG. 4B, a resist pattern 11d is formed on the N-MOS region, and the gate electrode 9 and the side wall 10 in the P-MOS region are used as masks to form a resist pattern 11B. Or BF ₂ To form a source / drain region 4 in which a P-type impurity is implanted at a high concentration in the P-MOS region.
[0044]
Here, in the conventional method of manufacturing a semiconductor device, annealing is performed to activate impurities. In this embodiment, however, following the above-described ion implantation, as shown in FIG. Ge is implanted by ion implantation using the mask 9 and the sidewalls 10 as a mask to form a Ge implanted region (not shown) in the gate electrode 9 and the source / drain regions 4. This implantation of Ge is preferably performed deeper than the Ni silicide film 5 formed near the surfaces of the gate electrode 9 and the source / drain regions 4, and the implantation energy is about 5 to 10 KeV and the implantation dose is 1E15 to 3E15 cm. ^-2 It is performed under the conditions of the degree.
[0045]
In addition, B or BF ₂ The reason why the Ge implantation is performed after the implantation of Ge is that when Ge is implanted, channeling is suppressed at the time of subsequent impurity implantation, so that impurities cannot be implanted deeply. In No. 4, it is preferable to form a concentration profile as gentle as possible in order to suppress the junction leak. However, if Ge is implanted first, a shallow and steep concentration profile is formed.
[0046]
Next, as shown in FIG. 5A, in order to activate the impurities in the N-MOS region and the P-MOS region, in a nitrogen atmosphere or a nitrogen + oxygen atmosphere, at 800 to 1100 ° C., 0 (spike annealing). 5) After annealing for about 10 seconds, as shown in FIG. 5B, Ni12 is formed to a thickness of about 10 nm on the entire surface of the substrate by using a sputtering method, and then a CVD method or the like is formed thereon. Then, TiN 13 is formed to a thickness of about 10 nm. The thickness of Ni12 can be adjusted in consideration of the thickness of the Ni silicide film, and Pt exhibiting the same phase transition can be used instead of Ni. Further, TiN 13 is formed to suppress the reaction between Ni and oxygen during the silicidation of Ni, and Ti or the like may be formed instead of TiN.
[0047]
Next, annealing is performed in a nitrogen or argon atmosphere at 300 to 600 ° C. for about 1 to 120 seconds to cause the silicon of the gate electrode 9 and the source / drain region 4 to react with Ni 12 to form an N-MOS region and a P- At the same time, a Ni silicide film 5 having a monosilicide structure is formed in the MOS region.
[0048]
At this time, in the conventional method of manufacturing a semiconductor device in which Ge is not implanted, the N-MOS region into which As or As + P is implanted, and the B or BF ₂ Is different from the P-MOS region into which Ni is implanted, the speed of the phase transition and the aggregation reaction of Ni silicide is different, and the reaction of the N-MOS region is suppressed by As. Therefore, if an attempt is made to form Ni monosilicide having a predetermined thickness in the N-MOS region, the reaction proceeds in the P-MOS region to form Ni disilicide, thereby increasing the parasitic resistance and increasing the ON current of the transistor. There has been a problem that the junction leakage may occur due to the decrease or unevenness of the Ni disilicide.
[0049]
On the other hand, in this embodiment, Ge of a predetermined concentration is implanted into the source / drain region 4 of the P-MOS region, and the effect of suppressing the silicide reaction by Ge and the effect of suppressing the silicide reaction by As are obtained. Are approximately the same, the same Ni monosilicide can be formed in both regions, the above problem can be suppressed, and the variation in the characteristics of the P-MOS transistor and the N-MOS transistor can be suppressed. be able to.
[0050]
Further, in recent miniaturized semiconductor devices, a stress from another structure is applied to the thin gate electrode 9, and as a result, a silicide reaction is promoted and the Ni silicide film 5 is formed to a deep position. And the problem that the Ni silicide film 5 abnormally grows, reaches the gate insulating film 8 and diffuses Ni, thereby deteriorating the gate insulating film 8. Further, if abnormal growth occurs at the end of the source / drain region 4 on the side wall 10 side, the source / drain region 4 recedes, resulting in a problem that the transistor characteristics fluctuate.
[0051]
On the other hand, in this embodiment, Ge of a predetermined concentration is also implanted on the gate electrode 9 in the P-MOS region, and the disilicidation or agglutination reaction is suppressed by Ge. Variations in transistor characteristics due to variations, deterioration of the gate insulating film 8, and receding of the source / drain regions 4 can also be suppressed.
[0052]
Thereafter, as shown in FIG. 5C, after removing TiN13 by dry etching, as shown in FIG. 5D, unreacted Ni12 is removed by wet etching, and the gate electrode 9 and the source / drain regions are removed. A contact plug (not shown) is formed in the upper layer 4 and connected to the wiring in the upper layer to form a part of the semiconductor device of this embodiment.
[0053]
In the above flow, As or As + P is injected into the N-MOS region, and then B or BF is injected into the P-MOS region. ₂ And Ge were implanted, but B or BF in the P-MOS region ₂ If the implantation of Ge and the implantation of Ge are in this order, the order of the impurity implantation in the N-MOS region and the impurity implantation in the P-MOS region may be reversed.
[0054]
Next, conditions for Ge implantation, which is a feature of the present invention, will be discussed. As described above, Ge is implanted in a part (preferably so as to cover the part) of the region where the Ni silicide film 5 is formed near the surface of the gate electrode 9 and the source / drain region 4 in the P-MOS region. In addition, it is necessary to perform the injection under conditions that are equivalent to the reaction suppression effect of As injected into the N-MOS transistor. The gate resistance and the amount of recession of the source / drain region 4 were measured using the implantation dose in Ge implantation as a parameter, and the implantation dose was determined based on the results. Hereinafter, the details and results of the experiment will be described.
[0055]
First, the implantation energy of Ge is fixed at 5 KeV, and the implantation dose is 0 to 5E15 cm. ^-2 The gate resistance was measured when it was changed in the range of, and the sample without Ge injection and 3E15 ^-2 The thickness of the Ni silicide film 5 was confirmed by an SEM photograph for the sample injected under the conditions described above. The results are shown in FIGS.
[0056]
As can be seen from FIG. 6A and FIG. 6B which is an enlarged view of FIG. 6A, the sample without Ge implantation or the implantation dose of Ge is 5E14 cm. ^-2 It can be seen that in the samples with a small number of samples, there is a large variation in the gate resistance, and there is a transistor in which the sheet resistance is partially reduced. On the other hand, the implantation dose of Ge is 1E15 to 3E15 cm. ^-2 In each of the samples, the variation in the sheet resistance value is small, and it can be seen that the silicide reaction is controlled by Ge implantation. On the other hand, the implantation dose of Ge is 5E15 cm. ^-2 It can be seen from the sample No. that the silicide reaction was excessively suppressed by Ge, the Ni silicide film 5 was not sufficiently formed, and the sheet resistance value was significantly increased.
[0057]
In order to confirm the relationship between the decrease in the sheet resistance value and the film thickness of the Ni silicide film 5, the sample without Ge implantation and the implantation dose of Ge were set to 3E15 cm. ^-2 The cross section of the portion of the gate electrode 9 of the sample set as above was observed with an electron microscope. In the sample in which Ge implantation is not performed, the thickness of the Ni silicide film 5 differs greatly from transistor to transistor, and as shown in the upper part of FIG. In contrast to Ge 3E15cm ^-2 7, the thickness of the Ni silicide film 5 is substantially constant at about 20 to 25 nm as shown in the lower diagram of FIG. 7, and the Ge implantation of the present invention suppresses abnormal growth of the Ni silicide film 5. I was sure that.
[0058]
Next, when the heat treatment at 600 ° C. was added, the receding amount of the end of the source / drain region 4 on the side wall 10 at each Ge implantation dose was measured. Further, the state where the source / drain region 4 receded was confirmed by SEM. The results are shown in FIGS. FIG. 8 is a graph showing the dependency of the amount of recession of the diffusion layer on the dose of Ge implantation. The horizontal axis represents the implantation dose of Ge, and the vertical axis represents the left and right of three representative samples at each implantation dose. Indicates the average value of the retreat amount.
[0059]
As can be seen from FIG. 8, in the sample in which Ge implantation was not performed, the retreat amount of the diffusion layer shown in FIG. 9 was as large as about 40 nm, but as the Ge implantation dose increased, the end of the source / drain region 4 was increased. It can be seen that the silicide reaction in the part is suppressed, and as a result, the receding amount gradually decreases. Since it is preferable that the retreat of the diffusion layer is as small as possible, it can be said that the larger the implantation dose of Ge, the better.
[0060]
From the above experimental results, the implantation dose of Ge is 1E15 to 3E15 cm. ^-2 The degree is a preferred range. The implantation energy is 5 to 10 KeV and the implantation dose is 1E15 to 3E15 cm. ^-2 It has been confirmed that, in the case of, the abundance ratio of Ge near the surface of the implantation region is about 0.1 to 5%.
[0061]
Thus, B or BF is applied to the gate electrode 9 and the source / drain region 4 in the P-MOS region. ₂ After implantation, the implantation energy is about 5 to 10 KeV, and the implantation dose is about 1E15 to 3E15 cm. ^-2 By performing Ge implantation under such conditions, Ge can be introduced into the region where the Ni silicide film 5 is to be formed at an abundance ratio of about 0.1 to 5%. Ni silicide reaction in both the N-MOS region and the N-MOS region can be controlled substantially equally, and as a result, Ni mono-silicide can be formed in both transistors with a uniform film thickness. As a result, it is possible to suppress a decrease in on-current due to an increase in parasitic capacitance and a junction leak due to unevenness of Ni disilicide, and an abnormality in the gate electrode 9 and the Ni silicide film 5 at the end of the source / drain region 4. Since growth is prevented, variations in gate resistance, deterioration of the gate insulating film 8, and retreat of the diffusion layer can be suppressed, and variations in transistor characteristics can be reduced.
[0062]
[Example 2]
Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. 10 to 12 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment.
[0063]
In the first embodiment, As or As + P is implanted into the source / drain regions of the N-MOS region, and dissilicidation or agglutination is suppressed by As in the N-MOS region. As the activation rate of P is higher than that of As, the use of P can increase the on-state current, but the disadvantage is that P is easily diffused and the short channel effect cannot be suppressed. . Because of these characteristics, in an actual semiconductor device, what is used as an N-type impurity is determined depending on the structure of the semiconductor device and required performance. In some cases, and disilicidation or agglutination cannot be sufficiently suppressed. Thus, the present embodiment is characterized in that Ge is implanted into the N-MOS region to suppress the silicide reaction.
[0064]
The method for manufacturing the semiconductor device will be described with reference to the process sectional views of FIGS. First, similarly to the first embodiment, an element isolation insulating film 2 is formed on a semiconductor substrate 1, and a P-MOS region and an N-MOS region are alternately covered with a resist pattern. ₂ P-type impurities such as P or As, or N-type impurities such as P and As are implanted to form a P-well region 3a and an N-well region 3b, and annealing for diffusing and activating the impurities is performed. Next, after a gate insulating film 8 having a desired thickness is formed, polycrystalline silicon, amorphous silicon, or the like serving as a gate electrode is deposited or grown and etched to form a gate electrode 9 (FIG. 10A). reference).
[0065]
Next, as shown in FIG. 10B, a resist pattern 11a is formed on the P-MOS region, and P or N-type impurities containing P are implanted using the gate electrode 9 in the N-MOS region as a mask. Annealing is performed in a nitrogen atmosphere or a nitrogen + oxygen atmosphere at 800 to 1000 ° C. for about 0 to 10 seconds to activate the impurities in the N-MOS region and form the LDD region 7 in the N-MOS region. Here, in the first embodiment, the structure including As as an N-type impurity is employed. However, in the present embodiment, Ge is implanted into the N-MOS region, and therefore, it is not necessary to include As.
[0066]
Next, as shown in FIG. 10C, a resist pattern 11b is formed on the N-MOS region, and B and BF are formed using the gate electrode 9 in the P-MOS region as a mask. ₂ The LDD region 7 is formed by implanting a P-type impurity such as Then, after depositing a silicon oxide film, a nitride film, and the like over the entire surface of the semiconductor substrate 1, the side walls 10 are formed on the side surfaces of the gate electrode 9 by etching back (see FIG. 11A).
[0067]
Next, as shown in FIG. 11B, a resist pattern 11c is formed on the P-MOS region, and an N-type impurity containing P or P is doped using the gate electrode 9 and the sidewall 10 in the N-MOS region as a mask. Implantation is performed to form source / drain regions 4 in which N-type impurities are implanted at a high concentration in the N-MOS region. Again, in the first embodiment, As is included as an N-type impurity, but in this embodiment, As is implanted into the N-MOS region, so that As may not be included.
[0068]
Next, as shown in FIG. 11C, a resist pattern 11d is formed on the N-MOS region, and B or BF is formed using the gate electrode 9 and the sidewall 10 in the P-MOS region as a mask. ₂ To form a source / drain region 4 in which a P-type impurity is implanted at a high concentration in the P-MOS region.
[0069]
Next, in the first embodiment, Ge is implanted while leaving the resist pattern 11d as it is. However, in this embodiment, Ge is implanted into the P-MOS region and the N-MOS region at the same time. As shown in a), after removing the resist pattern 11d, Ge is implanted into the entire surface of the substrate by using an ion implantation method to form a Ge implanted region (not shown) in the gate electrode 9 and the source / drain region 4. . The implantation of Ge is also performed at an implantation energy of about 5 to 10 KeV and an implantation dose of 1E15 to 3E15 cm so that the Ge surface concentration is about 0.1 to 5%. ^-2 It is performed under the conditions of the degree. It should be noted that the implantation amount of Ge can be changed between the N-MOS region and the P-MOS region according to the amount of As in the N-MOS region. In that case, for example, B or BF in FIG. ₂ After the implantation of Ge, Ge is implanted only in the P-MOS region while leaving the resist pattern 11d, then the resist pattern 11d is removed, and Ge is implanted into the entire surface of the substrate.
[0070]
Next, in order to activate impurities in the N-MOS region and the P-MOS region, annealing is performed at 800 to 1100 ° C. and 0 (spike annealing) for about 10 seconds in a nitrogen atmosphere or a nitrogen + oxygen atmosphere. Thereafter, as shown in FIG. 12 (b), Ni12 is formed to a thickness of about 10 nm on the entire surface of the substrate by sputtering, and TiN13 is deposited to a thickness of about 10 nm by CVD or the like. Form. Then, annealing is performed at 300 to 600 ° C. for about 1 to 120 seconds in a nitrogen or argon atmosphere to cause the silicon of the gate electrode 9 and the source / drain region 4 to react with Ni 12 to form an N-MOS region and a P-MOS At the same time, a Ni silicide film 5 having a monosilicide structure is formed in the region.
[0071]
Thereafter, as shown in FIG. 12C, after removing TiN 13 by dry etching, unreacted Ni 12 is removed by wet etching, and a contact plug (not shown) is formed on the gate electrode 9 and the source / drain region 4. Then, a part of the semiconductor device of the present embodiment is formed by connecting to the upper layer wiring.
[0072]
As described above, when As is not implanted into the N-MOS region or when the implantation dose is small, Ge is implanted into the entire surface of the substrate after forming the source / drain regions 4 in the P-MOS and N-MOS regions. Thereby, Ni monosilicide having the same thickness can be formed in both the P-MOS region and the N-MOS region, and the same effect as that of the first embodiment can be obtained.
[0073]
In each of the above embodiments, a method of manufacturing a semiconductor device including both an N-MOS transistor and a P-MOS transistor has been described. However, only the P-MOS transistor is used in the first embodiment, and the N-MOS transistor is used in the second embodiment. -The manufacturing method of the present invention can be applied only to MOS transistors. In the above embodiment, the same N-type impurity is implanted into the LDD region 7 and the source / drain region 4 in the N-MOS region. However, since the Ni silicide film 5 is not directly formed in the LDD region 7, In the first embodiment, the structure may not include As, and in the second embodiment, the structure may include As. Further, in each of the above embodiments, an example was described in which Ni was used as the metal to be silicided. However, the present invention is not limited to the above embodiment, and the same effect can be obtained by using Pt as the metal to be silicided. Has been confirmed. Further, the impurity that suppresses the silicide reaction is not limited to Ge, and another impurity that can suppress disilicide or agglutination can be used.
[0074]
【The invention's effect】
As described above, in a structure having a Ni silicide film near the surface of a gate electrode and source / drain regions, it is possible to suppress a decrease in on-current due to an increase in parasitic resistance and an increase in junction leak due to unevenness of the silicide film. In addition, variations in gate resistance due to abnormal growth of Ni silicide, deterioration of the gate insulating film, and recession of the source / drain regions can be suppressed, and the uniformity of transistor characteristics can be improved.
[0075]
The reason is that the gate electrode and the source / drain region of the P-MOS transistor or the gate electrode and the source / drain region of the N-MOS transistor which does not contain As as an N-type impurity or have a small As implantation dose are added to the gate electrode and the source / drain region. By ion implantation of Ge under the implantation conditions described above, the disilicidation and the aggregation reaction can be reliably suppressed. As a result, Ni monosilicide having a uniform film thickness can be formed in both the N-MOS and P-MOS transistors. This is because it can be formed. Further, silicide reaction in a portion where stress is concentrated in a semiconductor device having a fine structure can be suppressed.
[Brief description of the drawings]
FIG. 1 is a sectional view schematically showing a structure of a semiconductor device according to a first example of the present invention.
FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a graph showing the dependency of the gate resistance on the implantation dose due to Ge implantation according to the present invention.
FIG. 7 is an SEM photograph for explaining a difference in silicide film thickness due to Ge implantation.
FIG. 8 is a graph showing the dependence of the amount of retreat of a diffusion layer by Ge implantation of the present invention on the implantation dose.
FIG. 9 is an SEM photograph for explaining a retreat amount of a diffusion layer due to Ge implantation.
FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 12 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 13 is a process sectional view illustrating a method for manufacturing a conventional semiconductor device.
FIG. 14 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
1 semiconductor substrate
2 Element isolation insulating film
3a p-well region
3b n-well region
4 Source / drain regions
5 Ni silicide film
5a Ni silicide film grown abnormally
6 Ge implantation region
7 LDD area
8 Gate insulating film
9 Gate electrode
10 Sidewall
11a-11d resist pattern
12 Ni
13 TiN
14 Metal film
15 Metal silicide film
15a Thick metal silicide film
15b Thin metal silicide film

Claims (12)

A first impurity diffusion region formed in a self-aligned manner with respect to a gate electrode; and a second impurity formed in a self-aligned manner with respect to the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode. A semiconductor device including at least a diffusion region and a metal silicide film formed near a surface of the gate electrode and the second impurity diffusion region;
Ge is implanted in a region where the metal silicide film is formed. A first impurity diffusion region formed in a self-aligned manner with respect to a gate electrode; and a second impurity formed in a self-aligned manner with respect to the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode. A semiconductor device including a P-MOS transistor and an N-MOS transistor including at least a diffusion region and a metal silicide film formed near a surface of the gate electrode and the second impurity diffusion region,
The second impurity diffusion region of the N-MOS transistor is formed by implanting As or an N-type impurity including As,
Ge is implanted in a region of the P-MOS transistor where the metal silicide film is formed. A first impurity diffusion region formed in a self-aligned manner with respect to a gate electrode; and a second impurity formed in a self-aligned manner with respect to the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode. A semiconductor device including a P-MOS transistor and an N-MOS transistor including at least a diffusion region and a metal silicide film formed near a surface of the gate electrode and the second impurity diffusion region,
A second impurity diffusion region of the N-MOS transistor is formed by implanting P or an N-type impurity including P;
Ge is implanted in regions where the metal silicide films of the P-MOS transistor and the N-MOS transistor are formed. 4. The semiconductor device according to claim 1, wherein said Ge is implanted to a position deeper than said metal silicide film. 5. The semiconductor device according to claim 1, wherein the Ge is implanted under the conditions of an implantation energy of about 5 KeV and an implantation dose of about 1E15 to 3E15 cm ⁻² . 6. The semiconductor device according to claim 1, wherein the metal silicide film is a monosilicide film formed using Ni or Pt. Forming a first impurity diffusion region using the gate electrode as a mask, forming a second impurity diffusion region using the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode as a mask, A semiconductor device comprising at least a step of implanting Ge into an electrode and the second impurity diffusion region, and a step of forming a metal silicide film near a surface of the gate electrode and the second impurity diffusion region. Manufacturing method. A method for manufacturing a semiconductor device including a P-MOS transistor and an N-MOS transistor,
Using the gate electrode as a mask, implanting an N-type impurity into the N-MOS transistor formation region and implanting a P-type impurity into the P-MOS transistor formation region to form a first impurity diffusion region;
Using the gate electrode and a sidewall insulating film provided on the side wall of the gate electrode as a mask, As or an N-type impurity containing As is implanted into the N-MOS transistor formation region, and a P-type impurity is implanted into the P-MOS transistor formation region. Implanting an impurity to form a second impurity diffusion region;
Implanting Ge into the gate electrode and the second impurity diffusion region of the P-MOS transistor formation region;
Forming a metal silicide film near the surface of the gate electrode and the second impurity diffusion region in the P-MOS transistor formation region and the N-MOS transistor formation region. Manufacturing method. A method for manufacturing a semiconductor device including a P-MOS transistor and an N-MOS transistor,
Using the gate electrode as a mask, implanting an N-type impurity into the N-MOS transistor formation region and implanting a P-type impurity into the P-MOS transistor formation region to form a first impurity diffusion region;
Using the gate electrode and a sidewall insulating film provided on a side wall of the gate electrode as a mask, an N-type impurity containing P or P is implanted into the N-MOS transistor formation region, and a P-type impurity is implanted into the P-MOS transistor formation region. Implanting an impurity to form a second impurity diffusion region;
Implanting Ge into the gate electrode and the second impurity diffusion region of the P-MOS transistor formation region and the N-MOS transistor formation region;
Forming a metal silicide film near the surface of the gate electrode and the second impurity diffusion region in the P-MOS transistor formation region and the N-MOS transistor formation region. Manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 7, wherein said Ge is implanted to a position deeper than said metal silicide film. The method of manufacturing a semiconductor device according to claim 7, wherein the Ge is implanted under conditions of an implantation energy of about 5 KeV and an implantation dose of about 1E15 to 3E15 cm ⁻² . 12. The method of manufacturing a semiconductor device according to claim 7, wherein the metal silicide film is formed as a monosilicide film using Ni or Pt.

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