JP2004226435A - Display device and mobile terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in which the layout of a reference voltage line occupies the majority of a frame since the reference voltage line needs to be made low in impedance and wired as thick as possible to write a desired potential when a buffer of a trailing stage of a DA converting circuit is omitted. <P>SOLUTION: In a driving circuit integrated type liquid crystal display device using a reference voltage selection type DA converting circuit 134, the buffer of the trailing stage of the DA converting circuit 134 is omitted and a display signal is written directly to signal lines 25-1 to 25-x of a pixel part 12 to reduce power consumption; and further a reference voltage generating circuit 18 is arranged in a frame on the opposite side from a vertical driving circuit 14 across the pixel part 12 and an interface circuit 15 and a timing generating circuit 17 are arranged on the side of the vertical driving circuit 24, so even if the layout area of reference voltage lines 31-1 to 31-64 increases according as the buffer is omitted, an increase in the size of the frame of a display panel is minimized. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flat panel display device represented by a liquid crystal display device or an EL (electroluminescence) display device, and a portable terminal having the display device as a screen display unit. The present invention relates to a so-called drive circuit integrated display device formed integrally on a transparent insulating substrate, and a mobile terminal including the display device as a screen display portion.
[0002]
[Prior art]
In the field of flat panel display devices represented by liquid crystal display devices and EL display devices, in recent years, in order to reduce the size and thickness of the display device, the same transparent insulation as that of a pixel portion in which pixels are arranged in a matrix is used. On a substrate, for example, a glass substrate (display panel), a peripheral driving circuit for driving the pixel portion, specifically, a vertical driving circuit for selectively scanning each pixel of the pixel portion in a row unit, or a vertical driving circuit for selecting The development of a drive circuit integrated type display device in which a horizontal drive circuit for writing a display signal to the pixels in the specified row and the like are integrally formed has been advanced.
[0003]
FIG. 10 shows an example of the structure of the display device with integrated driving circuits. As is clear from the figure, pixels are arranged in a matrix on the same transparent insulating substrate, for example, a glass substrate 101 to form a pixel portion 102, and a region around the pixel portion 102 (hereinafter, this region is referred to as Driving circuits such as a pair of horizontal driving circuits 103A and 103B, a vertical driving circuit 104, an interface circuit 105, a timing generation (TG) circuit 106, a reference voltage generation circuit 107, a Vcom / CS driver 108, etc. The pixel unit 102 is arranged and formed integrally.
[0004]
In the drive circuit integrated display device, a pair of horizontal drive circuits 103A and 103B are arranged on the upper and lower frames of the pixel portion 102, and a vertical drive circuit 104 is arranged on the right frame thereof, for example. An interface circuit 105, a timing generation (TG) circuit 106, a reference voltage generation circuit 107, and a Vcom / CS driver 108 are arranged on the left frame, that is, on the frame opposite to the vertical drive circuit 104 across the pixel portion 102. (For example, see Patent Publication 1).
[0005]
The horizontal drive circuits 103A and 103B have a digital interface drive circuit configuration. FIG. 11 shows an example of the configuration of the horizontal drive circuits 103A and 103B.
[0006]
These horizontal drive circuits 103A and 103B sample display data in synchronization with the horizontal shift registers 201 of the number of stages corresponding to the number of pixels in the horizontal direction of the pixel portion 102 and sampling pulses sequentially output from the horizontal shift registers 201. A sampling latch circuit 202 for latching, a line-sequentialization latch circuit 203 for line-sequentializing by holding the sampling data for one horizontal period, and a plurality of reference voltages provided from the reference voltage generation circuit 107 in FIG. And a reference voltage selection type DA conversion circuit 204 for selecting a reference voltage corresponding to the latch data of the line-sequencing latch circuit 203 to convert the reference voltage into an analog display signal.
[0007]
In the horizontal drive circuits 103A and 103B having such a configuration, the reference potential is usually set so that a desired potential can be written to each of the signal lines wired in pixel columns in the pixel array of the pixel unit 102. A buffer 205 composed of, for example, a source follower circuit is provided at the subsequent stage of the voltage selection type DA conversion circuit 204, that is, between each of the signal lines of the pixel unit 102 (for example, see Patent Document 2).
[0008]
[Patent Document 1]
JP-A-2002-175026 (particularly, column 6, FIGS. 1 and 3)
[Patent Document 2]
JP-A-11-073165 (particularly, column 6, FIG. 4)
[0009]
By the way, as a use of a flat panel display device represented by a liquid crystal display device or an EL display device, for example, a portable terminal (device) represented by a mobile phone or a PDA (Personal Digital Assistants) is cited. . In this type of portable terminal, a battery is used as a power source, so it is desirable that the battery can be used for as long as possible by one charge of the battery. Therefore, there is a strong demand for lower power consumption for flat panel display devices mounted on mobile terminals.
[0010]
Therefore, various measures have been taken in the above-described drive circuit integrated display device in order to reduce power consumption. As one of the measures, the buffer 205 may be omitted in the horizontal driving circuits 103A and 103B. That is, by writing the analog display signal output from the DA conversion circuit 204 directly to each of the signal lines of the pixel unit 102 without passing through the buffer 205, a measure for reducing the power consumed by the buffer 205 in the past is considered. It is.
[0011]
As described above, in order to write a desired potential to each of the signal lines of the pixel portion 102 without passing through the buffer 205 in order to reduce power consumption, the reference voltage generated by the reference voltage generation circuit 107 is used. It is necessary to lower the impedance of the reference voltage line that transmits the voltage to the DA conversion circuit 204. For this purpose, it is necessary to wire the reference voltage lines in a pattern as thick as possible.
[0012]
[Problems to be solved by the invention]
However, considering that the digital display data input to the DA conversion circuit 204 is, for example, 6 bits, the reference voltage line connected between the reference voltage generation circuit 107 and the DA conversion circuit 204 is 64 (= 2). ⁶ (6) Since 64 lines are required corresponding to the reference voltages for the gradation, if the reference voltage lines are wired in a thick pattern, most of the frame is occupied by the layout of the reference voltage lines. Therefore, as described above, if the configuration in which the reference voltage generation circuit 107 is arranged on the same side as the interface circuit 105, the timing generation circuit 106, and the Vcom / CS driver 108 is employed, the layout area becomes very large. This makes it difficult to reduce the frame width of the flat panel display device, and eventually to reduce the size of the flat panel display device itself.
[0013]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the power consumption by omitting a buffer, and to reduce the layout area of a reference voltage line with the elimination of the buffer. An object of the present invention is to provide a display device capable of minimizing an increase in a frame of a display panel even when the display device increases, and a mobile terminal including the display device as a screen display unit.
[0014]
[Means for Solving the Problems]
A display device according to the present invention includes a pixel portion in which pixels are arranged in a matrix, a vertical drive circuit that selects each pixel of the pixel portion in a row unit, a reference voltage generation circuit that generates a plurality of reference voltages, A digital-to-analog conversion circuit that selects a reference voltage corresponding to digital display data from among a plurality of reference voltages, and applies the reference voltage selected by the digital-to-analog conversion circuit to each pixel in a row selected by the vertical drive circuit; A horizontal drive circuit that supplies a display signal, an interface circuit that performs level conversion of a signal input from outside the transparent insulating substrate, and various timing signals based on the level-converted signal generated by the interface circuit. A timing generation circuit provided to each circuit unit, wherein the vertical drive circuit, the reference voltage generation circuit, and the horizontal drive circuit are connected to the pixel unit and And the vertical drive circuit and the reference voltage generation circuit are disposed on opposite sides of the pixel portion, and the interface circuit and the timing generation circuit are disposed on the same vertical insulation circuit. It is a configuration arranged on the side. The display device having such a configuration is used by being mounted on a portable terminal typified by a PDA or a mobile phone as a screen display unit.
[0015]
In the display device having the above configuration or a mobile terminal including the display device as a screen display unit, a display signal converted to an analog signal by the DA conversion circuit without providing a buffer at a subsequent stage of the reference voltage selection type DA conversion circuit. Is written directly to each of the signal lines in the pixel portion, so that power consumption can be reduced by the amount of power conventionally consumed by the buffer. On the other hand, in order to write a desired potential to the signal line, it is necessary to lower the impedance of the reference voltage line wired between the reference voltage generation circuit and the DA conversion circuit. growing. However, by arranging the reference voltage generation circuit on the frame opposite to the vertical drive circuit across the pixel portion, and further arranging the interface circuit and the timing generation circuit on the vertical drive circuit side, the frame on the reference voltage generation circuit side is Since it can be mainly used for the layout of the reference voltage lines, it is possible to minimize an increase in the size of the frame of the display panel even when the number of reference voltage lines is large.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0017]
FIG. 1 is a block diagram showing a configuration example of a drive circuit integrated display device, for example, a liquid crystal display device according to an embodiment of the present invention. In FIG. 1, on a transparent insulating substrate, for example, a glass substrate 11, a large number of pixels are arranged in a matrix to form a pixel portion 12. The glass substrate 11 is opposed to another glass substrate (not shown) with a predetermined gap, and forms a display panel by sealing a liquid crystal material between the two substrates.
[0018]
FIG. 2 illustrates an example of a configuration of a pixel circuit in the pixel portion 12. Each of the pixels 20 arranged in a matrix includes a TFT (Thin Film Transistor) 21 serving as a pixel transistor, a liquid crystal cell 22 having a pixel electrode connected to a drain electrode of the TFT 21, and a pixel of the liquid crystal cell 22. The storage capacitor 23 has one electrode connected to one electrode. Here, the liquid crystal cell 22 means a liquid crystal capacitance generated between a pixel electrode and a counter electrode formed to face the pixel electrode.
[0019]
In this pixel structure, the TFT 21 has a gate electrode connected to a scanning line (gate line) 24 and a source electrode connected to a signal line (source line) 25. The liquid crystal cell 22 has a common electrode connected to a common line 26 for each pixel. Then, a common potential Vcom is commonly applied to the counter electrode of the liquid crystal cell 22 via the common line 26 for each pixel. The other electrode of the storage capacitor 23 is commonly connected to the CS line 27 for each pixel.
[0020]
By the way, in the liquid crystal display device, in order to prevent the specific resistance (resistance value inherent to a substance) of the liquid crystal from deteriorating due to the continuous application of the same polarity DC voltage to the liquid crystal, the polarity of the display signal is set to a predetermined period, for example, 1H (H is a horizontal period) or 1F (F is a field period). In the case of performing the AC inversion drive, the display signal written to each pixel performs the polarity inversion based on the common potential Vcom.
[0021]
When common inversion driving for inverting the polarity of the common potential Vcom at a fixed period, for example, 1H or 1F period is used together with 1H inversion driving or 1F inversion driving, the potential of the CS line 57 (hereinafter referred to as “CS potential”) ) Is also AC-inverted in synchronization with the common potential Vcom. Note that the CS potential is a potential having substantially the same amplitude and the same phase as the common potential Vcom.
[0022]
In FIG. 1 again, on the same glass substrate 11 as the pixel unit 12, for example, horizontal drive circuits 13A and 13B are provided on the upper and lower frames of the pixel unit 12, and a vertical drive circuit 14 is provided on the right frame of the pixel unit 12. An interface (IF) circuit 15, a horizontal (H) / vertical (V) synchronization detection circuit 16 and a timing generation (TG) circuit 17 are provided. A reference voltage generation circuit 18 and a Vcom / CS driver 19 are provided on the left frame of the pixel section 12. Each is mounted as a peripheral drive circuit. However, here, only a part is illustrated as a peripheral driving circuit, and the present invention is not limited to these. These peripheral drive circuits are manufactured using low-temperature polysilicon or CG (Continuous Grain: continuous grain boundary crystal) silicon together with the pixel transistors in the pixel section 12.
[0023]
In the liquid crystal display device integrated with a driving circuit having the above-described configuration, the horizontal driving circuit 13A employs a digital interface driving circuit configuration. For example, a horizontal shift register 131, a sampling latch circuit 132, a line sequential latch circuit 133, and a DA conversion circuit 134, and is responsible for driving, for example, pixels in an odd column of the pixel array of the pixel unit 12. The horizontal drive circuit 13B has exactly the same configuration as the horizontal drive circuit 13A. The horizontal drive circuit 13A drives the pixels in the odd columns, while the horizontal drive circuit 13A drives the pixels in the even columns.
[0024]
The horizontal shift register 131 starts the shift operation in response to the horizontal start pulse HST supplied from the timing generation circuit 17, and sequentially in one horizontal period in synchronization with the horizontal clock pulse HCK supplied from the timing generation circuit 17. Generate a sampling pulse to be transferred. The sampling latch circuit 132 samples and latches display data Data input from the outside of the substrate and supplied in a level-shifted manner by the interface circuit 15 in one horizontal period in synchronization with the sampling pulse generated by the horizontal shift register 131. I do.
[0025]
The latched digital display data for one line is line-sequentialized by being latched by the line-sequencing latch circuit 133. From the line-sequentialization latch circuit 133, digital display data for one line that has been line-sequentialized is output all at once. The output digital display data for one line is applied to a reference voltage selection type DA conversion circuit 134, where it is converted into an analog display signal. The analog display signal for one line output from the DA conversion circuit 134 is supplied to the signal lines 25-1 to 25-x wired corresponding to the number x of pixels in the horizontal direction of the pixel unit 12 without passing through a buffer. Output directly.
[0026]
The vertical drive circuit 14 includes a vertical shift register and a gate buffer. In the vertical drive circuit 14, the vertical shift register starts the shift operation in response to the vertical start pulse VST supplied from the timing generation circuit 17, and synchronizes with the vertical clock pulse VCK supplied from the timing generation circuit 17. To generate a scanning pulse which is sequentially transferred in one vertical period. The generated scanning pulses are sequentially output to the scanning lines 24-1 to 24-y wired corresponding to the number m of pixels in the vertical direction of the pixel unit 12 through the gate buffer.
[0027]
When the scanning pulse is sequentially output to the scanning lines 24-1 to 24-y by the vertical scanning by the vertical driving circuit 14, each pixel of the pixel unit 12 is sequentially selected in units of rows (lines). Then, one line of the analog display signal output from the DA conversion circuit 134 is simultaneously written directly to the selected one line of pixels via the signal lines 25-1 to 25-x. The image display for one screen is performed by repeating the line-by-line writing operation.
[0028]
The interface circuit 15 includes a master clock MCK having a low voltage amplitude (for example, 3.3 V amplitude) input from the outside of the glass substrate 11 via the input pad 28, a horizontal synchronization pulse Hsync, a vertical synchronization pulse Vsync, and R (red). The display data Data, the data enable signal DENB, and other control pulses of the G (green) and B (blue) parallel inputs are level-shifted (level-converted) to a signal level having a high voltage amplitude (for example, 6.0 V).
[0029]
The level-shifted master clock MCK is directly supplied to the timing generation circuit 17, and the horizontal synchronization pulse Hsync, the vertical synchronization pulse Vsync, and the data enable signal DENB are supplied to the timing generation circuit 17 via the H / V synchronization detection circuit 16. You. The timing generation circuit 17 is necessary for driving the horizontal drive circuits 13A and 13B, the vertical drive circuit 14, the reference voltage generation circuit 18, and the Vcom / CS driver 19 based on the master clock MCK, the horizontal synchronization pulse Hsync, and the vertical synchronization pulse Vsync. Various timing pulses are generated. The level-shifted display data Data is supplied to the horizontal drive circuits 13A and 13B, respectively.
[0030]
By the way, in the drive mode in which the timing generation circuit 17 detects the horizontal synchronization timing and the vertical synchronization timing from the horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync, respectively, the front porch and the back porch in the horizontal blanking period and the vertical blanking period are used. Must be changed depending on the manufacturer and model. In particular, since the horizontal synchronization timing and the vertical synchronization timing are detected at the falling timing of the horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync, the back porch is fixed when the peripheral driving circuit is formed on the glass substrate 11. Must be designed above.
[0031]
Therefore, as shown in the timing chart of FIG. 3, there is a method of using the data enable signal DENB so as not to change the setting of the blanking period for each maker or model. The timing chart of FIG. 3 shows an example in which the data dots are 240 horizontal dots, 240 vertical lines, 32 horizontal blanking periods, and 16 vertical blanking periods.
[0032]
In the drive circuit integrated type liquid crystal display device according to the present embodiment, as the drive modes, a SYNC mode in which the horizontal synchronization timing and the vertical synchronization timing are directly detected from the horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync, and an H / H signal from the data enable signal DENB. The V detection circuit 16 detects a horizontal synchronization pulse Hsync and a vertical synchronization pulse Vsync, and selectively employs a DENB mode in which horizontal synchronization timing and vertical synchronization timing are directly detected from the detected horizontal synchronization pulse DENB_H and vertical synchronization pulse DENB_V. I'm trying to get.
[0033]
FIG. 4 shows an example of timing in the SYNC mode. The horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync have a front porch from the end of the valid data period to the fall and a back porch from the fall to the start of the valid data period. In the SYNC mode, the H / V detection circuit 16 passes the horizontal synchronization pulse Hsync and the vertical synchronization pulse Vsync as they are and supplies them to the timing generation circuit 17.
[0034]
FIG. 5 shows an example of vertical timing in the DENB mode, and FIG. 6 shows an example of horizontal timing in the DENB mode. The data enable signal DENB has a low level during the horizontal blanking period and the vertical blanking period, and has a high level only during a period of capturing valid data. The data enable signal DENB is separated into a horizontal synchronizing pulse DENB_H and a vertical synchronizing pulse DENB_V in the H / V detection circuit 16 and supplied to the timing generation circuit 17. Then, the timing generation circuit 17 detects a horizontal synchronization timing and a vertical synchronization timing from the horizontal synchronization pulse DENB_H and the vertical synchronization pulse DENB_V, generates various timing signals based on these detection timings, and gives the timing signals to the respective circuit units. .
[0035]
As described above, the data enable signal DENB is separated into the horizontal synchronization pulse DENB_H and the vertical synchronization pulse DENB_V by the H / V detection circuit 16, and the timings of the horizontal synchronization and the vertical synchronization are determined from the horizontal synchronization pulse DENB_H and the vertical synchronization pulse DENB_V. By detecting, the peripheral drive circuit can be designed without fixing the back porch during the blanking period.
[0036]
The reference voltage generation circuit 18 is provided in association with the adoption of the reference voltage selection type in the DA conversion circuit 134, and has a level corresponding to the number of bits of the digital display data input to the DA conversion circuit 134. A reference voltage for the number of tones is generated and supplied to the DA conversion circuit 134. The Vcom / CS driver 16 generates a common potential Vcom and a CS potential, and applies these potentials to each pixel of the pixel unit 12 in common. As described above, in the case of employing the common inversion drive, the Vcom / CS driver 16 performs a drive that inverts the polarities of the common potential Vcom and the CS potential at a constant period.
[0037]
Here, the reference voltage generation circuit 18 and the DA conversion circuit 134 will be described in more detail.
[0038]
FIG. 7 is a circuit diagram showing an example of a specific configuration of the reference voltage generation circuit 18. As is apparent from FIG. 7, the reference voltage generation circuit 18 has a configuration including a resistance division (resistance division) circuit. That is, as an example, when the number of gradations is 64, the voltage between the first reference potential VA and the second reference potential VB is divided by 63 resistors R1 to R63 connected in series. Thereby, 62 reference voltages V1 to V62 are obtained from each voltage dividing point. By setting the reference potential VA to the reference voltage V0 and the reference potential VB to the reference voltage V63, the reference voltage generation circuit 18 outputs the reference voltages V0 to 64 corresponding to the number of bits “6” of the digital display data. V63 is generated. These reference voltages V0 to V63 are transmitted to the DA conversion circuit 134 via reference voltage lines 31-1 to 31-64, as shown in FIG.
[0039]
As described above, the liquid crystal display device according to the present embodiment employs the AC inversion drive (1H inversion drive or 1F inversion drive) in which the polarity of the display signal is inverted at a certain cycle. For this reason, the reference voltage generation circuit 18 employs a configuration in which the switches SW1 to SW4 are turned on (closed) / off (opened) by timing pulses φ1 and φ2 generated alternately in synchronization with the AC inversion.
[0040]
In the reference voltage generation circuit 18, when the timing pulse φ1 is generated at an inversion timing with AC inversion, the switches SW1 and SW4 are turned on, so that the positive power supply voltage VCC is used as the first reference potential VA and the second reference potential VB , A negative power supply voltage VSS is provided. When the timing pulse φ2 is generated at the next inversion timing, the switches SW2 and SW3 are turned on, so that the negative power supply voltage VSS is supplied as the first reference potential VA, and the positive power supply voltage VCC is supplied as the second reference potential VB.
[0041]
FIG. 8 is a circuit diagram showing an example of a specific configuration of the DA conversion circuit 134. Here, a unit circuit of the DA conversion circuit 134 is shown. That is, the DA conversion circuit 134 is configured by providing this unit circuit corresponding to each of the signal lines 25-1 to 25-x of the pixel unit 12. Hereinafter, the configuration of the unit circuit will be described.
[0042]
As is apparent from FIG. 8, the unit circuit of the DA conversion circuit 134 includes 64 gray scale selection units 32-64 provided corresponding to the 64 reference voltages V0 to V63 generated by the reference voltage generation circuit 18. 0-32-63. Each of the gradation selection units 32-0 to 32-63 includes 64 reference voltage lines 31-1 to 31-64 (see FIG. 1) for transmitting 64 reference voltages V0 to V63, respectively. Between the output lines 33 (33-1 to 33-x) respectively connected to the signal lines 25-1 to 25-x, the number of bits (6 in this example) of the digital display data d5 to d0 is provided. The configuration is such that transistor switches, for example, MOS switches are connected in series.
[0043]
In the unit circuit of the DA conversion circuit 134 having the above configuration, each of the MOS switches of the gradation selection units 32-0 to 32-63 performs an on / off operation according to the logical state of each of the bits d5 to d0 of the digital display data. . Then, according to the logic combination of the bits d5 to d0 among the gradation selection units 32-0 to 32-63, all the MOS switches of any one of the gradation selection units are turned on, whereby 64 One of the reference voltages V0 to V63 is selected, and the corresponding signal line 25 (25-1 to 25-x) is output as an analog display signal via the output line 33 (33-1 to 33-x). Output directly to
[0044]
As described above, in the drive circuit-integrated liquid crystal display device according to the present embodiment, in the horizontal drive circuits 13A and 13B, the analog display signal output from the DA conversion circuit 134 is directly transmitted to the pixel unit 12 without using a buffer. A configuration for writing to the signal lines 25-1 to 25-x is employed. As described above, by adopting a configuration in which a buffer is not provided at a subsequent stage of the DA conversion circuit 134, power consumption can be reduced by the power consumed by the buffer, and the horizontal drive circuit 13A can be reduced by the amount of the buffer omitted. , 13B can be reduced, so that the frame size on the upper and lower sides of the pixel unit 12 can be reduced.
[0045]
By the way, in order to write a desired potential to each of the signal lines 25-1 to 25-x of the pixel unit 12 without passing through a buffer, the reference voltages V0 to V63 are applied from the reference voltage generation circuit 18 to the DA conversion circuit 134. Since it is necessary to reduce the impedance of the reference voltage lines 31-1 to 31-64 to be transmitted, the reference voltage lines 31-1 to 31-64 are wired in a pattern as thick as possible. As a result, the layout area of the 64 reference voltage lines 31-1 to 31-64 increases.
[0046]
However, in the drive circuit-integrated liquid crystal display device according to the present embodiment, the interface circuit 15 and the timing generation circuit 17 which are conventionally arranged on the frame on the reference voltage generation circuit 18 side are replaced with the reference voltage generation circuit with the pixel portion 12 interposed therebetween. 18, that is, in the frame on the side of the vertical drive circuit 14, and a configuration in which the layout space for the reference voltage lines 31-1 to 31-64 is sufficiently ensured is adopted. An increase in the frame size on the reference voltage generating circuit 18 side due to the wirings 1-31 to 64 can be minimized.
[0047]
Regarding the layout of the interface circuit 15 and the timing generation circuit 17 in the frame on the side of the vertical drive circuit 14, the interface circuit 15 is disposed closer to the input pad 28 than the timing generation circuit 17, preferably, closer to the input pad 28. According to this, the master clock MCK, the horizontal synchronizing pulse Hsync, the vertical synchronizing pulse Vsync, the display data Data, the data enable signal DENB, and other rounded waveforms of the control pulse are input to the interface circuit 15 from outside the glass substrate 11. Can be avoided.
[0048]
Further, the H / V synchronization detection circuit 16 and the timing generation circuit 17 are preferably arranged near the interface circuit 15. By arranging the H / V synchronization detection circuit 16 and the timing generation circuit 17 near the interface circuit 15, it is possible to suppress a capacitance component and a resistance component associated with wiring routing, thereby causing waveform blunting and the like caused by the components. Without this, the master clock MCK level-shifted by the interface circuit 15 can be supplied to the timing generation circuit 17 and the horizontal synchronization pulse Hsync, the vertical synchronization pulse Vsync, and the data enable signal DENB can be supplied to the H / V synchronization detection circuit 16.
[0049]
The Vcom / CS driver 19 is arranged in the frame on the reference voltage generation circuit 18 side in the drive circuit integrated type liquid crystal display device according to the present embodiment.
However, the layout of the Vcom / CS driver 19 is not limited to the reference voltage generation circuit 18 side, and the reference voltage generation is performed so that the right and left frame sizes of the pixel unit 12 associated with the layout of each drive circuit become substantially equal. What is necessary is just to select whether to arrange on the circuit 18 side or the vertical drive circuit 14 side.
[0050]
The liquid crystal display device according to the present embodiment described above is suitable for use as a screen display unit of a small and lightweight portable terminal represented by a mobile phone or a PDA.
[0051]
In the present embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a display element of a pixel has been described as an example. However, the present invention is not limited to the application to a liquid crystal display device. The present invention can be applied to all flat panel display devices using a digital interface drive circuit including a reference voltage selection type DA conversion circuit as a horizontal drive circuit, such as an EL display device using an electroluminescence (EL) element as a display element. .
[0052]
FIG. 9 is an external view schematically showing the configuration of a portable terminal, for example, a PDA according to the present invention.
[0053]
The PDA according to the present example has, for example, a foldable configuration in which a lid 62 is provided on an apparatus main body 61 so as to be freely opened and closed. On the upper surface of the apparatus main body 61, an operation unit 63 in which various keys such as a keyboard are arranged is arranged. On the other hand, a screen display unit 64 is arranged on the lid 62. As the screen display unit 64, the drive circuit integrated type liquid crystal display device according to the above-described embodiment is used.
[0054]
As described above, the drive-circuit-integrated liquid crystal display device according to the present embodiment eliminates the buffer at the subsequent stage of the reference voltage selection type D / A conversion circuit, thereby suppressing the increase in the frame size of the display panel and reducing the consumption of the display panel. Since the power consumption can be reduced by the amount of power consumed, by mounting the liquid crystal display device as the screen display unit 64, the power consumption of the screen display unit 64 is reduced and the continuous use time by the battery power source is extended. be able to.
[0055]
Here, the case where the present invention is applied to a PDA has been described as an example. However, the present invention is not limited to this application example, and a display device represented by a liquid crystal display device according to the present invention is particularly small-sized, such as a mobile phone. It is suitable for use in general lightweight portable terminals.
[0056]
【The invention's effect】
As described above, according to the present invention, in a display device using a reference voltage selection type DA conversion circuit, a buffer at a subsequent stage of the DA conversion circuit is omitted and a display signal is directly transmitted to a signal line of a pixel portion. By writing, the reference voltage generation circuit is arranged on the frame opposite to the vertical drive circuit across the pixel part, and the interface circuit and the timing generation circuit are arranged on the vertical drive circuit side, so that the buffer is omitted. Even if the power consumption is reduced and the layout area of the reference voltage lines increases with the omission of the buffer, it is possible to minimize the increase in the frame of the display panel.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a drive circuit integrated type liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a configuration of a pixel circuit.
FIG. 3 is a timing chart showing a timing relationship when a setting of a blanking period is not changed using a data enable signal DENB.
FIG. 4 is a timing chart showing a timing example in a SYNC mode.
FIG. 5 is a timing chart showing an example of vertical timing in a DENB mode.
FIG. 6 is a timing chart showing an example of horizontal timing in the DENB mode.
FIG. 7 is a circuit diagram showing an example of a specific configuration of a reference voltage generation circuit.
FIG. 8 is a circuit diagram showing an example of a specific configuration of a unit circuit of the DA conversion circuit.
FIG. 9 is an external view schematically showing a configuration of a PDA according to the present invention.
FIG. 10 is a block diagram showing a configuration example of a drive circuit integrated type display device according to a conventional example.
FIG. 11 is a block diagram illustrating an example of a configuration of a horizontal drive circuit in a drive circuit integrated type display device according to a conventional example.
[Explanation of symbols]
11: glass substrate, 12 pixel portions, 13A, 13B: horizontal drive circuit, 14: vertical drive circuit, 15: interface circuit, 16: H / V synchronization detection circuit, 17: timing generation circuit, 18: reference voltage generation circuit, 19: Vcom / CS driver, 20: pixel, 21: TFT (thin film transistor), 22: liquid crystal cell, 23: storage capacitor, 24, 24-1 to 24-y: scanning line (gate line), 25, 25-1 25-x: signal line (source line), 31-1 to 31-64: reference voltage line

Claims (5)

A pixel portion in which pixels are arranged in a matrix,
A vertical drive circuit for selecting each pixel of the pixel unit on a row-by-row basis;
A reference voltage generation circuit that generates a plurality of reference voltages;
A digital-to-analog conversion circuit that selects a reference voltage corresponding to digital display data from the plurality of reference voltages, and applies the reference voltage selected by the DA conversion circuit to each pixel in a row selected by the vertical drive circuit; A horizontal drive circuit for supplying as an analog display signal;
An interface circuit that performs level conversion of a signal input from outside the transparent insulating substrate,
A timing generation circuit that generates various timing signals based on the signal whose level has been converted by the interface circuit and provides the timing signals to each circuit unit,
The vertical drive circuit, the reference voltage generation circuit, and the horizontal drive circuit are formed on the same transparent insulating substrate together with the pixel portion, and the vertical drive circuit and the reference voltage generation circuit are opposite to each other across the pixel portion. A display device, wherein the interface circuit and the timing generation circuit are disposed on the vertical drive circuit side. The pixel portion, the vertical drive circuit, the reference voltage generation circuit, the horizontal drive circuit, the interface circuit, and the timing generation circuit are formed on the transparent insulating substrate using low-temperature polysilicon or continuous grain silicon. The display device according to claim 1, wherein: The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell. A pixel portion in which pixels are arranged in a matrix,
A vertical drive circuit for selecting each pixel of the pixel unit on a row-by-row basis;
A reference voltage generation circuit that generates a plurality of reference voltages;
A digital-to-analog conversion circuit that selects a reference voltage corresponding to digital display data from the plurality of reference voltages, and applies the reference voltage selected by the DA conversion circuit to each pixel in a row selected by the vertical drive circuit; A horizontal drive circuit for supplying as an analog display signal;
An interface circuit that performs level conversion of a signal input from outside the transparent insulating substrate,
A timing generation circuit that generates various timing signals based on the signal whose level has been converted by the interface circuit and provides the timing signals to each circuit unit,
The vertical drive circuit, the reference voltage generation circuit, and the horizontal drive circuit are formed on the same transparent insulating substrate together with the pixel portion, and the vertical drive circuit and the reference voltage generation circuit are opposite to each other across the pixel portion. A portable device comprising a display device disposed on the side of the vertical drive circuit and having the interface circuit and the timing generation circuit disposed on the vertical drive circuit side as a screen display unit. The mobile terminal according to claim 4, wherein the display device is a liquid crystal display device using a liquid crystal cell as a display element of the pixel.

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