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JP2004214374A - Semiconductor device and liquid-crystal display panel - Google Patents

Semiconductor device and liquid-crystal display panel Download PDF

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Publication number
JP2004214374A
JP2004214374A JP2002381347A JP2002381347A JP2004214374A JP 2004214374 A JP2004214374 A JP 2004214374A JP 2002381347 A JP2002381347 A JP 2002381347A JP 2002381347 A JP2002381347 A JP 2002381347A JP 2004214374 A JP2004214374 A JP 2004214374A
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Prior art keywords
bump
semiconductor element
bumps
conductive particles
semiconductor device
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JP2002381347A
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JP4115832B2 (en
Inventor
Makoto Nitta
誠 新田
Hikari Fujita
光 藤田
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Japan Display Central Inc
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Toshiba Matsushita Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

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  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which sections among bumps formed to the semiconductor device are not short-circuited, in the face-down mounted semiconductor device and a liquid-crystal display panel. <P>SOLUTION: In the semiconductor device 20 having the bumps 10 as projecting electrodes on a mounting surface as input/output terminals and being mounted by an anisotropic conductive film 5, an insulating film 13 is formed to side faces 3a in which the top faces 3b of the bump layers 3 of the bumps 10 are removed, and the mounting surface 20a of the semiconductor device 20. The device 20 is mounted on a substrate 21 for the liquid-crystal display panel by a contact bonding by a heating through the anisotropic conductive film 5 having conductive particles 6. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、フェースダウン実装される半導体素子、特に液晶表示パネルの一方の基板にＣＯＧ実装される半導体素子及び液晶表示パネルに関する。
【０００２】
【従来の技術】
液晶表示装置は、液晶層を狭持する一対のガラス基板に形成された電極を半導体素子により制御し、液晶の電気光学効果を利用して表示される。半導体素子の電気的接続方法としては、例えば、ゴムコネクション法、ヒートシール法、ＴＡＢ（ｔａｐｅ ａｕｔｏｍａｔｅｄ ｂｏｎｄｉｎｇ）法、ＣＯＧ（ｃｈｉｐ ｏｎ ｇｌａｓｓ）法等の提案がされているが、今日では、実装工程の自動化およびプロセススループットの観点からＴＡＢ法とＣＯＧ法が主流となっており、装置の小型化及び薄型化の観点から特に、ＣＯＧ法が重要視されている。
【０００３】
図４は、従来の半導体素子２０に形成したバンプ１０の模式図である。半導体素子２０の表面にアルミニウム等により形成された電極パッド１上に、シリコンナイトライド（Ｓｉ３Ｎ４）等からなるパッシベーション層２が形成されている。パッシベーション層２には開口部２ａが設けられており、電極パッド１上にスパッタリング、メッキもしくはボンディングツール等によりバンプ層３を形成し、開口部２ａを介して電極パッド１とバンプ層３とが導通される。バンプ層３は、主に金で形成され、この電極パッド１、パッシベーション層２及びバンプ層３によりバンプ１０が形成されている。また、パッシベーション層２表面を保護するため、バンプ１０周辺を除き、ポリイミド膜１２が形成されている。
【０００４】
一般的に、ＣＯＧ法による半導体素子２０の接続は図５に示される構造となっている。ＣＯＧ法は、一対のガラス基板の一方の基板２１に半導体素子２０をフェースダウンにて直接実装する方法である。ＣＯＧ法では、半導体素子２０のバンプ１０と基板２１に形成された電極端子４とを対向させて、異方性導電膜（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ；ＡＣＦ）５を介して加熱圧着により実装する方法が配線のファインピッチ化や実装による歩留まり性能の点等から採用されるのがほとんどである。異方性導電膜５は、樹脂製の接着剤に導電粒子６を分散させたものであり、加熱及び加圧により、半導体素子２０のバンプ１０と基板２１上の電極端子４との間に、導電粒子６が挟まれて接触することによって、電気的導通が得られる。このとき、バンプ１０と電極端子４とで挟まれることによって導電粒子６がつぶれ、この状態で固定することにより、導電粒子６が弾力性を持ってバンプ１０と電極端子４とに密着し、導通状態が安定的に保持される。ここで、導電粒子６は、直径３μｍのポリスチレン粒子表面に厚さ約０．１μｍのニッケルめっきを施したものである。一方、導電粒子６が挟まれることにより、バンプ１０は、めり込むように変形し、導電粒子６とバンプ１０とが密着することとなる。このため、バンプ層３の材料には通常、変形しやすい金が使用され、また、変形分を考慮して所定の高さとなるように形成される。
【０００５】
【発明が解決しようとする課題】
隣接するバンプ１０間において、導電粒子６が接触して連なった場合、この導電粒子６の連なりを原因として導通してショートしてしまうことがある。導電粒子６が連なった状態とは、バンプ１０と電極端子４とに挟まれた導電粒子６に周辺の導電粒子６が連なる場合のみならず、図５右側に示されるように、バンプ層３の側面３ａに導電粒子６が連なって接触する場合も含まれ、ショートの原因となる。上述したように、バンプ１０は導電粒子６を挟むことによる変形分を考慮した高さとなっているため、バンプ層３の側面３ａに導電粒子６が接触することは多く、それに伴ってバンプ層３の側面３ａに連なった導電粒子６が接触することも多かった。また近年、液晶表示装置の狭額縁化による半導体素子２０の小型化及び配線の狭ピッチ化に伴い、隣接するバンプ１０間が狭くなる傾向にあるため、このような導電粒子６の連なりによるショートの危険性は高くなっていた。
【０００６】
また、バンプ１０は様々な形状の層が重ねられた層構造であるため、その表面形状は凹凸ができている。図５左側に示すようにこの凹部１０ａに導電粒子６が引っかかったり（時には凹部１０ａにはまり込んだり）、図５中央に示すように凹部１０ａに異方性導電膜５が入り込まずに気泡１４ができたりすることもある。特に、このバンプ１０表面の凹凸形状により異方性導電膜５が偏ってしまうと、導電粒子６も偏ることとなり、特定の場所に偏った導電粒子６が連なることにより、ショートする危険性もあった。
【０００７】
上記の導電粒子６の連なりによるショートを防止するためには、様々な方法が採られてきた。まず、異方性導電膜５の導電粒子６の密度を低くする方法が考えられる。しかし、半導体素子２０をＣＯＧ法により異方性導電膜５を用いて実装する際、バンプ１０と電極端子４とを確実に導通させるためには、ある程度の数量の導電粒子６をバンプ１０と電極端子４との間に挟み込む必要がある。例えば、液晶表示装置に使用される一般的な駆動用の半導体素子においては、径が３〜５μｍ程度の一般的な導電粒子６を用いる場合、一箇所の接続部分（上記半導体素子２０ではバンプ１０の先端接触面３ｂに）において４〜８個程度の導電粒子６を少なくとも挟み込む必要がある。特に、半導体素子２０の小型化に伴い、バンプ１０は小型化される傾向にあるため、上記のように導電粒子６の密度を低くすると所定数量の導電粒子６を挟み込めないこととなり、導通不良が多数検出され、歩留まりの低下につながっていた。
【０００８】
他の方法として、導電粒子６の径を小さくする方法が考えられる。しかし、バンプ１０は、一般的に高さのバラツキ（公差）があり、導電粒子６のつぶれ度合いやバンプ１０の変形（めり込み）度合いによってこの高さのバラツキを吸収しているため、導電粒子６の径が小さくなると、この高さのバラツキを吸収し難くなる。これにより、導電粒子６がバンプ１０と電極端子４との間に有効に挟まれなくなり、導通不良となっていた。
【０００９】
また、絶縁コートした導電粒子６を使用する方法も考えられるが、導電方向についてこの絶縁コートを破壊する必要があるため、絶縁コートのない導電粒子６の接続時に比べて加圧力を大きくしなければならない。すなわち、所定の接続信頼性を得るための実装条件が厳しくなる分、絶縁コートが十分に破壊されないことによる導通不良が検出される確率も高くなっていた。
【００１０】
そこで、本発明の目的は、フェースダウンにより実装される半導体素子において、バンプが小型化及び狭ピッチ化しても隣接するバンプ間がショートすることのない半導体素子及び液晶表示パネルを提供することを目的とする。
【００１１】
【課題を解決するための手段】
上記課題を解決するために、本発明の請求項１記載の半導体素子は、凸状の電極であるバンプを有し、この凸状のバンプを有する実装面を電極端子が形成された実装用基板に向けて異方性導電膜を使用して実装し、異方性導電膜の導電粒子を介して凸状のバンプの先端接触面と電極端子とを導通させる半導体素子において、上記凸状のバンプの側面に絶縁膜が形成されていることを特徴とする。
【００１２】
この発明によれば、上記凸状のバンプの側面に絶縁膜が形成されていることから、隣接するバンプ間において異方性導電膜中の導電粒子が連なったとしても、バンプ側面の絶縁膜によって隣接するバンプ間におけるショートが防止される。
【００１３】
本発明の請求項２記載の半導体素子は、請求項１記載の発明を前提として、前記絶縁膜は、前記凸状のバンプの先端接触面を除き、半導体素子のバンプを有する面の全体に形成されていることを特徴とする。
【００１４】
この発明によれば、絶縁膜が、バンプの先端接触面を除き、半導体素子のバンプを有する面の全体に形成されているため、半導体素子の実装面すなわち他の実装用基板等に対向する面が、バンプの先端接触面を除いた全体が滑らかな絶縁膜面となる。これにより、半導体素子を実装する際に流動性を持った異方性導電膜が、バンプの先端接触面すなわちバンプにて挟まれる部分を除いて、滑らかに移動することとなり、異方性導電膜（特に導電粒子）が偏ることなく半導体素子の実装面の全体に均一に行き渡ることとなり、異方性導電膜の偏りによる気泡もできにくくなる。
【００１５】
本発明の請求子３記載の半導体素子の実装構造は、液晶を挟持する一対の基板の一方の基板を実装用基板として、この実装用基板の電極端子に請求項１又は請求項２のいずれかに記載の半導体素子を導電粒子を有する異方性導電膜を介して加熱圧着より実装させていることを特徴とする。
【００１６】
この発明によれば、請求項１又は請求項３記載の半導体素子を液晶表示パネルの一方の実装用基板に異方性導電膜を介して実装するに際して、隣接するバンプ間において導電粒子の連なりによってショートすることなく、実装用基板と半導体素子とが導電粒子を介して安定的に導通する実装構造の液晶表示パネルとなる。
【００１７】
【発明の実施の形態】
以下、本発明の実施の形態を図面を引用しながら説明する。
【００１８】
図１（ａ）は、本実施の形態の半導体素子の構造図、図１（ｂ）は、本実施の形態の半導体素子を液晶表示パネルの一方の基板に実装した図を示す。図１（ａ）に示される半導体素子２０は、液晶表示パネルの表示を制御する電子素子であり、表面にバンプ１０が形成される。バンプ１０は、半導体素子２０への入出力電極の役割を果たす突起状（凸状）の電極であり、少なくとも入出力信号の数が実装面２０ｂに形成されている。図１（ｂ）に示されるように、液晶表示パネルは文字及び映像を表示するもので、表示用電極（図示せず）が敷設された一対の透明基板２１，２２を適宜な間隔で対峙させ、その間隔に液晶材料（図示せず）を注入し、前記透明基板２１，２２の周辺をシール材（図示せず）で封止して構成される。一対の透明基板２１，２２のうち、一方の基板２１は他方の基板２２より広く形成され、重ね合わせたときに外側に張り出す部分に金属製の配線パターン９が所定の形状で施され、この配線パターン９と本実施の形態の半導体素子２０とを電気的に導通させる。すなわち、配線パターン９の接続箇所（後述する電極端子４）に半導体素子２０のバンプ１０を有する実装面２０ｂを向けて、異方性導電膜５を介して実装される。なお、半導体素子２０等の駆動回路が施された回路基板（図示せず）が、基板２１のさらに外側に設けられ、フレキシブル配線基板（図示せず）を介して回路基板と基板２１とが接続される場合もある。
【００１９】
図２は、接続パッド１０を半導体素子２０の表面に作製する手順を示す。１１は、シリコン等の基板に所定の回路、配線及び層間絶縁膜等が作製されたウェハーである。まず、ウェハー１１の表面にアルミニウム等の電極パッド膜１を一様の厚さで形成する（図２（ａ））。次に、フォトリソグラフィーにより所定の形状のマスクパターンを形成し、エッチング等により電極パッド１を形成する（図２（ｂ））。次に、シリコンナイトライド（Ｓｉ３Ｎ４）等のパッシベーション層２を形成し（図２（ｃ））、フォトリソグラフィーにより、開口部２ａの形状のマスクパターンを形成して、エッチングにより電極パッド１の上に開口部２ａを設ける（図２（ｄ））。
【００２０】
次いで、図２（ｅ）に示すように、開口部２ａ周辺を残して表面保護のためにポリイミド膜１２を形成する。その後、電極パッド１上にスパッタリング、メッキもしくはボンディングツール等によりバンプ層３を形成し、開口部２ａを介して電極パッド１とバンプ層３とが導通される（図２（ｆ））。バンプ層３は、主に金で形成され、この電極パッド１、パッシベーション層２及びバンプ層３によりバンプ１０が形成される。次に、ウェハー１１の表面全体に、窒化膜（ＳｉＮｘ）からなる絶縁膜１３を形成する（図２（ｇ））。その後、フォトリソグラフィー及びエッチングにより、バンプ層３周辺の絶縁膜１３の高さがバンプ層３の表面（先端接触面）３ｂの高さとなるように、また、バンプ層３の表面が開口するように、絶縁膜１３を整形する（図２（ｈ））。本実施の形態において、絶縁膜１３として窒化膜を使用したが、本発明はこれを限定するものではなく、例えば、シリコン酸化膜（ＳｉＯ２）を使用してもよく、より低温で成膜できる材料を選択することが好ましい。
【００２１】
ここで、異方性導電膜５の導電粒子６の捕捉率を高めるために、絶縁膜１３の高さをバンプ１０の先端接触面３ｂの高さよりも若干高く形成しても良い。この場合において、絶縁膜１３を、材質がバンプ１０よりも柔らかい材質（すなわち実装時においてバンプ１０よりも潰れ具合の大きい材質）によることとして、その若干高く形成した部分が加熱圧着による際に潰れて、バンプ層３の表面（先端接触面）３ｂの高さとなるようにして、いわゆる平行度を出すようにしても良い。図６（ａ）に示されるように、絶縁膜１３をバンプ１０の先端接触面３ｂを覆わないようにこれより高くする場合、絶縁膜１３はスピンコーターによって塗布することが好ましい。また、図６（ｂ）に示されるように、絶縁膜１３をバンプの先端接触面３ｂを一部覆うようにこれより高くする場合は、図２（ｇ）において、絶縁膜１３の開口がバンプ先端接触面３ｂより若干小さくなるようにエッチングすれば、絶縁膜１３の膜厚の分だけ容易に高くすることができる。さらに、図６（ｃ）に示されるように、ポリイミド膜１２をバンプ層３の外周側面３ａに形成させることで絶縁膜１３の機能を兼務させてもよい。また、凸状のバンプ１０の先端接触面３ｂを開口させて、バンプ層３の外周側面３ａに絶縁膜１３（あるいはポリイミド膜１２）が形成されていれば、半導体素子２０の実装面２０ｂの全体に絶縁膜１３が形成されていなくとも、導電粒子６の連なりによるショートが防止される。
【００２２】
以上の方法にて接続パッド１０が作製されたウェハー１１は、所定の形状にダイシングされ、半導体素子２０が得られる。
【００２３】
次に、上記のように製造された半導体素子２０を実装用基板２１に実装する実装構造を説明する。半導体素子２０は、ＣＯＧ法によりフェースダウン実装される。実装用基板２１の表面には、図３に示すように、配線パターン９の接続箇所に所定形状で電極端子４が形成され、半導体素子２０の実装される部分に異方性導電膜５を塗布し、半導体素子２０を位置合わせして裏面（図４において上側）から加圧しながら加熱する。このとき、図３右側に示されるように、連なった導電粒子６がバンプ１０の側面方向から接触しても、バンプ層３の側面３ａは、絶縁膜１３で覆われているため、隣接するバンプ１０とショートすることがない。
【００２４】
また、絶縁膜１１は、バンプ１０の上面を除き半導体素子２０の表面全体に膜形成されているため、層構造によるバンプ１０の表面凹凸形状が、絶縁膜１１により滑らかに覆われていることとなる。すなわち、半導体素子２０の実装面において、バンプ１０の上面（先端接触面）３ｂを除いた全体が滑らかになっているため、加熱により流動性を持った異方性導電膜５が半導体素子２０の実装面上を滑らかに移動することとなる。これにより、異方性導電膜５が偏ることなく半導体素子２０の実装面全体に行き渡ることとなり、異方性導電膜５の流れが阻害されることによる気泡もできにくくなる。特に、異方性導電膜５の滑らかな移動に伴って、導電粒子６の偏り、すなわち導電粒子６の連なりも起こりにくくなる。
【００２５】
以上、本実施の形態においては、半導体素子２０を液晶表示パネルに使用される実装用基板２１に実装する例で説明したが、本発明はこれに限らず、フェースダウン実装する半導体素子２０及びその実装構造であれば、広く適用可能である。
【００２６】
【発明の効果】
本発明の半導体素子は、まず、凸状のバンプの側面に絶縁膜を形成することにより、隣接するバンプ間において異方性導電膜中の導電粒子が連なったとしても、バンプ側面の絶縁膜によって隣接するバンプ間におけるショートが防止される。また、バンプ側面のみならず、バンプの先端接触面を除き、半導体素子のバンプを有する面の全体に絶縁膜を形成することにより、半導体素子の実装面全体（バンプの先端接触面を除く）が滑らかな絶縁膜面となる。これにより、異方性導電膜（特に導電粒子）が偏ることなく半導体素子の実装面の全体に均一に行き渡ることとなり、導電粒子の連なりが起こりにくくなることで、さらに隣接するバンプ間におけるショートの防止が図られる。また、異方性導電膜の偏りによる気泡の発生が防止されることとなる。また、本発明の液晶表示パネルによれば、隣接するバンプ間において、導電粒子の連なりによるショートが防止される構造となるため、バンプが小型化及び狭ピッチ化しても隣接するバンプ間がショートすることがなく、実装用基板と半導体素子とが安定的に導通することとなり、液晶表示パネルの信頼性の向上が図られる。
【００２７】
【図面の簡単な説明】
【図１】（ａ）は本発明の半導体素子の構造図、（ｂ）は本発明の半導体素子を液晶表示パネルに実装した構成図
【図２】本発明の実施の形態における半導体素子のバンプを形成する説明図
【図３】本発明の半導体素子と液晶表示パネルの接続断面図
【図４】従来のバンプの構造図
【図５】従来の半導体素子と液晶表示パネルの接続断面図
【図６】（ａ）は、本発明のバンプの別の例を示す構造図、（ｂ）は、本発明のバンプのさらに別の例を示す構造図、（ｃ）は、本発明のバンプのさらに別の例を示す構造図
【符号の説明】
１ 電極パッド
２ パッシベーション層
２ａ 開口部
３ バンプ層
３ａ バンプの側面
３ｂ バンプの上面（先端接触面）
４ 電極端子
５ 異方性導電膜
６ 導電粒子
９ 配線パターン
１０ バンプ
１０ａ 凹部
１１ ウェハー
１２ ポリイミド膜
１３ 絶縁膜
１４ 気泡
２０ 半導体素子
２０ｂ 半導体素子の実装面（バンプを有する面）
２１ 一方の基板（実装用基板）
２２ 他方の基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element mounted face down, in particular, a semiconductor element mounted on one substrate of a liquid crystal display panel by COG and a liquid crystal display panel.
[0002]
[Prior art]
In a liquid crystal display device, an electrode formed on a pair of glass substrates sandwiching a liquid crystal layer is controlled by a semiconductor element, and a display is performed using an electro-optic effect of liquid crystal. As an electrical connection method of the semiconductor element, for example, a rubber connection method, a heat sealing method, a TAB (tape automated bonding) method, a COG (chip on glass) method, and the like have been proposed. The TAB method and the COG method are predominant from the viewpoint of automation and process throughput, and the COG method is particularly important from the viewpoint of reducing the size and thickness of the apparatus.
[0003]
FIG. 4 is a schematic view of the bump 10 formed on the conventional semiconductor element 20. A passivation layer 2 made of silicon nitride (Si 3 N 4 ) or the like is formed on an electrode pad 1 made of aluminum or the like on the surface of the semiconductor element 20. An opening 2a is provided in the passivation layer 2. A bump layer 3 is formed on the electrode pad 1 by sputtering, plating, a bonding tool, or the like, and the electrode pad 1 and the bump layer 3 are conducted through the opening 2a. Is done. The bump layer 3 is mainly formed of gold, and a bump 10 is formed by the electrode pad 1, the passivation layer 2, and the bump layer 3. In order to protect the surface of the passivation layer 2, a polyimide film 12 is formed except for the periphery of the bump 10.
[0004]
Generally, the connection of the semiconductor element 20 by the COG method has a structure shown in FIG. The COG method is a method in which the semiconductor element 20 is directly mounted face down on one substrate 21 of a pair of glass substrates. In the COG method, a method in which bumps 10 of a semiconductor element 20 and electrode terminals 4 formed on a substrate 21 are opposed to each other and mounted by heat compression through an anisotropic conductive film (ACF) 5 is used. In most cases, it is adopted from the viewpoint of fine pitch and yield performance by mounting. The anisotropic conductive film 5 is obtained by dispersing conductive particles 6 in an adhesive made of a resin, and is heated and pressed between the bumps 10 of the semiconductor element 20 and the electrode terminals 4 on the substrate 21. When the conductive particles 6 are sandwiched and come into contact with each other, electrical continuity is obtained. At this time, the conductive particles 6 are crushed by being sandwiched between the bumps 10 and the electrode terminals 4. By fixing the conductive particles 6 in this state, the conductive particles 6 adhere to the bumps 10 and the electrode terminals 4 elastically, and The state is stably maintained. Here, the conductive particles 6 are obtained by applying nickel plating having a thickness of about 0.1 μm to the surface of polystyrene particles having a diameter of 3 μm. On the other hand, when the conductive particles 6 are sandwiched, the bumps 10 are deformed so as to be embedded, and the conductive particles 6 and the bumps 10 adhere to each other. For this reason, the material of the bump layer 3 is usually formed of gold which is easily deformable, and is formed to have a predetermined height in consideration of the amount of deformation.
[0005]
[Problems to be solved by the invention]
When the conductive particles 6 are in contact with each other and are connected between the adjacent bumps 10, conduction may occur due to the connection of the conductive particles 6 and a short circuit may occur. The state in which the conductive particles 6 are connected means not only the case where the conductive particles 6 sandwiched between the bump 10 and the electrode terminal 4 are connected with the conductive particles 6 in the vicinity, but also as shown in the right side of FIG. This includes a case where the conductive particles 6 are continuously contacted with the side surface 3a, which causes a short circuit. As described above, since the bump 10 has a height in consideration of the amount of deformation caused by sandwiching the conductive particles 6, the conductive particles 6 often come into contact with the side surface 3 a of the bump layer 3. In many cases, the conductive particles 6 connected to the side surface 3a contacted. Further, in recent years, with the miniaturization of the semiconductor element 20 and the narrower pitch of the wiring due to the narrower frame of the liquid crystal display device, the interval between adjacent bumps 10 tends to be narrower. The danger was higher.
[0006]
Further, since the bump 10 has a layer structure in which layers of various shapes are stacked, the surface shape is uneven. As shown on the left side of FIG. 5, the conductive particles 6 are caught in the concave portion 10a (and sometimes stuck in the concave portion 10a), and as shown in the center of FIG. Sometimes you can. In particular, if the anisotropic conductive film 5 is biased due to the uneven shape of the surface of the bump 10, the conductive particles 6 are also biased, and the conductive particles 6 biased to a specific place are connected to each other. Was.
[0007]
Various methods have been employed to prevent short-circuiting due to the series of conductive particles 6 described above. First, a method of reducing the density of the conductive particles 6 of the anisotropic conductive film 5 can be considered. However, when the semiconductor element 20 is mounted using the anisotropic conductive film 5 by the COG method, a certain number of conductive particles 6 must be added to the bump 10 and the electrode 10 in order to ensure conduction between the bump 10 and the electrode terminal 4. It must be sandwiched between the terminal 4. For example, in a general driving semiconductor element used for a liquid crystal display device, when a general conductive particle 6 having a diameter of about 3 to 5 μm is used, one connection portion (a bump 10 in the semiconductor element 20) is used. It is necessary to sandwich at least about 4 to 8 conductive particles 6 in the tip contact surface 3b). In particular, since the bumps 10 tend to be miniaturized with the miniaturization of the semiconductor element 20, if the density of the conductive particles 6 is reduced as described above, a predetermined number of the conductive particles 6 cannot be interposed, resulting in poor conduction. Was detected in large numbers, leading to a decrease in yield.
[0008]
As another method, a method of reducing the diameter of the conductive particles 6 can be considered. However, the bumps 10 generally have variations in height (tolerance), and the bumps 10 absorb the variations in height due to the degree of crushing of the conductive particles 6 and the degree of deformation (indentation) of the bumps 10. When the diameter is small, it becomes difficult to absorb the variation in height. As a result, the conductive particles 6 were not effectively sandwiched between the bumps 10 and the electrode terminals 4, resulting in poor conduction.
[0009]
In addition, a method of using the conductive particles 6 coated with an insulating layer is also conceivable. However, it is necessary to break the insulating layer in the conductive direction. No. That is, as the mounting conditions for obtaining the predetermined connection reliability become stricter, the probability of detecting a conduction failure due to insufficient breakdown of the insulating coat has been increased.
[0010]
Accordingly, an object of the present invention is to provide a semiconductor element and a liquid crystal display panel in which adjacent bumps are not short-circuited even if the bumps are reduced in size and narrowed in pitch, in a semiconductor element mounted face-down. And
[0011]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor element according to claim 1 of the present invention has a bump which is a convex electrode, and a mounting surface having the convex bump has a mounting surface on which an electrode terminal is formed. A semiconductor element mounted using an anisotropic conductive film toward the semiconductor device and electrically connecting a contact end surface of the convex bump to an electrode terminal via conductive particles of the anisotropic conductive film. Is characterized in that an insulating film is formed on the side surface of.
[0012]
According to the present invention, since the insulating film is formed on the side surface of the convex bump, even if the conductive particles in the anisotropic conductive film are connected between the adjacent bumps, the insulating film on the side surface of the bump is used. Short circuit between adjacent bumps is prevented.
[0013]
In the semiconductor device according to a second aspect of the present invention, based on the premise of the first aspect, the insulating film is formed on the entire surface of the semiconductor element having the bumps, except for the tip contact surface of the convex bump. It is characterized by having been done.
[0014]
According to the present invention, since the insulating film is formed on the entire surface of the semiconductor element having the bumps, except for the tip contact surface of the bump, the semiconductor element mounting surface, that is, the surface facing the other mounting substrate or the like However, the entire surface except for the contact surface at the tip of the bump becomes a smooth insulating film surface. As a result, the anisotropic conductive film having fluidity when the semiconductor element is mounted moves smoothly except for the tip contact surface of the bump, that is, the portion sandwiched between the bumps. (Especially, conductive particles) are evenly distributed over the entire mounting surface of the semiconductor element without unevenness, and bubbles due to unevenness of the anisotropic conductive film are hardly generated.
[0015]
The mounting structure of a semiconductor element according to claim 3 of the present invention is characterized in that one of a pair of substrates sandwiching a liquid crystal is used as a mounting substrate, and the electrode terminal of the mounting substrate is provided as one of claims 1 and 2. Wherein the semiconductor element is mounted by thermocompression bonding via an anisotropic conductive film having conductive particles.
[0016]
According to this invention, when the semiconductor element according to claim 1 or 3 is mounted on one of the mounting substrates of the liquid crystal display panel via the anisotropic conductive film, the conductive particles are connected between the adjacent bumps. The liquid crystal display panel has a mounting structure in which the mounting substrate and the semiconductor element are stably conducted through the conductive particles without short-circuit.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1A is a structural diagram of a semiconductor element of this embodiment, and FIG. 1B is a diagram in which the semiconductor element of this embodiment is mounted on one substrate of a liquid crystal display panel. A semiconductor element 20 shown in FIG. 1A is an electronic element for controlling display of a liquid crystal display panel, and has a bump 10 formed on a surface thereof. The bump 10 is a protruding (convex) electrode serving as an input / output electrode to the semiconductor element 20, and at least the number of input / output signals is formed on the mounting surface 20b. As shown in FIG. 1B, the liquid crystal display panel displays characters and images, and a pair of transparent substrates 21 and 22 on which display electrodes (not shown) are laid face each other at appropriate intervals. A liquid crystal material (not shown) is injected into the space, and the periphery of the transparent substrates 21 and 22 is sealed with a sealing material (not shown). Of the pair of transparent substrates 21 and 22, one substrate 21 is formed wider than the other substrate 22, and a metal wiring pattern 9 is formed in a predetermined shape on a portion that protrudes outward when superimposed. The wiring pattern 9 and the semiconductor element 20 of the present embodiment are electrically connected. That is, the semiconductor element 20 is mounted via the anisotropic conductive film 5 with the mounting surface 20b having the bump 10 of the semiconductor element 20 facing the connection portion (the electrode terminal 4 described later) of the wiring pattern 9. A circuit board (not shown) on which a drive circuit such as the semiconductor element 20 is provided is further provided outside the board 21, and the circuit board and the board 21 are connected via a flexible wiring board (not shown). It may be done.
[0019]
FIG. 2 shows a procedure for forming the connection pad 10 on the surface of the semiconductor element 20. Reference numeral 11 denotes a wafer in which predetermined circuits, wirings, interlayer insulating films, and the like are formed on a substrate such as silicon. First, the electrode pad film 1 of aluminum or the like is formed on the surface of the wafer 11 with a uniform thickness (FIG. 2A). Next, a mask pattern having a predetermined shape is formed by photolithography, and the electrode pad 1 is formed by etching or the like (FIG. 2B). Next, a passivation layer 2 such as silicon nitride (Si 3 N 4 ) is formed (FIG. 2C), a mask pattern in the shape of the opening 2a is formed by photolithography, and the electrode pad 1 is etched. An opening 2a is provided on the substrate (FIG. 2D).
[0020]
Next, as shown in FIG. 2E, a polyimide film 12 is formed for surface protection while leaving the periphery of the opening 2a. Thereafter, a bump layer 3 is formed on the electrode pad 1 by sputtering, plating, a bonding tool, or the like, and the electrode pad 1 and the bump layer 3 are conducted through the opening 2a (FIG. 2 (f)). The bump layer 3 is mainly made of gold, and a bump 10 is formed by the electrode pad 1, the passivation layer 2, and the bump layer 3. Next, an insulating film 13 made of a nitride film (SiNx) is formed on the entire surface of the wafer 11 (FIG. 2G). After that, by photolithography and etching, the height of the insulating film 13 around the bump layer 3 is set to the height of the surface (tip contact surface) 3b of the bump layer 3 and the surface of the bump layer 3 is opened. Then, the insulating film 13 is shaped (FIG. 2H). In the present embodiment, a nitride film is used as the insulating film 13. However, the present invention is not limited to this. For example, a silicon oxide film (SiO 2 ) may be used, and the film can be formed at a lower temperature. It is preferable to select a material.
[0021]
Here, in order to increase the capture rate of the conductive particles 6 of the anisotropic conductive film 5, the height of the insulating film 13 may be formed slightly higher than the height of the tip contact surface 3 b of the bump 10. In this case, the insulating film 13 is made of a material that is softer than the bump 10 (that is, a material that is more crushed than the bump 10 at the time of mounting). Alternatively, the surface (tip contact surface) 3b of the bump layer 3 may be set at a height so as to provide a so-called parallelism. As shown in FIG. 6A, when the insulating film 13 is made higher than this so as not to cover the tip contact surface 3b of the bump 10, the insulating film 13 is preferably applied by a spin coater. In addition, as shown in FIG. 6B, when the insulating film 13 is made higher than this so as to partially cover the tip contact surface 3b of the bump, in FIG. If the etching is performed so as to be slightly smaller than the tip contact surface 3b, the height can be easily increased by the thickness of the insulating film 13. Further, as shown in FIG. 6C, the function of the insulating film 13 may be performed by forming the polyimide film 12 on the outer peripheral side surface 3a of the bump layer 3. If the insulating film 13 (or the polyimide film 12) is formed on the outer peripheral side surface 3a of the bump layer 3 by opening the tip contact surface 3b of the convex bump 10, the entire mounting surface 20b of the semiconductor element 20 is formed. Even if the insulating film 13 is not formed, short circuit due to the connection of the conductive particles 6 is prevented.
[0022]
The wafer 11 on which the connection pads 10 are manufactured by the above method is diced into a predetermined shape, and the semiconductor element 20 is obtained.
[0023]
Next, a mounting structure for mounting the semiconductor element 20 manufactured as described above on the mounting substrate 21 will be described. The semiconductor element 20 is mounted face down by the COG method. As shown in FIG. 3, on the surface of the mounting substrate 21, the electrode terminals 4 are formed in a predetermined shape at connection positions of the wiring patterns 9, and the anisotropic conductive film 5 is applied to a portion where the semiconductor element 20 is mounted. Then, the semiconductor element 20 is positioned and heated while being pressed from the rear surface (the upper side in FIG. 4). At this time, as shown on the right side of FIG. 3, even if the continuous conductive particles 6 come into contact from the side of the bump 10, the side 3 a of the bump layer 3 is covered with the insulating film 13, so that the adjacent bump No short circuit with 10.
[0024]
Further, since the insulating film 11 is formed on the entire surface of the semiconductor element 20 except for the upper surface of the bump 10, the surface unevenness of the bump 10 due to the layer structure is smoothly covered by the insulating film 11. Become. That is, since the entire surface of the mounting surface of the semiconductor element 20 except for the upper surface (tip contact surface) 3b of the bump 10 is smooth, the anisotropic conductive film 5 having fluidity by heating causes the It moves smoothly on the mounting surface. Accordingly, the anisotropic conductive film 5 spreads over the entire mounting surface of the semiconductor element 20 without bias, and bubbles due to obstruction of the flow of the anisotropic conductive film 5 are less likely to be generated. In particular, with the smooth movement of the anisotropic conductive film 5, the bias of the conductive particles 6, that is, the connection of the conductive particles 6 is less likely to occur.
[0025]
As described above, in the present embodiment, the example in which the semiconductor element 20 is mounted on the mounting substrate 21 used for the liquid crystal display panel has been described, but the present invention is not limited to this, and the semiconductor element 20 to be mounted face-down and its If it is a mounting structure, it can be widely applied.
[0026]
【The invention's effect】
In the semiconductor device of the present invention, first, an insulating film is formed on the side surface of a convex bump, so that even if conductive particles in an anisotropic conductive film are connected between adjacent bumps, the insulating film on the side surface of the bump is used. Short circuit between adjacent bumps is prevented. In addition, by forming an insulating film on the entire surface of the semiconductor device having the bumps, not only on the side surfaces of the bumps, but also on the contact surfaces of the bumps, the entire mounting surface of the semiconductor device (excluding the contact surfaces of the bumps) can be formed. The surface of the insulating film becomes smooth. As a result, the anisotropic conductive film (especially, conductive particles) is uniformly distributed over the entire mounting surface of the semiconductor element without being biased, and the conductive particles are less likely to be connected to each other. Prevention is achieved. Further, the generation of bubbles due to the bias of the anisotropic conductive film is prevented. Further, according to the liquid crystal display panel of the present invention, since a short circuit due to a series of conductive particles is prevented between the adjacent bumps, the adjacent bumps are short-circuited even if the bumps are reduced in size and pitch is reduced. As a result, the mounting substrate and the semiconductor element are stably conducted, and the reliability of the liquid crystal display panel is improved.
[0027]
[Brief description of the drawings]
FIG. 1A is a structural view of a semiconductor device of the present invention, and FIG. 1B is a configuration diagram of the semiconductor device of the present invention mounted on a liquid crystal display panel. FIG. 2 is a bump of the semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a connection between a semiconductor element of the present invention and a liquid crystal display panel. FIG. 4 is a structural view of a conventional bump. FIG. 5 is a cross-sectional view of a connection between a conventional semiconductor element and a liquid crystal display panel. 6 (a) is a structural diagram showing another example of the bump of the present invention, (b) is a structural diagram showing still another example of the bump of the present invention, and (c) is a structural diagram showing another example of the bump of the present invention. Structure diagram showing another example [Explanation of reference numerals]
REFERENCE SIGNS LIST 1 electrode pad 2 passivation layer 2 a opening 3 bump layer 3 a side surface of bump 3 b upper surface of bump (contact surface at the tip)
4 Electrode terminal 5 Anisotropic conductive film 6 Conductive particle 9 Wiring pattern 10 Bump 10a Depression 11 Wafer 12 Polyimide film 13 Insulating film 14 Bubbles 20 Semiconductor element 20b Semiconductor element mounting surface (surface having bumps)
21 One board (Mounting board)
22 The other substrate

Claims (3)

凸状の電極であるバンプを有し、この凸状のバンプを有する実装面を電極端子が形成された実装用基板に向けて異方性導電膜を使用して実装し、異方性導電膜の導電粒子を介して上記凸状のバンプの先端接触面と上記電極端子とを導通させる半導体素子において、上記凸状のバンプの側面に絶縁膜が形成されていることを特徴とする半導体素子。A mounting surface having bumps that are convex electrodes is mounted using an anisotropic conductive film with the mounting surface having the bumps facing the mounting substrate on which the electrode terminals are formed. A semiconductor element for electrically connecting a tip end contact surface of said convex bump to said electrode terminal via said conductive particles, wherein an insulating film is formed on a side surface of said convex bump. 前記絶縁膜は、前記凸状のバンプの先端接触面を除き、半導体素子のバンプを有する面の全体に形成されていることを特徴とする請求項１記載の半導体素子。2. The semiconductor device according to claim 1, wherein the insulating film is formed on the entire surface of the semiconductor device having the bumps, except for a contact surface at the tip of the convex bump. 3. 液晶を挟持する一対の基板の一方の基板を実装用基板として、この実装用基板の電極端子に請求項１又は請求項２のいずれかに記載の半導体素子を導電粒子を有する異方性導電膜を介して加熱圧着より実装させていることを特徴とする液晶表示パネル。3. An anisotropic conductive film having one of a pair of substrates sandwiching a liquid crystal as a mounting substrate, wherein the semiconductor element according to claim 1 or 2 has conductive particles at an electrode terminal of the mounting substrate. A liquid crystal display panel characterized in that the liquid crystal display panel is mounted by thermocompression bonding via a substrate.
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