JP2004207613A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method thereof wherein its operational delay is suppressed and the deterioration of its characteristic caused by hot carriers is suppressed. <P>SOLUTION: The semiconductor device has a gate insulation film 6a provided on a semiconductor substrate 1, a gate electrode 5a provided on the gate insulation film 6a, offset side walls 9a comprising silicon oxide films containing nitrogen and provided on the side surfaces of the gate electrode 5a and the gate insulation film 6a, and side walls 8 comprising silicon nitride films and provided on the side surfaces of the offset side walls 9a. Since nitrogen is introduced into the offset side walls 9a, the deterioration of the electric characteristic of the semiconductor device which is caused by hot carriers is suppressed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS transistor having a double sidewall structure and a method of manufacturing the same.
[0002]
[Prior art]
One of the factors that lower the reliability of MOS transistors due to miniaturization is injection of hot carriers into the gate insulating film. As the size of the semiconductor device decreases, the electric field in the direction along the channel region between the source and the drain increases, and carriers existing in the channel region are accelerated by the electric field to have high energy. Such a carrier is called a hot carrier. Since the hot carriers have high energy, they are easily injected into the gate insulating film of the MOS transistor over the energy barrier at the interface between the semiconductor substrate and the gate insulating film. The carriers injected into the gate insulating film are trapped in the gate insulating film or generate an interface state to change the threshold voltage of the semiconductor, thereby lowering the current driving capability of the MOS transistor.
[0003]
Hereinafter, a semiconductor device in which reliability is improved by such hot carriers will be described (for example, see Patent Document 1).
[0004]
FIG. 9 is a sectional view showing the structure of a MOS transistor according to a first conventional example.
[0005]
As shown in FIG. 1, a conventional MOS transistor includes a semiconductor substrate 101 made of P-type silicon, a gate insulating film 106a made of silicon oxide provided on the semiconductor substrate 101, and a gate insulating film 106a made of polysilicon. A gate electrode 105a provided thereon, a sidewall 108 formed of an insulating film provided on a side surface of the gate electrode 105a, and an n-type provided in a region of the semiconductor substrate 101 located on both sides of the gate electrode 105a. A high-concentration impurity diffusion region 103 containing impurities and an n-type semiconductor layer provided in a region of the semiconductor substrate 101 in contact with the high-concentration impurity diffusion region 103 and the end of the gate insulating film 106a and having a lower concentration than the high-concentration impurity diffusion region 103. Low-concentration impurity diffusion region 102 containing a p-type impurity, and gate electrode 105 And a nitrogen-containing region 106b provided in a region located under both the lower end of the. The active region of the semiconductor substrate 101 is surrounded by the isolation insulating film 104.
[0006]
A feature of the MOS transistor according to the first conventional example is that a nitrogen-containing region 106b is provided in the gate insulating film 106a. During the operation of the MOS transistor, an electric field is concentrated in a region of the gate insulating film located below the lower end of the gate electrode, so that hot carriers are easily generated. Therefore, by introducing nitrogen into a region where an electric field is likely to be concentrated, hot carriers can be prevented from being trapped in the gate insulating film 106a. As described above, in the MOS transistor according to the first conventional example, the hot carrier resistance is improved.
[0007]
Next, a method of manufacturing the MOS transistor according to the first conventional example will be briefly described.
[0008]
FIGS. 10A to 10C and FIGS. 11A and 11B are cross-sectional views showing a process for manufacturing a MOS transistor according to a first conventional example.
[0009]
First, as shown in FIG. 10A, an isolation insulating film 104 is formed on a P-type semiconductor substrate 101 by a normal trench isolation method, and then an oxide film 106 is formed on the semiconductor substrate 101 by a thermal oxidation method. To form After that, a polysilicon film 105 is formed on the substrate.
[0010]
Subsequently, as shown in FIG. 10B, a resist film is applied on the entire surface of the polysilicon film 105, and is patterned into a predetermined shape using a lithography technique. Next, after the polysilicon film 105 and the oxide film 106 are etched using this resist film as a mask, the resist film is removed, and a gate insulating film 106a and a gate electrode 105a are formed.
[0011]
Next, as shown in FIG. 10C, the substrate is heat-treated in an atmosphere containing ammonia, and a region of the gate insulating film 106a located under the lower end portion of the gate electrode 105a is nitrided to contain nitrogen. The region 106a is formed. At this time, the exposed portions of the gate electrode 105a and the semiconductor substrate 101 are also nitrided (not shown).
[0012]
Then, as shown in FIG. 11A, arsenic ions are implanted into the semiconductor substrate 101 using the gate electrode 105a as a mask, and an n-type low-concentration An impurity diffusion region 102 is formed.
[0013]
Next, as shown in FIG. 11B, a sidewall 108 is formed on a side surface of the gate electrode 105a. Although not shown, after that, arsenic ions are implanted into the semiconductor substrate 101 using the gate electrode 105a and the sidewalls 108 as a mask to form an n-type high-concentration impurity diffusion region 103. Then, by applying heat treatment to the substrate, the conventional MOS transistor shown in FIG. 9 can be manufactured.
[0014]
On the other hand, in recent years, as elements have been miniaturized, MOS transistors having a so-called double sidewall structure as shown in FIG. 12 have been widely used.
[0015]
FIG. 12 is a sectional view showing a structure of a MOS transistor according to a second conventional example. In the figure, the same reference numerals are used for members or regions similar to those of the MOS transistor according to the first conventional example.
[0016]
As shown in FIG. 12, a MOS transistor according to a second conventional example includes a semiconductor substrate 101 made of P-type silicon, a gate insulating film 106a provided on the semiconductor substrate 101, and a gate insulating film 106a provided on the gate insulating film 106a. A high concentration impurity diffusion region 103 provided in a region of the semiconductor substrate 101 which is located below both sides of the gate electrode 105a and contains a high concentration impurity diffusion region 103. A low-concentration impurity diffusion region 102 provided in a region of the semiconductor substrate 101 which is lower than both sides of the gate electrode 105a and contains an n-type impurity at a lower concentration, and an offset side provided on a side surface of the gate electrode 105a. The wall 119 and the side wall 118 provided on the side surface of the offset side wall 119 Eteiru. The offset sidewall 119 is made of, for example, silicon oxide, and the sidewall 118 is made of silicon nitride.
[0017]
In the MOS transistor according to the second conventional example, the side wall 118 and the offset side wall 119 are formed to reduce the overlap region between the gate electrode 105a and the low concentration impurity diffusion region 102 as compared with the first conventional example. Is provided. When the overlap region increases, the parasitic capacitance between the gate electrode 105a and the semiconductor substrate 101 increases, causing a circuit delay. For this reason, the parasitic capacitance is reduced in the MOS transistor according to the second conventional example.
[0018]
Next, a method of manufacturing the MOS transistor according to the second conventional example will be briefly described.
[0019]
FIGS. 13A to 13C and FIGS. 14A and 14B are cross-sectional views showing a process for manufacturing a MOS transistor according to a second conventional example.
[0020]
First, as shown in FIG. 13A, an insulating film 104 for element isolation is formed on a P-type semiconductor substrate 101 by a known trench isolation method, and then an oxide film 106 is formed by thermal oxidation of the substrate. Next, a polysilicon film 105 is formed on the oxide film 106.
[0021]
Next, as shown in FIG. 13B, a resist is applied to the entire upper surface of the substrate, and is patterned into a predetermined shape using lithography. Next, the polysilicon film 105 and the oxide film 106 are etched using the resist film as a mask, and the unnecessary resist is removed, thereby forming the gate electrode 105a and the gate insulating film 106a, respectively.
[0022]
Next, as shown in FIG. 13C, an offset sidewall 119 made of silicon oxide is formed on the side surface of the gate electrode 105a.
[0023]
Thereafter, as shown in FIG. 14A, arsenic ions are implanted into the semiconductor substrate 101 using the gate electrode 105a and the offset side walls 119 as a mask, thereby forming a low-concentration impurity diffusion region 102 containing an n-type impurity.
[0024]
Next, as shown in FIG. 14B, a side wall 118 made of a silicon nitride film or the like is formed on the side surface of the offset side wall 119. Subsequently, arsenic ions are implanted using the gate electrode 105a, the offset sidewalls 119, and the sidewalls 118 as masks to form n-type high-concentration impurity diffusion regions 103 (not shown). Next, by subjecting the substrate to heat treatment, a MOS transistor according to the second conventional example can be manufactured.
[0025]
[Patent Document 1]
JP-A-9-313393 (FIG. 1, FIG. 3 to FIG. 8)
[0026]
[Problems to be solved by the invention]
As described above, in the MOS transistor according to the second conventional example, the capacitance between the gate electrode 105a and the low-concentration impurity diffusion region 102 can be reduced, so that the operation delay is suppressed as compared with the first conventional example. I have.
[0027]
However, in the MOS transistor according to the second conventional example, since the gate insulating film is formed of the silicon oxide film, the problem caused by hot carriers is not improved. Therefore, the inventors of the present application tried to introduce nitrogen into a region located under both lower ends of the gate electrode 105a in the gate insulating film 106a as in the first conventional example. The performance degradation of the transistor could not be sufficiently suppressed.
[0028]
The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a highly reliable semiconductor device in which operation delay is suppressed and characteristic deterioration due to hot carriers is suppressed, and a method for manufacturing the same. And
[0029]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film provided on the semiconductor substrate and made of an insulator, a gate electrode made of a conductor provided on the gate insulating film, and the gate electrode and the gate electrode. A first sidewall provided on a side surface of the gate insulating film and made of an insulator into which nitrogen is introduced; a second sidewall provided on a side surface of the first sidewall and made of an insulator; The semiconductor substrate includes a first impurity diffusion region provided in a region located below both sides of the gate electrode and containing a first conductivity type impurity.
[0030]
Thus, since nitrogen is introduced into the first sidewall, hot carriers generated during operation are trapped in the first sidewall, for example, as compared with the case where the first sidewall is formed of a silicon oxide film. It is hard to be done. Therefore, in the semiconductor device of the present invention, a change in threshold value and a deterioration in operation performance due to hot carriers are suppressed, and the reliability is improved. Further, since the semiconductor device of the present invention has a double sidewall structure, parasitic capacitance generated between the gate electrode and the first impurity diffusion region is reduced, so that circuit delay is suppressed.
[0031]
Since the first sidewall is made of the silicon oxynitride film, even when a double sidewall structure is adopted, deterioration of electrical characteristics due to hot carriers can be reduced.
[0032]
Since the nitrogen-containing region made of silicon oxynitride is provided in at least a part of the gate insulating film, not only the hot carriers trapped in the first sidewall but also the hot carriers trapped in the gate insulating film are formed. Since carriers can also be reduced, the generation of interface states generated between the semiconductor substrate and the gate insulating film can be suppressed. Therefore, according to this configuration, when hot carriers are generated during operation, it is possible to make the electrical characteristics less susceptible to deterioration.
[0033]
The nitrogen-containing region is provided at both ends of the gate insulating film in contact with the first impurity diffusion region, and a portion of the gate insulating film other than the nitrogen-containing region is formed of a silicon oxide film. By doing so, performance degradation due to hot carriers can be reduced as compared with a configuration in which the entire region of the gate insulating film is formed of a silicon oxide film.
[0034]
The semiconductor substrate is provided at a position below both sides of the second sidewall and adjacent to the first impurity diffusion region, and is higher in concentration than the first impurity diffusion region and of the first conductivity type. By further providing the second impurity diffusion region containing impurities, a so-called lightly-doped drain (LDD) structure is provided, so that the withstand voltage can be improved.
[0035]
According to a first method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film provided on a semiconductor substrate and made of an insulator and a gate electrode provided on the gate insulating film and made of a conductor ( a), after the step (a), a step (b) of forming a silicon oxide film on the exposed surface of the gate electrode and on the semiconductor substrate over the entire surface of the substrate, and etching the silicon oxide film. (C) forming a first sidewall on the side surface of the gate electrode, (d) introducing nitrogen into the first sidewall, and forming the first sidewall on the gate electrode and the first sidewall. Forming a first impurity diffusion region by implanting impurity ions of the first conductivity type into the semiconductor substrate using the mask as a mask, and after the steps (d) and (e), the first side On the side of the wall And a step (f) forming a second side wall made of an insulating material.
[0036]
By this method, nitrogen is introduced into the first sidewall made of the silicon oxide film in the step (d), so that carrier trapping on the first sidewall is reduced, and the semiconductor device hardly affected by hot carriers can be obtained. Can be manufactured.
[0037]
In the step (d), nitrogen is introduced into the first sidewall by heating the semiconductor substrate in an ammonia atmosphere, so that nitrogen can be easily introduced into the first sidewall.
[0038]
In the step (d), when nitrogen is introduced into the first sidewall by oblique ion rotation implantation of nitrogen ions, a desired amount of nitrogen can be introduced into a desired place with good controllability.
[0039]
In the step (d), when nitrogen is introduced into the first sidewall by exposing the semiconductor substrate to a plasma containing nitrogen radicals, a process at a lower temperature can be performed as compared with a method of heating in an ammonia atmosphere. Therefore, when an impurity is implanted into the semiconductor substrate for controlling the threshold value, the diffusion of the impurity can be suppressed.
[0040]
After the step (a) and before the step (b), the method further comprises introducing nitrogen to both ends of the gate insulating film, and the gate insulating film formed in the step (a) is a silicon oxide film. With this configuration, it is possible to manufacture a semiconductor device that is less susceptible to deterioration in performance due to hot carriers as compared with a configuration in which the entire region of the gate insulating film is formed of a silicon oxide film.
[0041]
The gate insulating film formed in the step (a) is made of a silicon oxide film. In the step (d), nitrogen is introduced into the first sidewall by oblique ion rotation implantation of nitrogen ions, and simultaneously the nitrogen is introduced into the first sidewall. When nitrogen is introduced into both ends of the gate insulating film, it is possible to manufacture a semiconductor device which is less susceptible to deterioration in performance due to hot carriers in fewer steps.
[0042]
After the step (f), impurity ions of the first conductivity type are implanted into the semiconductor substrate using the gate electrode, the first sidewall, and the second sidewall as a mask, and the first impurity diffusion region is formed. By forming the second impurity diffusion region containing a higher concentration of impurity ions, a semiconductor device having an LDD structure with improved withstand voltage can be manufactured.
[0043]
According to a second method of manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film provided on a semiconductor substrate and made of an insulator, and a gate electrode provided on the gate insulating film and made of a conductor ( a), after the step (a), a step (b) of forming a silicon oxide film on the exposed surface of the gate electrode and on the semiconductor substrate over the entire surface of the substrate, and introducing nitrogen into the silicon oxide film (C) forming a nitrogen-containing oxide film; (d) etching the nitrogen-containing oxide film to form a first sidewall on a side surface of the gate electrode; A step (e) of implanting first conductivity type impurity ions into the semiconductor substrate using the first sidewall as a mask to form a first impurity diffusion region; Of the sidewall And a step (f) forming a second side wall made of an insulating material on a surface.
[0044]
According to this method, nitrogen is introduced into the silicon oxide film in the step (c), so that the constituent material of the first sidewall can be a nitrogen-containing oxide film, and a semiconductor device which is not easily affected by hot carriers is manufactured. can do.
[0045]
In the step (c), nitrogen may be introduced into the silicon oxide film by heating the semiconductor substrate in an ammonia atmosphere.
[0046]
In the step (c), nitrogen may be introduced into the silicon oxide film by oblique ion rotation implantation of nitrogen ions.
[0047]
In the step (c), nitrogen may be introduced into the silicon oxide film by exposing the semiconductor substrate to plasma containing nitrogen radicals.
[0048]
After the step (a) and before the step (b), the method further comprises introducing nitrogen to both ends of the gate insulating film, and the gate insulating film formed in the step (a) is a silicon oxide film. With this configuration, a semiconductor device that is less susceptible to deterioration in performance due to hot carriers can be manufactured.
[0049]
The gate insulating film formed in the step (a) is made of a silicon oxide film. In the step (c), nitrogen is introduced into the first sidewall by oblique ion rotation implantation of nitrogen ions, and simultaneously the nitrogen is introduced into the first sidewall. When nitrogen is introduced into both ends of the gate insulating film, it is possible to manufacture a semiconductor device which is less susceptible to deterioration in performance due to hot carriers in fewer steps.
[0050]
After the step (f), impurity ions of the first conductivity type are implanted into the semiconductor substrate using the gate electrode, the first sidewall, and the second sidewall as a mask, and the first impurity diffusion region is formed. By forming the second impurity diffusion region containing a higher concentration of impurity ions, a semiconductor device having an LDD structure with improved withstand voltage can be manufactured.
[0051]
Embodiment of the present invention
-Examination of the cause of the defect-
First, the inventors of the present application examined the cause of the tendency of characteristic deterioration due to hot carriers in the second conventional example shown in FIG. As a result, in the MOS transistor according to the second conventional example, hot carriers are trapped below the offset sidewall 119, so that an interface state is generated between the semiconductor substrate 101 and the offset sidewall 119, It was found that the electrical characteristics deteriorated. It is considered that this occurs because the offset sidewall 119 is made of silicon oxide. Therefore, the present inventors have considered means for reducing carriers trapped in the offset sidewall 119 and have arrived at the present invention.
[0052]
Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
[0053]
(1st Embodiment)
FIG. 1 is a sectional view showing the structure of the MOS transistor according to the first embodiment of the present invention. The feature of the MOS transistor of this embodiment is that it has a double sidewall structure of the offset sidewall 9a and the sidewall 8, and nitrogen is introduced into the offset sidewall 9a.
[0054]
That is, as shown in FIG. 1, the MOS transistor according to the present embodiment has an active region, a semiconductor substrate 1 made of P-type silicon, and a gate insulating film having a thickness of 3 nm provided on the active region of the semiconductor substrate 1. A film 6a, a gate electrode 5a made of polysilicon provided on the gate insulating film 6a, and an offset sidewall 9a provided on the semiconductor substrate 1 and formed on side surfaces of the gate electrode 5a and the gate insulating film 6a. And a sidewall 8 provided on the semiconductor substrate 1 and formed on a side surface of the offset sidewall 9a. In the semiconductor substrate 1, regions located on both sides of the gate electrode 5a are, for example, 5 × 10 ¹⁸ cm ^-3 A low-concentration impurity diffusion region 2 containing an N-type impurity at a low concentration; ²⁰ cm ^-3 And a high-concentration impurity diffusion region 3 containing an N-type impurity at a high concentration. The active region is surrounded by the isolation insulating film 4.
[0055]
The offset sidewall 9a has a thickness (width in the gate length direction) of about 10 nm and is made of an oxide film containing nitrogen (a nitrogen-containing oxide film). On the other hand, the sidewall 8 is made of, for example, a silicon nitride film.
[0056]
As described above, since the MOS transistor of the present embodiment has the offset sidewall 9a made of a nitrogen-containing oxide film, hot carriers are generated in the offset sidewall 9a as compared with the MOS transistor according to the second conventional example. It is hard to be trapped. Therefore, the MOS transistor of the present embodiment is less susceptible to a change in the threshold value or a change in the current driving characteristic due to the hot carriers, and the reliability is improved.
[0057]
In addition, the MOS transistor according to the present embodiment has a small overlap between the low-concentration impurity diffusion region 2 and the gate electrode 5a similarly to the MOS transistor according to the second conventional example. The operation speed is improved as compared with the above.
[0058]
Next, a method for manufacturing the MOS transistor according to the present embodiment will be described with reference to the drawings.
[0059]
2A to 2D and 3A to 3C are cross-sectional views showing the steps of manufacturing the MOS transistor according to the present embodiment.
[0060]
First, as shown in FIG. 2A, an element isolation insulating film 4 is formed on a P-type semiconductor substrate 1 by a known trench isolation method, and then an oxide film 6 is formed on the semiconductor substrate 1 by thermal oxidation. . Thereafter, a polysilicon film 5 having a thickness of about 160 nm is formed on the substrate.
[0061]
Next, as shown in FIG. 2B, a resist (not shown) is applied to the entire upper surface of the polysilicon film 5, and is patterned into a predetermined shape by using a lithography technique. Next, the polysilicon film 5 and the oxide film 6 are etched using the resist film as a mask, and the unnecessary resist is removed to form a gate electrode 5a and a gate insulating film 6a, respectively.
[0062]
Next, as shown in FIG. 2C, a silicon oxide film 9 having a thickness of about 14 nm is formed on the substrate by a CVD (Chemical Vapor Deposition) method. The silicon oxide film 9 deposited here is, for example, an HTO film (High temperature oxcide) deposited at a high temperature.
[0063]
Next, as shown in FIG. 2D, the oxide film 9 is etched back to leave an offset sidewall 9A made of an oxide film on the side surfaces of the gate electrode 5a and the gate insulating film 6a. Here, the width of the offset sidewall 9A is about 10 nm.
[0064]
Next, as shown in FIG. _Three The substrate is heat-treated at a temperature of 600 ° C. or more and 900 ° C. or less in an atmosphere including As a result, nitrogen is introduced into the offset sidewall 9A made of an oxide film, and the offset sidewall 9a made of a nitrogen-containing oxide film is formed. In this step, nitrogen is also introduced into the exposed portion of the semiconductor substrate 1 and the exposed portion of the gate electrode 5a, but this is not shown because it is not essential to the invention.
[0065]
Next, as shown in FIG. 3B, N-type impurity ions such as arsenic ions are implanted into the semiconductor substrate 1 using the gate electrode 5a and the offset sidewalls 9a as a mask to form the low concentration impurity diffusion region 2. Here, the overlap between the low-concentration impurity diffusion region 2 and the gate electrode 5a when viewed from above is reduced by the thickness of the offset sidewall 9a.
[0066]
Subsequently, as shown in FIG. 3C, a silicon nitride film having a thickness of about 60 nm is deposited on the entire substrate, and the silicon nitride film is etched back to form a sidewall 8 on the side surface of the offset sidewall 9a. To form Thereafter, arsenic ions are implanted using the gate electrode 5a, the offset sidewalls 9a, and the sidewalls 8 as masks to form the high-concentration impurity diffusion regions 3 (not shown). Subsequently, by subjecting the substrate to a heat treatment, the MOS transistor of the present embodiment shown in FIG. 1 can be manufactured.
[0067]
In the method for manufacturing a MOS transistor according to the present embodiment, after the offset sidewall 9A made of an oxide film is formed, the offset sidewall 9a made of a nitrogen-containing oxide film is introduced by introducing nitrogen in the step shown in FIG. I have to. This method is used because it is difficult to directly deposit a silicon oxynitride film by a CVD method or the like.
[0068]
Further, in the above-described method, the introduction of nitrogen into the offset sidewall 9A is performed after the oxide film 9 is etched back. However, after the oxide film 9 is formed as shown in FIG. You may go before the back. In this case, no nitride film is formed on the exposed portion of the semiconductor substrate 1 or on the upper surface of the gate electrode 5a. However, the method of introducing nitrogen after etching back the oxide film 9 is preferable because the etching of the oxide film 9 can be performed with good controllability.
[0069]
In the above description, only the case of an N-type MOS transistor has been described. However, also in the case of a P-type MOS transistor, an offset sidewall made of a nitrogen-containing oxide film can be formed by a similar process.
[0070]
In the present embodiment, the description has been made using the MOSFET. However, the same effect can be obtained in a flash EEPROM by forming a double sidewall structure in the same manner as described above.
[0071]
(Second embodiment)
A method for manufacturing a MOS transistor according to the second embodiment of the present invention will be described below.
[0072]
The method of manufacturing the MOS transistor of the present embodiment is different from the method of the first embodiment only in the step of introducing nitrogen into the offset sidewall 9A, and the other steps are the same as the method of the first embodiment.
[0073]
That is, as shown in FIG. 2A, after an insulating film 4 for element isolation is formed on a P-type semiconductor substrate 1 by a known trench isolation method, an oxide film 6 is formed on the semiconductor substrate 1 by thermal oxidation. . After that, a polysilicon film 5 is formed on the substrate.
[0074]
Next, as shown in FIG. 2B, a resist (not shown) is applied to the entire upper surface of the polysilicon film 5, and is patterned into a predetermined shape by using a lithography technique. Next, the polysilicon film 5 and the oxide film 6 are etched using the resist film as a mask, and the unnecessary resist is removed to form a gate electrode 5a and a gate insulating film 6a, respectively.
[0075]
Next, as shown in FIG. 2C, an oxide film 9 made of HTO is formed on the substrate by a CVD method.
[0076]
Then, as shown in FIG. 2D, the oxide film 9 is etched back to leave an offset sidewall 9A on the side surfaces of the gate electrode 5a and the gate insulating film 6a.
[0077]
Next, nitrogen is introduced into the offset sidewall 9A.
[0078]
FIG. 4 is a cross-sectional view showing an oblique ion implantation step in the method for manufacturing a MOS transistor according to the present embodiment.
[0079]
In the step shown in the figure, nitrogen ions are implanted while rotating the substrate from a position inclined at 3 degrees or more and 45 degrees or less with respect to the substrate. Thereby, nitrogen is introduced into the offset sidewall 9A. At this time, the injection amount of nitrogen ions is 5 × 10 ¹⁴ cm ^-2 More than 1 × 10 ¹⁶ cm ^-2 The implantation energy is preferably not more than 5 keV, and the implantation energy is preferably not less than 5 keV and not more than 20 keV. As a result, nitrogen is introduced into the oxide film forming the offset sidewall 9A, and the offset sidewall 9a is formed from a nitrogen-containing oxide film. Here, when the implantation energy is increased, nitrogen ions are implanted into both ends of the gate insulating film 6a as described later.
[0080]
After this step, as shown in FIGS. 3B and 3C, a step of forming a low-concentration impurity diffusion region 2 by implanting N-type ions, a step of forming a sidewall 8 made of a silicon nitride film, and a step shown in FIG. The MOS transistor of the present embodiment (the MOS transistor of the first embodiment) is manufactured through the step of forming the impurity diffusion region 3 and the step of activating the impurities by heat treatment in this order. Note that the heat treatment after the formation of the high-concentration impurity diffusion region 3 also serves as a heat treatment for nitrogen introduced into the offset sidewall 9a.
[0081]
Even in the case of the offset sidewall 9a made of the nitrogen-containing oxide film formed by the nitrogen implantation described above, similarly to the method of the first embodiment, the change in the electrical characteristics due to the trapping of the hot carriers into the offset sidewall 9a is suppressed. A highly reliable MOS transistor can be manufactured.
[0082]
In particular, in the method for manufacturing a MOS transistor according to the present embodiment, since nitrogen is introduced into the offset sidewall 9A by ion implantation, it is easy to control the amount of nitrogen to be introduced. Further, since the implantation energy can be adjusted according to the thickness of the offset sidewall 9A, the nitrogen profile in the offset sidewall 9a film can be arbitrarily controlled. By increasing the implantation energy of nitrogen ions, nitrogen can be simultaneously introduced into both ends of the gate insulating film 6a as well as the offset sidewalls 9a.
[0083]
In the above description, the resist mask formed in the step of implanting nitrogen ions shown in FIG. 4 can also be used in the step of forming the low-concentration impurity diffusion region 2 shown in FIG. Accordingly, the number of steps can be reduced as compared with the case where masks are separately formed. Further, only by adding a step of patterning a resist in a predetermined region before ion implantation, nitrogen can be contained in an offset sidewall only in, for example, only an NMOS region, for example, only an I / O region (input / output circuit region). it can.
[0084]
In the method of the present embodiment, the nitrogen ion implantation step may be performed after the oxide film 9 is formed and before the oxide film 9 is etched back. However, the method of introducing nitrogen after the etch back of the oxide film 9 is more preferable because the etching of the oxide film 9 can be performed with good controllability.
[0085]
(Third embodiment)
As a third embodiment of the present invention, another method of manufacturing the MOS transistor according to the first embodiment will be described.
[0086]
In the method for manufacturing a MOS transistor according to the present embodiment, nitrogen is introduced into the offset sidewalls 9a by plasma nitridation, and the other steps are the same as those in the first and second embodiments.
[0087]
That is, as shown in FIG. 2A, after an insulating film 4 for element isolation is formed on a P-type semiconductor substrate 1 by a known trench isolation method, an oxide film 6 is formed on the semiconductor substrate 1 by thermal oxidation. . After that, a polysilicon film 5 is formed on the substrate.
[0088]
Next, as shown in FIG. 2B, a resist (not shown) is applied to the entire upper surface of the polysilicon film 5, and is patterned into a predetermined shape by using a lithography technique. Next, the polysilicon film 5 and the oxide film 6 are etched using the resist film as a mask, and the unnecessary resist is removed to form a gate electrode 5a and a gate insulating film 6a, respectively.
[0089]
Next, as shown in FIG. 2C, an oxide film 9 made of HTO is formed on the substrate by a CVD method.
[0090]
Then, as shown in FIG. 2D, the oxide film 9 is etched back to leave an offset sidewall 9A on the side surfaces of the gate electrode 5a and the gate insulating film 6a.
[0091]
Next, nitrogen is introduced into the offset sidewall 9A.
[0092]
FIG. 5 is a cross-sectional view showing a plasma nitriding step in the method for manufacturing a MOS transistor according to the present embodiment.
[0093]
In this step, as shown in FIG. 5, the offset sidewall 9A is nitrided by exposing the substrate to a plasma containing nitrogen radicals. In this case, for example, it is preferable that the pressure is about 1.27 Pa (950 mTorr), the temperature is 200 ° C. or more and 400 ° C. or less, and the processing time is 20 seconds. In addition, argon (Ar) gas and nitrogen (N _Two ) The gas flow rate was 2.0 × 10 ^Three ml / min and 1.5 × 10 ^Two ml / min and the power is preferably 1.5 kW. In this step, nitridation proceeds rapidly from the surface of the substrate including the side surface of the offset sidewall 9A by the highly reactive nitrogen plasma.
[0094]
After this step, as shown in FIGS. 3B and 3C, a step of forming a low-concentration impurity diffusion region 2 by implanting N-type ions, a step of forming a sidewall 8 made of a silicon nitride film, and a step shown in FIG. The MOS transistor of the present embodiment (the MOS transistor of the first embodiment) is manufactured through the step of forming the impurity diffusion region 3 and the step of activating the impurities by heat treatment in this order.
[0095]
Even in the case of the offset sidewall 9a made of a nitrogen-containing oxide film formed by the above-described plasma nitriding, a highly reliable MOS transistor in which a change in electrical characteristics due to trapping of hot carriers to the offset sidewall 9a is manufactured. be able to.
[0096]
In addition, according to the method of the present embodiment, by performing plasma nitridation, nitrogen can be introduced into the offset sidewall 9a at a lower temperature than in the method of the first embodiment. Diffusion of threshold control impurities and the like implanted in the semiconductor device can be prevented.
[0097]
(Fourth embodiment)
As a fourth embodiment of the present invention, a description will be given of a MOS transistor in which nitrogen is introduced into both ends of a gate insulating film as well as an offset sidewall and a method of manufacturing the same.
[0098]
FIG. 6 is a sectional view showing the structure of the MOS transistor according to the fourth embodiment of the present invention.
[0099]
As shown in the figure, the MOS transistor of this embodiment has an active region, a semiconductor substrate 1 made of P-type silicon, and a gate insulating film 6a having a thickness of 3 nm provided on the active region of the semiconductor substrate 1. A gate electrode 5a made of polysilicon provided on the gate insulating film 6a, and an offset sidewall 9a provided on the semiconductor substrate 1 and formed on the side surface of the gate electrode 5a and the gate insulating film 6a. A side wall provided on the semiconductor substrate and formed on a side surface of the offset side wall. In the semiconductor substrate 1, regions located on both sides of the gate electrode 5a are, for example, 5 × 10 ¹⁸ cm ^-3 A low-concentration impurity diffusion region 2 containing an N-type impurity at a low concentration; ²⁰ cm ^-3 And a high-concentration impurity diffusion region 3 containing an N-type impurity at a high concentration. The active region is surrounded by the isolation insulating film 4. The offset sidewall 9a has a thickness of about 10 nm and is made of a nitrogen-containing oxide film.
[0100]
In the MOS transistor of the present embodiment, a nitrogen-containing region 6b is provided at both ends of the gate insulating film 6a, that is, at a portion in contact with the low-concentration impurity diffusion region 2, and other portions of the gate insulating film 6a are formed of silicon. It is made of an oxide film.
[0101]
For this reason, in the MOS transistor of the present embodiment, it is difficult for hot carriers to be trapped not only at the offset sidewalls 9a but also at both ends of the gate insulating film 6a. Therefore, in the MOS transistor of the present embodiment, the deterioration of the electrical characteristics when hot carriers are generated is more effectively reduced than in the MOS transistor of the first embodiment.
[0102]
Next, a method for manufacturing the MOS transistor of the present embodiment will be described.
[0103]
7A to 7D and 8A to 8D are cross-sectional views showing the steps of manufacturing the MOS transistor according to the present embodiment.
[0104]
First, as shown in FIG. 7A, after an insulating film 4 for element isolation is formed on a P-type semiconductor substrate 1 by a known trench isolation method, an oxide film 6 is formed on the semiconductor substrate 1 by thermal oxidation. . Thereafter, a polysilicon film 5 having a thickness of about 160 nm is formed on the substrate.
[0105]
Next, as shown in FIG. 7B, a resist (not shown) is applied to the entire upper surface of the polysilicon film 5, and is patterned into a predetermined shape by using a lithography technique. Next, the polysilicon film 5 and the oxide film 6 are etched using the resist film as a mask, and the unnecessary resist is removed to form a gate electrode 5a and a gate insulating film 6a, respectively. The steps so far are the same as in the first embodiment.
[0106]
Next, as shown in FIG. 7C, the substrate is heat-treated in an ammonia atmosphere, and nitrogen is introduced into both ends of the gate insulating film 6a to form a nitrogen-containing region 6b. However, instead of this method, a nitrogen introduction method such as plasma nitridation or nitrogen ion implantation may be used.
[0107]
Subsequently, as shown in FIG. 7D, an oxide film 9 having a thickness of about 14 nm is formed on the substrate by the CVD method.
[0108]
Next, as shown in FIG. 8A, the oxide film 9 is etched back to leave an offset sidewall 9A on the side surfaces of the gate electrode 5a and the gate insulating film 6a.
[0109]
Next, as shown in FIG. 8B, nitrogen is introduced into the offset sidewall 9A. Here, as a method for introducing nitrogen, any of the methods described in the first to third embodiments may be used. That is, any of heat treatment in an ammonia atmosphere, oblique ion implantation of nitrogen ions, and nitrogen plasma treatment may be used. As a result, nitrogen is introduced into the offset sidewall 9A, and the offset sidewall 9a made of a nitrogen-containing oxide film is obtained.
[0110]
Next, as shown in FIG. 8C, N-type impurity ions such as arsenic ions are implanted into the semiconductor substrate 1 using the gate electrode 5a and the offset sidewalls 9a as a mask to form the low concentration impurity diffusion region 2.
[0111]
Next, as shown in FIG. 8D, a silicon nitride film having a thickness of about 60 nm is deposited on the entire substrate, and the silicon nitride film is etched back to form a sidewall 8 on the side surface of the offset sidewall 9a. To form Thereafter, arsenic ions are implanted using the gate electrode 5a, the offset sidewalls 9a, and the sidewalls 8 as masks to form the high-concentration impurity diffusion regions 3 (not shown). Subsequently, by subjecting the substrate to a heat treatment, the MOS transistor of the present embodiment shown in FIG. 6 can be manufactured.
[0112]
In the above description, an example in which the step of introducing nitrogen into both ends of the gate insulating film 6a and the step of introducing nitrogen into the offset sidewall 9a are performed separately is described. , Both steps can be performed simultaneously. In this case, the step shown in FIG. 7C is not performed, and nitrogen ions may be implanted with an energy that can reach the end of the gate insulating film 9a in the step shown in FIG. 8B. At this time, the implantation energy is set to about 20 keV, and the implantation is performed at a position inclined from 3 degrees to 45 degrees with respect to the substrate.
According to this method, the MOS transistor of the present embodiment can be manufactured with fewer steps.
[0113]
In the MOS transistor of the present embodiment, the nitrogen-containing region 6b is provided at the end of the gate insulating film 6a. There may be. In such a MOS (MIS) transistor, a decrease in performance due to hot carriers is further reduced. Note that instead of performing the step shown in FIG. 7C, in the step shown in FIG. 7A, a step of introducing nitrogen after forming the oxide film 6 and before forming the polysilicon film 5 is performed. This MIS transistor can be manufactured.
[0114]
【The invention's effect】
A first semiconductor device according to the present invention is a MOS transistor including an offset sidewall covering a side surface of a gate electrode and a sidewall provided on a side surface of the offset sidewall, wherein nitrogen is introduced into the offset sidewall. Have been. Therefore, carriers are less likely to be trapped in the offset sidewalls, so that deterioration of electrical characteristics due to hot carrier injection can be reduced.
[0115]
A second semiconductor device according to the present invention is a MOS transistor including an offset sidewall covering a side surface of a gate electrode, and a sidewall provided on a side surface of the offset sidewall, the MOS transistor including an offset sidewall and a gate insulating film. Are introduced at both ends. This makes it difficult for carriers to be trapped not only at the offset sidewalls but also at both ends of the gate insulating film, so that deterioration of electrical characteristics due to hot carrier injection can be reduced more effectively.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a structure of a MOS transistor according to a first embodiment of the present invention.
FIGS. 2A to 2D are cross-sectional views illustrating a process up to forming an offset sidewall in a process of manufacturing the MOS transistor according to the first embodiment of the present invention.
FIGS. 3A to 3C are cross-sectional views illustrating a process up to formation of a sidewall in a manufacturing process of the MOS transistor according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an oblique ion implantation step in a method for manufacturing a MOS transistor according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a plasma nitriding step in a method for manufacturing a MOS transistor according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view illustrating a structure of a MOS transistor according to a fourth embodiment of the present invention.
FIGS. 7A to 7D are cross-sectional views showing up to a step of forming an oxide film in a manufacturing process of a MOS transistor according to a fourth embodiment.
FIGS. 8A to 8D are cross-sectional views illustrating a process up to formation of a sidewall in a process of manufacturing a MOS transistor according to a fourth embodiment.
FIG. 9 is a sectional view showing a structure of a MOS transistor according to a first conventional example.
FIGS. 10A to 10C are cross-sectional views illustrating a process of manufacturing a MOS transistor according to a first conventional example until nitrogen is introduced into a gate insulating film.
FIGS. 11A and 11B are cross-sectional views showing a process of manufacturing a MOS transistor according to a first conventional example until a sidewall is formed.
FIG. 12 is a sectional view showing a structure of a MOS transistor according to a second conventional example.
FIGS. 13A to 13C are cross-sectional views showing a process of manufacturing a MOS transistor according to a second conventional example until an offset sidewall is formed.
FIGS. 14A and 14B are cross-sectional views illustrating a process of manufacturing a MOS transistor according to a second conventional example until a sidewall is formed.
[Explanation of symbols]
1 semiconductor substrate
2 Low concentration impurity diffusion region
3 High concentration impurity diffusion region
4 Insulating film for element isolation
5 Polysilicon film
5a Gate electrode
6 oxide film
6a Gate insulating film
6b Nitrogen introduction area
8 Side wall
9 oxide film
9A offset sidewall (oxide film)
9a Offset sidewall (nitrogen-containing oxide film)

Claims (19)

A semiconductor substrate;
A gate insulating film provided on the semiconductor substrate and made of an insulator,
A gate electrode provided on the gate insulating film and made of a conductor,
A first sidewall provided on a side surface of the gate electrode and the gate insulating film and made of an insulator into which nitrogen is introduced;
A second sidewall provided on a side surface of the first sidewall and made of an insulator;
A semiconductor device, comprising: a first impurity diffusion region including an impurity of a first conductivity type, provided in a region of the semiconductor substrate located below both sides of the gate electrode. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first sidewall is made of a silicon oxynitride film. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein a nitrogen-containing region is provided in at least a part of the gate insulating film. The semiconductor device according to claim 3,
The nitrogen-containing region is provided at both ends of the gate insulating film in contact with the first impurity diffusion region,
A semiconductor device, wherein a portion of the gate insulating film other than the nitrogen-containing region is made of a silicon oxide film. The semiconductor device according to any one of claims 1 to 4,
The semiconductor substrate is provided at a position below both sides of the second sidewall and adjacent to the first impurity diffusion region, and is higher in concentration than the first impurity diffusion region and of the first conductivity type. A semiconductor device further comprising a second impurity diffusion region containing an impurity. (A) forming a gate insulating film provided on a semiconductor substrate and made of an insulator, and a gate electrode made of an electric conductor provided on the gate insulating film;
A step (b) of forming a silicon oxide film on the entire surface of the substrate after the step (a);
(C) forming a first sidewall on the side surface of the gate electrode by etching the silicon oxide film;
A step (d) of introducing nitrogen into the first sidewall;
(E) implanting a first conductivity type impurity ion into the semiconductor substrate using the gate electrode and the first sidewall as a mask to form a first impurity diffusion region;
Forming a second sidewall made of an insulator on the side surface of the first sidewall after the steps (d) and (e), a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 6,
In the step (d), a method of manufacturing a semiconductor device, characterized in that nitrogen is introduced into the first sidewall by heating the semiconductor substrate in an ammonia atmosphere. The method for manufacturing a semiconductor device according to claim 6,
In the step (d), nitrogen is introduced into the first side wall by oblique ion rotation implantation of nitrogen ions. The method for manufacturing a semiconductor device according to claim 6,
In the above step (d), a method for manufacturing a semiconductor device, characterized in that nitrogen is introduced into the first sidewall by exposing the semiconductor substrate to plasma containing nitrogen radicals. The method for manufacturing a semiconductor device according to any one of claims 6 to 9,
After the step (a) and before the step (b), the method further includes a step of introducing nitrogen to both ends of the gate insulating film,
A method of manufacturing a semiconductor device, wherein the gate insulating film formed in the step (a) is made of a silicon oxide film. The method for manufacturing a semiconductor device according to claim 8,
The gate insulating film formed in the step (a) is made of a silicon oxide film,
In the step (d), a method of manufacturing a semiconductor device is characterized in that nitrogen is introduced into the first sidewall and simultaneously nitrogen is introduced into both ends of the gate insulating film by oblique ion rotation implantation of nitrogen ions. . The method of manufacturing a semiconductor device according to claim 6,
After the step (f), impurity ions of the first conductivity type are implanted into the semiconductor substrate using the gate electrode, the first sidewall, and the second sidewall as a mask, and the first impurity diffusion region is formed. A method for manufacturing a semiconductor device, comprising: forming a second impurity diffusion region containing a higher concentration of impurity ions. (A) forming a gate insulating film provided on a semiconductor substrate and made of an insulator, and a gate electrode made of an electric conductor provided on the gate insulating film;
A step (b) of forming a silicon oxide film on the entire surface of the substrate after the step (a);
(C) introducing nitrogen into the silicon oxide film to form a nitrogen-containing oxide film;
(D) forming a first sidewall on the side surface of the gate electrode by etching the nitrogen-containing oxide film;
(E) implanting a first conductivity type impurity ion into the semiconductor substrate using the gate electrode and the first sidewall as a mask to form a first impurity diffusion region;
Forming a second sidewall made of an insulator on the side surface of the first sidewall after the step (e). The method for manufacturing a semiconductor device according to claim 13,
In the step (c), a method of manufacturing a semiconductor device, characterized in that nitrogen is introduced into the silicon oxide film by heating the semiconductor substrate in an ammonia atmosphere. The method for manufacturing a semiconductor device according to claim 13,
In the step (c), a method of manufacturing a semiconductor device, characterized in that nitrogen is introduced into the silicon oxide film by oblique ion rotation implantation of nitrogen ions. The method for manufacturing a semiconductor device according to claim 13,
In the step (c), a method of manufacturing a semiconductor device, characterized in that nitrogen is introduced into the silicon oxide film by exposing the semiconductor substrate to a plasma containing nitrogen radicals. The method of manufacturing a semiconductor device according to claim 13,
After the step (a) and before the step (b), the method further includes a step of introducing nitrogen to both ends of the gate insulating film,
A method of manufacturing a semiconductor device, wherein the gate insulating film formed in the step (a) is made of a silicon oxide film. The method for manufacturing a semiconductor device according to claim 15,
The gate insulating film formed in the step (a) is made of a silicon oxide film,
In the step (c), a method of manufacturing a semiconductor device is characterized in that nitrogen is introduced into the first sidewall and simultaneously nitrogen is introduced into both ends of the gate insulating film by oblique ion rotation implantation of nitrogen ions. . The method of manufacturing a semiconductor device according to claim 13,
After the step (f), impurity ions of the first conductivity type are implanted into the semiconductor substrate using the gate electrode, the first sidewall, and the second sidewall as a mask, and the first impurity diffusion region is formed. A method for manufacturing a semiconductor device, comprising: forming a second impurity diffusion region containing a higher concentration of impurity ions.

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