JP2004207518A - Multilayer printed circuit board, method for manufacturing the same passive element array, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To try to save labor in designing in a multilayer printed circuit board, while making it easy to cope with multiple models. <P>SOLUTION: A multilayer printed circuit board 1 has a wiring layer 2 formed with a wiring and an array layer 3 connected electrically with the wiring layer 2. The array layer 3 contains a general-purpose passive element array in which a plurality of passive elements are arrayed regularly. In order to constitute a desired circuit, an electric connection regarding the passive element selected from among passive element arrays is carried out. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer printed circuit board, a passive element array, a method for manufacturing a multilayer printed circuit board, and a method for manufacturing a passive element array.
[0002]
[Prior art]
Conventionally, a multilayer printed circuit board (PCB) incorporating electronic components has been proposed. For example, Non-Patent Document 1 discloses a multilayer sheet device structure in which a circuit is formed three-dimensionally by forming various types of passive elements in a thin film on a flexible wiring board and laminating them. In a printed circuit board with a built-in component, the number of individual components mounted on the surface of the substrate can be reduced, so that the space on the substrate surface can be reduced and the size of the substrate itself can be reduced accordingly.
[0003]
[Non-patent document 1]
Takaaki Higashida, 5 others, "Multilayer sheet device formation technology to realize component built-in wiring board", "Journal of Japan Institute of Electronics Packaging" Vol.5 No.7 (2002), P630-P635
[0004]
[Problems to be solved by the invention]
In general, the design of a multilayer printed circuit board is often performed separately and independently for each product type because the functions and specifications differ depending on the product type. Due to such full customizability, not only does a considerable amount of labor and time be spent on circuit design and the like of each type, but also there is little commonality and commonality between types.
[0005]
SUMMARY OF THE INVENTION It is an object of the present invention to facilitate the use of a variety of products while saving labor in designing a multilayer printed circuit board.
[0006]
[Means for Solving the Problems]
In order to solve such a problem, a first invention provides a multilayer printed circuit board configured by stacking a plurality of layers. The printed circuit board has a wiring layer on which wiring is formed, and an array layer including a general-purpose passive element array in which a plurality of passive elements are regularly arranged and electrically connected to the wiring layer. Then, in order to configure a desired circuit, an electrical connection is made to a passive element selected from the passive element array.
[0007]
Here, in the first invention, it is preferable that the passive element array includes a first passive element group of the same type. In this case, the first passive element group includes a first passive element having a predetermined electric characteristic value and a second passive element having an electric characteristic value different from the first passive element. Is also good. Further, the passive element array may include a second passive element group of a type different from the first passive element group.
[0008]
Further, in the first invention, the array layer has a substrate thin film and a passive element layer formed on the substrate thin film and each of the passive elements constituting the passive element array being electrically separated from each other. Is preferred.
[0009]
Further, in the first invention, the passive element may be a capacitor. In this case, the passive element layer is formed on the substrate thin film, a first conductive thin film serving as a lower electrode of the capacitor, a dielectric thin film formed on the first conductive thin film, and formed on the dielectric thin film. And a second conductive thin film serving as an upper electrode of the second conductive thin film.
[0010]
Further, as a configuration example of the capacitor in the first invention, the lower electrode may be a common electrode common to a plurality of capacitors, and the upper electrode may be an individual electrode formed for each capacitor. In this case, with respect to the capacitor selected to form a desired circuit, a wiring located above the passive element layer is electrically connected to the upper electrode. Further, as another configuration example, the lower electrode may be an individual electrode formed for each capacitor, and the upper electrode may be an individual electrode formed for each capacitor. In this case, with respect to the capacitor selected to form the desired circuit, the first wiring located above the passive element layer is electrically connected to the upper electrode and is located below the passive element layer. The second wiring located on the side is electrically connected to the lower electrode through a via hole penetrating the substrate thin film. Further, as another configuration example, the capacitor may correspond to a portion where a lower electrode extending in a predetermined direction intersects with an upper electrode extending in a predetermined direction. In this case, with respect to the capacitor selected to form a desired circuit, the first wiring located above the passive element layer is electrically connected to the upper electrode and is located above the passive element layer. Is electrically connected to the lower electrode through a via hole penetrating the dielectric film.
[0011]
Further, in the first invention, a via hole extending from the upper electrode to the lower surface of the substrate thin film via the lower electrode is formed with respect to the capacitor selected for forming a desired circuit, and the via hole is formed above the passive element layer. The located first wiring and the second wiring located below the passive element layer may be electrically connected to each other via a via hole. It is preferable that an insulating film for electrically separating the first wiring and the second wiring from the upper electrode and the lower electrode be formed on the inner wall of the via hole.
[0012]
A second invention provides a passive element array used as one layer of a multilayer printed circuit board formed by laminating a plurality of layers. This passive element array is a general-purpose array in which a plurality of passive elements are regularly arranged, each of the passive elements is electrically separated from each other, and the passive elements are arranged in accordance with a desired circuit configuration. The passive elements to be used can be arbitrarily selected from the array.
[0013]
A third invention provides a passive element array used as one layer of a multilayer printed circuit board constituted by laminating a plurality of layers. This passive element array has a substrate thin film and a general-purpose passive element array formed on the substrate thin film, in which a plurality of passive elements are regularly arranged, and each of the passive elements is electrically separated from each other. And a passive element layer. Then, a passive element to be used can be arbitrarily selected from the passive element array according to a desired circuit configuration.
[0014]
Here, in the second or third aspect, the passive element array preferably includes a first passive element group of the same type. In this case, the first passive element group includes a first passive element having a predetermined electric characteristic value and a second passive element having an electric characteristic value different from the first passive element. May be. Further, the passive element array may include a second passive element group of a type different from the first passive element group.
[0015]
In the third aspect, the passive element may be a capacitor. In this case, the passive element layer is formed on the substrate thin film, a first conductive thin film serving as a lower electrode of the capacitor, a dielectric thin film formed on the first conductive thin film, and formed on the dielectric thin film. And a second conductive thin film serving as an upper electrode of the second conductive thin film.
[0016]
A fourth invention provides a method for manufacturing a multilayer printed circuit board constituted by laminating a plurality of layers. According to this manufacturing method, in a first step of forming a plurality of wiring layers having wirings, and in an array layer having a general-purpose passive element array in which a plurality of passive elements are regularly arranged, according to a desired circuit configuration, Stacking in order of forming a multilayer printed circuit board by inserting an array layer between a plurality of wiring layers, and a second step of electrically connecting a passive element selected from the passive element array. A third step of forming the stacked body, and a fourth step of integrating the stacked body.
[0017]
A fifth invention provides a method for manufacturing a passive element array used as one layer of a multilayer printed circuit board constituted by laminating a plurality of layers. This manufacturing method includes a first step of preparing a substrate thin film, and a second step of forming a passive element layer on the substrate thin film to be a general-purpose passive element array in which a plurality of passive elements are regularly arranged. And Then, a passive element to be used can be arbitrarily selected from the passive element array according to a desired circuit configuration.
[0018]
Here, in the fifth invention, the second step is a step of forming a first conductive thin film to be a lower electrode of the capacitor on the substrate thin film and a step of forming a dielectric thin film on the first conductive thin film And forming a second conductive thin film to be an upper electrode of the capacitor on the dielectric thin film.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is an exploded perspective view of a multilayer printed circuit board with a built-in component according to the present embodiment. The multilayer printed circuit board 1 is configured by stacking a plurality of wiring layers 2 and an array layer 3. Wirings 2 a are formed on the upper and lower surfaces of each wiring layer 2. In each wiring layer 2, a plurality of via holes 2b penetrating above and below the wiring layer 2 are provided at appropriate locations. The inside of the via hole 2b is filled with a conductor, through which interconnections necessary for the circuit configuration (upper / lower surface connection and interlayer connection) are made. The filling of the via hole 2b with a conductor is performed by, for example, a plating method, via filling with a conductor (for example, a bump in the form of a protrusion), or embedding of a conductive paste.
[0020]
On the other hand, the array layer 3 sandwiched between the upper and lower wiring layers 2 includes a passive element array including passive elements such as a capacitor (C), a resistor (R), and a coil (L). Is electrically connected to In the array layer 3, a plurality of via holes 3b are provided at appropriate locations, and interconnects (upper / lower surface connections, internal connections, and interlayer connections) necessary for a circuit configuration are provided by conductors filled therein. Done.
[0021]
In the present embodiment, the interlayer connection is performed by using a conductor filled in the via holes 2b and 3b as an electric path. However, the form of interlayer connection is not limited to this, and well-known connection methods including, for example, bonding between electrode pads formed on the layer surface can be widely used.
[0022]
FIG. 2 is a schematic perspective view of a passive element array used as the array layer 3. The passive element array 4 includes a group of “general-purpose” passive elements, for example, a plurality of passive elements 4 a regularly arranged in a matrix. The passive element 4a is one unit (passive element unit) of the passive element array 4, and is electrically separated from each other when no electrical connection is made to the passive element array. Although the passive element array 4 can be formed by integrating a large number of individual components, it is preferable to use a laminate of thin films as described later.
[0023]
Here, “general-purpose” means that it can be used without depending on the type of the multilayer printed circuit board 1, in other words, it has flexibility that can flexibly cope with various circuit configurations. Therefore, the passive element array 4 has a redundancy that the passive elements 4a are selected according to each kind. When designing a board of a certain type, passive elements 4a that are preferable in terms of circuit arrangement are selectively used as circuit elements, and unused passive elements 4a are redundant and useless elements in this type (however, other types are not used). May be used.) By using the general-purpose passive element array 4 having such redundancy regardless of the product type, it is possible to improve the flexibility in designing individual circuits and to make the design and manufacturing processes common.
[0024]
The passive element 4a selected from the passive element array 4 is used as a circuit element constituting a part of the entire circuit by connecting the wiring 2a to the passive element 4a. The following four use modes of the selected passive element 4a can be cited, and one of them or a combination thereof is set according to the connection of the wiring 2a and the formation of the via hole 3b. The passive element 4a, which is a two-terminal element, is provided with one terminal on each of the upper and lower sides, for example. Further, as the wiring used in this example, the wiring 2a on the upper and lower wiring layers 2 adjacent to the array layer 3 is used, but instead of or in addition to this, the wiring 2a is formed on the array layer 3 itself. The embedded wiring may be used.
[0025]
(1) Single use
A single passive element 4a is used as a circuit element. For example, as shown in A of the figure, the input / output of the circuit element is extracted from the upper and lower terminals of the single passive element 4a. For example, when the passive element 4a is a capacitor, the electric characteristic value (capacitance C) of this circuit element is a capacitance value C0 unique to the capacitor. In the two-dimensional plane defined by the passive element array 4, the most advantageous passive element 4a is selected in terms of circuit arrangement (the same applies to the following (2) to (4)).
[0026]
(2) Use in series
One in which a plurality of passive elements 4a are connected in series is used as a circuit element. For example, as shown in FIG. 2B, in the two passive elements 4a, the lower terminals are commonly connected, and the input / output of the circuit element is taken out from each upper terminal. For example, when the two passive elements 4a are capacitors having the same capacitance, the capacitance C of this circuit element is (C0 × C0) / (C0 + C0). This use form is effective when a value different from the characteristic value of the passive element 4a is set as the electrical characteristic value of the circuit element.
[0027]
(3) Parallel use
A circuit in which a plurality of passive elements 4a are connected in parallel is used as a circuit element. For example, as shown in C of the figure, in the two passive elements 4a, the upper terminals are commonly connected to take out one of the input / output, and the lower terminals are commonly connected to take out the other of the input / output. For example, when the two passive elements 4a are capacitors having the same capacitance, the capacitance C of this circuit element is (C0 + C0). This usage mode is effective from the viewpoint of improving the flexibility in circuit design by giving variations to the electrical characteristic values of the circuit elements, as in the above (2).
[0028]
(4) Use for connection between upper and lower surfaces
The function as the passive element 4a is invalidated and used as an electrical path connecting the upper and lower surfaces of the array layer 3. For example, as shown in D of the same figure, in a single passive element 4a, a via hole 3b penetrating the upper and lower sides thereof is provided, and the wiring 2a is electrically connected to the upper and lower sides via this.
[0029]
The passive element array 4 may be composed of a single type of passive element 4a (for example, a capacitor unit), and in this case, these may have the same electrical characteristic value (capacitance value). However, as long as the versatility of the passive element array 4 is maintained, it is not necessary that all the passive elements 4a be of the same type, and it is not necessary that all the passive elements 4a have the same electrical characteristic value. . Therefore, for example, the passive element array 4 may be composed of a plurality of different types of passive elements 4a such as a capacitor and a resistor. Further, even when the passive element 4a is constituted by a single type of passive element, its electrical characteristic value may be changed, for example, by changing its shape or material.
[0030]
FIG. 3 is an explanatory diagram of the manufacturing process of the multilayer printed circuit board 1. The printed circuit board 1 is typically manufactured by a thermoplastic collective pressure bonding process, but may be manufactured by using an adhesive layer fixed on a thermosetting layer. First, in step 1, a substrate thin film 10 such as a polymer thin film, for example, which is a base substrate of the wiring layer 2, is prepared. In the following step 2, the metal thin film 11 is laminated on the substrate thin film 10. In step 3, the metal thin film 11 is subjected to light exposure and etching, so that the wiring layer 2 having the wiring 2a having a different pattern for each layer is formed by printing. In step 4, formation of via holes 2b and necessary interconnection are performed in each sheet-like wiring layer 2. In step 5, the array layer 3 is inserted between the adjacent upper and lower wiring layers 2 to form a stacked body in an order according to the configuration of the printed circuit board 1. Then, in step 6, the printed circuit board 1 with a built-in component is completed by integrating the laminated body composed of the layers 2 and 3 by, for example, thermoplastic batch pressing.
[0031]
Next, a manufacturing process of the array layer 3 including the capacitor array will be described as an example of the passive element array with reference to FIG. On the sheet-like array layer 3, a capacitor array 24 which is a set of capacitor units 24a arranged at high density is formed. The array layer 3 is manufactured separately from the manufacturing process of the multilayer printed circuit board 1 described above. The manufacturer of the array layer 3 may be the manufacturer of the printed circuit board 1 itself, or may be another third party. In a case where a board manufacturer receives a component supply from a third party, the product assurance on the component is usually performed by the third party in many cases. Therefore, it is possible for the substrate manufacturer who receives the supply of the array layer 3 to reduce the quality control cost to be borne by the substrate manufacturer. Usually, it is assumed that the board manufacturer receives the supply of the array layer 3 as a general-purpose component from a third party, customizes the same, and then incorporates it as a layer of the multilayer printed circuit board 1.
[0032]
In step 11, a substrate thin film 20 serving as a base substrate of the array layer 3 is prepared. The substrate thin film 20 is preferably made of the same material (for example, a polymer thin film) as the substrate thin film 10 used in the manufacturing process of the printed circuit board 1 described above. Thereby, the array layer 3 can be manufactured by the same manufacturing process as that of the printed circuit board 1, and the affinity of the material in each layer can be secured.
[0033]
In the following Steps 12 to 15, a passive element layer as the capacitor array 24 is formed. First, in step 12, a metal thin film 21, which is one of the passive element layers, is laminated on the substrate thin film 20. In step 13, the metal thin film 21 is exposed to light and etched to form a pattern of a plurality of lower electrodes 21a arranged in a matrix. Each lower electrode 21a has the same shape and the same area, and is separated from each other. In step 14, a dielectric film 22, which is one of the passive element layers, is stacked on the substrate thin film 20 on which the lower electrode 21a is formed. In step 15, a metal thin film 23, which is one of the passive element layers, is stacked on the dielectric film 22. In step 16, the metal thin film 23 is exposed to light and etched to form a pattern of a plurality of upper electrodes 23a arranged in a matrix. Each upper electrode 23a has the same shape and the same area, and is separated from each other. Thus, the capacitor array 24 including the passive element layers 21a, 22, 23a is completed. Each capacitor unit 24a constituting the capacitor array 24 has the same capacitance value and is electrically separated from each other. Then, in step 17, via holes 3b are formed at appropriate positions in order to customize the electrical connection according to the type of the printed circuit board 1 to be manufactured. As a result, the customized array layer 3 suitable for a specific type is completed. Note that a wiring may be formed on the array layer 3 itself if necessary.
[0034]
The manner of customizing the capacitor array 24 differs depending on the structure of the capacitor unit 24a. Hereinafter, three customizing methods will be described with reference to three configuration examples of the capacitor unit 24a.
[0035]
(First configuration example)
FIG. 5 is a sectional view showing a first configuration example of the capacitor unit 24a. The upper electrode 23a is an individual electrode formed for each capacitor unit 24a. On the other hand, the lower electrode 21a is a common electrode common to the plurality of capacitor units 24, and a ground voltage is applied to the lower electrode 21a. This type of customization depends on the connection of the wiring 2a located above the passive element layer. When a certain capacitor unit 24a is used as a circuit element, the upper wiring 2a is connected to the upper electrode 23a. On the other hand, with respect to the unused capacitor unit 24a, such wiring connection to the upper electrode 23a is not performed. In this type, since the lower electrode 21a is a common electrode, there is a restriction that (2) cannot be used in series among the above four usage modes (1) to (4). Further, in the case of the above usage mode (4), the via hole 3b needs to have a structure as shown in FIG. 9 described later.
[0036]
(Second configuration example)
FIG. 6 is a sectional view showing a second configuration example of the capacitor unit 24a. The upper and lower electrodes 21a and 23a are individual electrodes formed for each capacitor unit 24a. This type of customization depends on the connection of the upper and lower wirings 2a and the formation of the via holes 3b. When a certain capacitor unit 24a is used as a circuit element, a via hole 3b penetrating vertically through the substrate thin film 20 is formed at a position corresponding to the lower electrode 21a. Then, the wiring 2a located above the passive element layer is connected to the upper electrode 23a, and the wiring 2a located below this is connected to the lower electrode 21a. On the other hand, for the unused capacitor unit 24a, such via hole formation and wiring connection are not performed. In this type, customization can be freely performed without any restriction on the above-mentioned usage patterns (all of the usage patterns (1) to (4) can be realized).
[0037]
(Third configuration example)
FIG. 7 is a sectional view showing a third configuration example of the capacitor unit 24a. The upper and lower electrodes 21a and 23a extend in a predetermined direction, and a portion where they intersect becomes a capacitor unit 24a. This type of customization depends on the connection of the wiring 2a located above the passive element layer and the formation position of the via hole 3b. When a certain capacitor unit 24a is used as a circuit element, a via hole 3b penetrating through the dielectric film 22 is formed at a position corresponding to the lower electrode 21a, and a wiring 2a is formed on the upper and lower electrodes 21a and 23a, respectively. Connecting. On the other hand, for the unused capacitor unit 24a, such via hole formation and wiring connection are not performed. This type can be freely customized without restriction on the use form, similarly to the type of FIG.
[0038]
When an area corresponding to a certain capacitor unit 24a is used as a mere electric path as in the usage pattern (4) described above, it is necessary to form a via hole 3b penetrating vertically above and below the array layer 3. Hereinafter, two configuration examples of the via hole 8b will be described. FIG. 8 is a cross-sectional view illustrating a first configuration example of the via hole 3b. When a certain capacitor unit 24a is used for this purpose, a via hole 3b is formed from the upper electrode 23a to the lower surface of the substrate thin film 20 via the lower electrode 21a, in which a conductor is present. Then, the wiring 2a located above the passive element layer and the wiring 2a located below the passive element layer are electrically connected via the via hole 3b. As a result, the upper and lower electrodes 21a and 23a conduct, so that the function as a capacitor is invalidated, and this portion becomes a simple electric path. FIG. 9 is a sectional view showing a second configuration example of the via hole 3b. The difference from the via hole 8b shown in FIG. 8 is that a relatively thin insulating film 3c is formed on the inner wall of the via hole 3b. As a result, the upper and lower wirings 2a, 2a and the electrodes 21a, 23a can be electrically separated, which is advantageous in terms of inductance.
[0039]
The capacitor units 24a constituting the capacitor array 24 need not all have the same electrode shape, and may have, for example, an electrode shape as shown in FIG. 10 or FIG. FIG. 10 is a top view illustrating a first configuration example of the capacitor array 24. This capacitor array 24 is composed of a first capacitor unit group 24b having a rectangular electrode of a certain area and a second capacitor unit group 24c having a rectangular electrode of a smaller area. Each of the first capacitor unit groups 24b has the same capacitance value C1. Also, each of the second capacitor units 24c has the same capacitance value C2, but this capacitance value C2 is smaller than the capacitance value C1. By providing a plurality of passive element groups having different electric characteristic values in this manner, flexibility can be improved with respect to setting of a capacitance value as a circuit element. FIG. 11 is a top view illustrating a second configuration example of the capacitor array 24. In this example, the electrode shape is hexagonal in order to increase the density of the capacitor unit 24a.
[0040]
In this embodiment, an array layer 3 having a general-purpose passive element array 4 is used as one layer of the multilayer printed circuit board 1. Then, a passive element 4a necessary for the configuration of a desired circuit is selected from the passive element array 4 according to the type of the printed circuit board 1, and the electrical connection is made via the via holes 3b and the like. As described above, by using the general-purpose passive element array 4, the flexibility in circuit design is improved, and it is easy to cope with various multilayer printed circuit boards 1. As a result, the circuit design of the multilayer printed circuit board 1 can be saved, and the cost required for developing and manufacturing the multilayer printed circuit board 1 can be reduced. Further, by incorporating the passive element 4a in the multilayer printed circuit board 1, the number of individual components mounted on the surface of the board can be reduced. As a result, it is possible to reduce the space on the substrate surface and reduce the size of the substrate itself by the reduced number.
[0041]
【The invention's effect】
In the present invention, an array layer including a general-purpose passive element array in which a plurality of passive elements are regularly arranged is used as one layer of the multilayer printed circuit board. Then, in order to configure a desired circuit, an electrical connection is made with respect to a passive element selected from the passive element array. Thus, the circuit design of the printed circuit board can be labor-saving, and it is easy to handle various types.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view of a multilayer printed circuit board.
FIG. 2 is a schematic perspective view of a passive element array.
FIG. 3 is an explanatory diagram of a manufacturing process of a multilayer printed circuit board.
FIG. 4 is an explanatory diagram of a manufacturing process of an array layer.
FIG. 5 is a sectional view showing a first configuration example of a capacitor unit;
FIG. 6 is a sectional view showing a second configuration example of the capacitor unit;
FIG. 7 is a sectional view showing a third configuration example of the capacitor unit;
FIG. 8 is a sectional view showing a first configuration example of a via hole.
FIG. 9 is a sectional view showing a second configuration example of the via hole.
FIG. 10 is a top view showing a first configuration example of a capacitor array.
FIG. 11 is a top view showing a second configuration example of the capacitor array.
[Explanation of symbols]
1 multilayer printed circuit board
2 Wiring layer
2a Wiring
2b Via hole
3 Array layer
3b Via hole
3c insulating film
4 Passive element array
4a Passive element
10. Substrate thin film
11 Metal thin film
20 Substrate thin film
21 Metal thin film
21a Lower electrode
22 Dielectric film
23 Metal thin film
23a upper electrode
24 capacitor array
24a capacitor unit
24b First capacitor unit group
24c Second capacitor unit group

Claims (20)

In a multilayer printed circuit board configured by laminating a plurality of layers,
A wiring layer on which wiring is formed;
Including a general-purpose passive element array in which a plurality of passive elements are regularly arranged, and having an array layer electrically connected to the wiring layer,
A multilayer printed circuit board, wherein an electrical connection is made with respect to the passive element selected from the passive element array to form a desired circuit. The multilayer printed circuit board according to claim 1, wherein the passive element array includes a first passive element group of the same type. The first passive element group includes a first passive element having a predetermined electric characteristic value and a second passive element having an electric characteristic value different from the first passive element. The multilayer printed circuit board according to claim 2, wherein 4. The multilayer printed circuit board according to claim 2, wherein the passive element array includes a second passive element group of a type different from the first passive element group. The array layer comprises:
A substrate thin film,
5. The passive element layer formed on the substrate thin film, and each of the passive elements constituting the passive element array has a passive element layer electrically separated from each other. The described multilayer printed circuit board. The passive element is a capacitor,
The passive element layer,
A first conductive thin film formed on the substrate thin film and serving as a lower electrode of the capacitor;
A dielectric thin film formed on the first conductive thin film;
The multilayer printed circuit board according to claim 5, further comprising a second conductive thin film formed on the dielectric thin film and serving as an upper electrode of the capacitor. The lower electrode is a common electrode common to a plurality of the capacitors,
The upper electrode is an individual electrode formed for each of the capacitors,
7. The capacitor according to claim 6, wherein a wiring located above the passive element layer is electrically connected to the upper electrode with respect to the capacitor selected to form a desired circuit. Multilayer printed circuit board. The lower electrode is an individual electrode formed for each of the capacitors,
The upper electrode is an individual electrode formed for each of the capacitors,
With respect to the capacitor selected to form a desired circuit, a first wiring located above the passive element layer is electrically connected to the upper electrode and is located above the passive element layer. 7. The multilayer printed circuit board according to claim 6, wherein the lower second wiring is electrically connected to the lower electrode through a via hole penetrating the substrate thin film. The capacitor corresponds to a portion where the lower electrode extending in a predetermined direction and the upper electrode extending in a predetermined direction intersect,
With respect to the capacitor selected to form a desired circuit, a first wiring located above the passive element layer is electrically connected to the upper electrode and is located above the passive element layer. 7. The multilayer printed circuit board according to claim 6, wherein the second wiring located on the upper side is electrically connected to the lower electrode via a via hole penetrating the dielectric film. Regarding the capacitor selected to form a desired circuit, a via hole is formed from the upper electrode to the lower surface of the substrate thin film via the lower electrode, and a via hole located above the passive element layer is formed. 7. The multilayer according to claim 6, wherein the first wiring and the second wiring located below the passive element layer are electrically connected to each other via the via hole. Printed circuit board. The insulating film for electrically separating the first wiring and the second wiring from the upper electrode and the lower electrode is formed on an inner wall of the via hole. 11. The multilayer printed circuit board according to 10. In a passive element array used as one layer of a multilayer printed circuit board configured by laminating a plurality of layers,
The passive element array is a general-purpose array in which a plurality of passive elements are regularly arranged, each of the passive elements is electrically separated from each other, and according to a desired circuit configuration, The passive element array, wherein the passive element to be used can be arbitrarily selected from the passive element array. In a passive element array used as one layer of a multilayer printed circuit board configured by laminating a plurality of layers,
A substrate thin film,
A passive element layer formed on the substrate thin film, having a general-purpose passive element array in which a plurality of passive elements are regularly arranged, and a passive element layer in which each of the passive elements is electrically separated from each other. Have
The passive element array, wherein the passive element to be used can be arbitrarily selected from the passive element array according to a desired circuit configuration. 14. The passive element array according to claim 12, wherein the passive element array includes a first passive element group of the same type. The first passive element group includes a first passive element having a predetermined electric characteristic value and a second passive element having an electric characteristic value different from the first passive element. The passive element array according to claim 14, wherein 16. The passive element array according to claim 14, wherein the passive element array includes a second passive element group of a type different from the first passive element group. The passive element is a capacitor,
The passive element layer,
A first conductive thin film formed on the substrate thin film and serving as a lower electrode of the capacitor;
A dielectric thin film formed on the first conductive thin film;
14. The passive element array according to claim 13, further comprising a second conductive thin film formed on the dielectric thin film and serving as an upper electrode of the capacitor. In a method for manufacturing a multilayer printed circuit board configured by laminating a plurality of layers,
A first step of forming a plurality of wiring layers having wiring,
In an array layer having a general-purpose passive element array in which a plurality of passive elements are regularly arranged, an electrical connection related to the passive element selected from the passive element array is selected according to a desired circuit configuration. A second step to perform;
A third step of forming a stacked body that is stacked in the order of forming the multilayer printed circuit board by inserting the array layer between the plurality of wiring layers;
And a fourth step of integrating the laminate. In a method of manufacturing a passive element array used as one layer of a multilayer printed circuit board configured by laminating a plurality of layers,
A first step of preparing a substrate thin film;
A second step of forming a passive element layer that becomes a general-purpose passive element array in which a plurality of passive elements are regularly arranged on the substrate thin film,
A method of manufacturing a passive element array, wherein the passive element to be used can be arbitrarily selected from the passive element array according to a desired circuit configuration. The second step is
Forming a first conductive thin film to be a lower electrode of a capacitor on the substrate thin film;
Forming a dielectric thin film on the first conductive thin film;
20. The method according to claim 19, further comprising: forming a second conductive thin film on the dielectric thin film to be an upper electrode of the capacitor.

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