JP2004288997A - Method for manufacturing ferroelectric device, ferroelectric device, ferroelectric memory, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a ferroelectric device in relatively few processes and a structure of the ferroelectric device. <P>SOLUTION: This method for manufacturing a ferroelectric device structured to apply an electric field to a ferroelectric layer formed by a ferroelectric comprises a process(ST2) for forming a barrier layer 102 on an insulating layer 10, a process(ST2) for forming a lower electrode layer 103 on the barrier layer 102, a process(ST3) for forming a lower electrode group constituted of a plurality of lower electrode wiring by etching the lower electrode layer 103, a process(ST4) for forming a ferroelectric layer 104 on the lower electrode group, a process(ST4) for forming an upper electrode layer 105 on the ferroelectric layer 104, and a process(ST4) for forming the upper electrode group constituted of a plurality of upper electrode wiring crossing the lower electrode group through the ferroelectric layer by etching the upper electrode layer 105 and the ferroelectric layer 104. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory, and more particularly, to a structure of a ferroelectric memory that can be manufactured by relatively simple steps and a method of manufacturing the same.
[0002]
[Prior art]
A ferroelectric memory has features such as a writing speed comparable to that of an SRAM and a large number of rewritable times, and is attracting attention as a next-generation nonvolatile memory. There is a form in which a drive circuit is provided for each memory element, and a form in which a drive circuit is provided outside the wiring layer with a ferroelectric interposed between the wiring layers. The latter is preferable as a structure capable of high-density integration. .
[0003]
Conventionally, as a method of manufacturing such a ferroelectric memory, for example, a manufacturing method described in Japanese Patent Application Laid-Open No. 2002-299579 has been known (Patent Document 1). According to this publication, a lower electrode layer, a ferroelectric layer, and an upper electrode layer are successively formed on a substrate, and then the upper electrode layer and the ferroelectric layer are etched to form an upper electrode wiring. There is disclosed a manufacturing method in which a lower electrode wiring is formed by masking an electrode wiring and then performing etching again. Forming the lower ferroelectric layer which is originally located in the lower layer and then forming the upper ferroelectric layer is simple and requires few steps, but since the ferroelectric layer reacts with the oxide film and deteriorates the characteristics, It had to go through such complicated steps.
[0004]
[Patent Document 1]
JP-A-2002-299579
[Problems to be solved by the invention]
However, since a step of masking the upper electrode wiring is required in order to pattern the lower electrode wiring after forming the upper electrode wiring, complication of the process was inevitable.
[0005]
Further, in the ferroelectric memory formed by the above-described manufacturing method, the oxide film and the lower electrode are close to each other at a distance of about the thickness of the lower electrode below the ferroelectric material, so that the reaction between the ferroelectric material and the oxide film does not occur. There was a possibility that the advanced ferroelectric material was deteriorated.
[0006]
Accordingly, it is an object of the present invention to provide a manufacturing method for manufacturing a ferroelectric device with relatively few steps and a structure of the ferroelectric device.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is a method for manufacturing a ferroelectric device having a structure for applying an electric field to a ferroelectric layer formed of a ferroelectric, wherein a barrier layer is formed on an insulating film. Forming a lower electrode layer on the barrier layer, etching the lower electrode layer to form a lower electrode group including a plurality of lower electrode wirings, and forming a ferroelectric layer on the lower electrode group. Forming, forming an upper electrode layer on the ferroelectric layer, etching the upper electrode layer and the ferroelectric layer, and intersecting the lower electrode group and the ferroelectric layer via the ferroelectric layer. Forming an upper electrode group consisting of electrode wirings.
[0008]
According to the above process, the ferroelectric layer is formed after the lower electrode wiring is formed first. However, since the barrier layer is provided below the lower electrode layer, the insulating film and the ferroelectric layer are directly Contact and reaction can be prevented. Therefore, there is no need to go through a complicated process of masking the upper electrode and then patterning the lower electrode, thereby providing an effect that the process can be simplified as compared with the related art.
[0009]
Here, in the present invention, there is no limitation on the material of the “ferroelectric substance”. For example, a material capable of maintaining a continuous physical state by polarization can have a memory function.
[0010]
The “barrier layer” may be any material and thickness that can block the movement of elements from the ferroelectric layer to the insulating film or in the opposite direction. For example, in the step of forming a barrier layer, it is preferable to deposit a metal oxide to form the barrier layer. This is because the interposition of the metal oxide can prevent the ferroelectric layer from reacting with the insulating film. For example, TiOx is mentioned as such a metal oxide.
[0011]
The “insulating film” may be any material as long as it has no conductivity, and includes a substrate such as silicon or glass in addition to an oxide film.
[0012]
Here, in the step of forming the lower electrode group, it is preferable to perform over-etching up to the upper layer of the barrier layer. According to this step, even if a variation in the etching rate or a variation in the thickness of the lower electrode layer occurs due to over-etching of the upper layer portion of the barrier layer, the lower electrode layer extends to a portion exceeding the variation width. This is because the metal wiring can be reliably separated from each other.
[0013]
Here, in the step of forming the upper electrode group, it is preferable to perform etching so that the lower layer of the ferroelectric layer remains in a region other than the region where the lower electrode layer remains. According to this step, since the ferroelectric layer is under-etched, it is possible to prevent the ferroelectric layer from being completely removed and the lower electrode layer and the like below from being etched. Further, since the barrier layer prevents the exposure of the insulating film, there is no problem even if the ferroelectric remains.
[0014]
According to the present invention, there is provided a ferroelectric device having a structure for applying an electric field to a ferroelectric layer formed of a ferroelectric, comprising: an insulating film; and a plurality of lower electrode wirings formed on the insulating film. , An upper electrode group including a plurality of upper electrode wirings intersecting the lower electrode group, and a ferroelectric layer formed at least in an intersection region between the lower electrode wiring and the upper electrode wiring. Further, a barrier layer is provided between the insulating film and the ferroelectric layer.
[0015]
According to the above configuration, since the barrier layer is provided below the lower electrode layer, the insulating film and the ferroelectric layer can be prevented from directly contacting and reacting with each other. Can be provided. In the manufacturing process, a process of forming a lower electrode wiring first and then forming a ferroelectric layer can be adopted, and a complicated process of masking the upper electrode and then patterning the lower electrode as in the related art can be adopted. Since there is no need to go through, there is an operational effect that the process can be simplified as compared with the related art.
[0016]
Here, the ferroelectric layer is preferably formed in a region other than the lower layer of the upper electrode wiring. This means that the ferroelectric device having such a structure is etched to such an extent that the lower layer of the ferroelectric layer remains in a region other than the region where the lower electrode layer remains. Therefore, in such a device, there is no possibility that the ferroelectric layer is completely removed and the lower electrode layer and the like below are etched. Further, since the barrier layer prevents the exposure of the insulating film, there is no problem even if the ferroelectric remains.
[0017]
Here, it is preferable that the ferroelectric layer formed in a region other than the lower layer of the upper electrode wiring is formed thinner than the ferroelectric layer formed in the lower layer of the upper electrode wiring. Such a structure is formed in a step of etching such that the lower layer of the ferroelectric layer remains in a region other than the region where the lower electrode layer remains. Therefore, the ferroelectric layer is not completely removed and the lower electrode layer and the like below are not etched. Further, since the barrier layer prevents the exposure of the insulating film, there is no problem even if the ferroelectric remains.
[0018]
Here, the ferroelectric layer formed below the intersection area between the upper electrode wiring and the lower electrode wiring is a region other than the lower layer below the intersection area and the ferroelectric layer formed below the upper electrode wiring. They are formed to have substantially the same thickness. According to this configuration, it means that the lower electrode is not formed after the formation and etching of the upper electrode layer and the ferroelectric layer, and the ferroelectric layer obtained when the manufacturing method of the present invention is used. It has structural features.
[0019]
Here, it is preferable that the lower electrode wiring is provided on the projecting structure of the barrier layer. Such a protruding structure is formed in a step of over-etching the upper layer portion of the barrier layer. Therefore, even if a variation in the etching rate or a variation in the thickness of the lower electrode layer occurs, the lower electrode layer is removed to a portion exceeding the variation width, so that the metal wiring can be reliably separated.
[0020]
The present invention is a ferroelectric memory including a peripheral circuit that supplies a word selection signal and a bit selection signal to each of a lower electrode group and an upper electrode group. According to this configuration, the lower electrode group becomes the word selection signal line, and the upper electrode group becomes the bit selection signal line, and the supply of the word selection signal and the bit selection signal from the peripheral circuit causes polarization in the ferroelectric material in each intersection region. To operate as a memory.
[0021]
The present invention is also an electronic apparatus including a ferroelectric device of the present invention or a ferroelectric device or a ferroelectric memory manufactured by the method of manufacturing a ferroelectric device of the present invention. According to this configuration, since the electronic device includes the ferroelectric device or the memory, the ferroelectric in the device or the memory is hardly deteriorated, and the electronic device is manufactured by a simplified process. Can be kept low.
[0022]
Here, “electronic equipment” refers to general equipment having a certain function provided with a ferroelectric device or a ferroelectric memory according to the present invention, and the configuration thereof is not particularly limited. Equipped personal computer, mobile phone, video camera, head mounted display, rear or front type projector, fax device with display function, digital camera finder, portable TV, DSP device, PDA, electronic notebook, electronic bulletin board, A display for publicity announcement is included.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024]
(1st Embodiment)
The first embodiment of the present invention relates to a ferroelectric memory having a structure as a ferroelectric device of the present invention and manufactured by the method of manufacturing a ferroelectric device of the present invention. FIG. 1 shows a perspective view of a memory cell array of the ferroelectric memory 1 according to the first embodiment. In the perspective view, illustration of the protective layer is omitted to clarify the crossing structure of the electrode wiring.
[0025]
As shown in FIG. 1, the memory cell array in the ferroelectric memory 1 includes a lower electrode group 12 composed of lower electrode wirings 12-n-1 to 12-n + 1 (1 ≦ n ≦ X) and an upper electrode wiring 11-. The upper electrode group 11 composed of m-1 to 11-m + 1 (1 ≦ m ≦ Y) intersects. A ferroelectric layer 104 is formed below the upper electrode wiring 11. In the present embodiment, the lower electrode group 12 is formed of a plurality of layers, but the uppermost layer is formed of a platinum layer 103c. The upper electrode group 11 is also formed of the platinum layer 105.
[0026]
FIG. 4 is a schematic plan view of the entire ferroelectric memory 1 including the memory cell array 10, and FIG. 5 is a cross-sectional view of the ferroelectric memory along a lower electrode line 12-1 which is a word line, taken along a CC cutting plane. FIG.
[0027]
As shown in FIG. 4, the upper electrode wirings 11-1 to 11-Y intersect on the lower electrode wirings 12-1 to 12-X, and are sandwiched in the intersection region of both wirings. The ferroelectric layer 104 forms each memory cell. The lower electrode group 12 is configured so that a bit signal can be output from the peripheral circuit 3. The peripheral circuit 3 includes a circuit suitable for selecting a memory cell, such as an X gate, a sense amplifier, an input / output buffer, an X address decoder, and an address buffer. Have.
A word signal can be output from the peripheral circuit 2 to the upper electrode group 11. The peripheral circuit 2 includes a circuit suitable for selecting a memory cell, such as a Y gate, a sense amplifier, an input / output buffer, a Y address decoder, and an address buffer. Have. Gates such as transistors are formed inside the peripheral circuits 2 and 3.
[0028]
As a layer structure, as shown in FIG. 5, a barrier layer 102, a lower electrode layer 103, a ferroelectric layer 104, and an upper electrode layer 105 are formed on an insulating film 101 formed on a substrate 100, A first protective layer 109 is formed thereon. A second protective layer 110 is formed thereon. FIG. 5 shows a state in which the last-stage transistor of the peripheral circuit 2 is connected to the lower electrode layer 103. The transistor in the peripheral circuit 2 includes a source / drain 111 formed in the substrate 100 and a gate insulating film 106 and a gate electrode 107 formed on a channel region between them. Source / drain electrodes 108 are formed between the first protective layer 109 and the second protective layer 110.
[0029]
In such a configuration, the peripheral circuits 2 and 3 are driven to select the lower electrode wiring 12-n and the upper electrode wiring 11-m, which are word lines, and to store a predetermined value or more in the memory cell in the n-th column and the m-th row. Is applied, the ferroelectric layer of the memory cell is polarized, and information corresponding to the polarity of the voltage is recorded. When a predetermined memory cell is selected from the peripheral circuits 2 and 3, a voltage corresponding to the polarization state is obtained, and the recorded information can be read. When rewriting is performed, a voltage that eliminates the polarization state is applied again to the memory cell.
[0030]
Further, the layer structure will be described in detail. FIG. 2 is a cross-sectional view as viewed from the AA cross section of FIG. 1, and FIG. 3 is a cross-sectional view as viewed from the BB cross section of FIG. As shown in FIGS. 2 and 3, in the layer structure of the ferroelectric memory 1, a substrate 100, an insulating film 101, a barrier layer 102, and a lower electrode layer 103 are sequentially stacked from the lower layer. A ferroelectric layer 104 and an upper electrode layer 105 are further formed in a region where the upper electrode wiring 11-m crosses the lower electrode wiring 12-n. The lower electrode group 12 is formed by patterning the lower electrode layer 103 so as to form a lower electrode wiring according to the protruding structure on the barrier layer 102. The upper electrode group 11 is formed by patterning the ferroelectric layer 104 and the upper electrode layer 105 so as to cross the lower electrode group 12. Hereinafter, description will be made in order from the lower layer.
[0031]
The substrate 100 is a base on which the ferroelectric memory 1 is formed, and a suitable rigid glass plate or silicon substrate on which the insulating film 101 can be formed can be used.
[0032]
The insulating film 101 needs to be formed of a material having low electrical conductivity for the lower electrode wiring, and a predetermined oxide film, for example, SiO 2 ₂ A membrane is applied. It is known that such an oxide film reacts with, for example, a ferroelectric material containing lead to generate lead oxide, thereby deteriorating the characteristics of the ferroelectric. In the present invention, this problem is solved by forming a barrier layer on the insulating film. The thickness of the insulating film is 5000 ° or more. This is to ensure sufficient insulation performance.
[0033]
The barrier layer 102 is formed of a material having a shielding function capable of preventing the ferroelectric material forming the ferroelectric layer 104 from reacting with the insulating film material forming the insulating film 101. As such a material, various metal oxide films are suitable because of their characteristics and ease of formation. For example, compositions suitable for the barrier layer include titanium oxide (TiOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and magnesium oxide (MgOx). The film thickness required for the barrier layer is the thinnest part to be etched away, preferably 3000 to 5000 or more, more preferably 10000 or more. This is because it is considered that the greater the thickness, the more the barrier effect can be obtained. The formation method is suitable as a method for forming a metal oxide thin film and may be any method capable of forming a barrier layer with a uniform thickness, and can be appropriately selected according to various conditions such as the composition and thickness of the layer. . For example, various vapor deposition methods such as CVD (including MOCCVD, low pressure CVD, and ECR-CVD), vapor deposition, molecular beam deposition (MB), sputtering, ion plating, and PVD, electroplating, and immersion plating ( Dipping), various plating methods such as electroless plating method, coating methods such as Langmuir-Blodgett (LB) method, spin coating method, spray coating method, roll coating method, various printing methods, transfer method, ink jet method, powder jet method And so on. Two or more of these methods may be combined.
[0034]
The lower electrode layer 103 is formed by stacking a titanium (Ti) layer 103a, a titanium oxide (TiOx) layer 103b, and a platinum (Pt) layer 103c. The titanium layer 103a is an adhesion layer that enhances the adhesion between the barrier layer 102 and the platinum layer 103b, and is a material capable of increasing the adhesion between the two layers by being interposed between the two layers, for example, Pt, Ir, Au, It is formed of a metal such as W, Ta, Mo, Al, Cr, Ti or an alloy containing these as main components. The thickness of the adhesion layer is appropriately determined according to the purpose of the formation. For example, it is formed to a thickness of about 200 °. Eventually, the thickness will be reduced to about 100 ° by the next thermal oxidation step.
[0035]
The titanium oxide layer 103b is a metal oxide film having a dense crystal structure for orienting the platinum layer 103c in an appropriate direction (for example, the [111] direction). This is because if the platinum layer is oriented in a uniform direction, the crystal state of the ferroelectric layer grown from the platinum layer can be made uniform, and the characteristics of the ferroelectric layer can be improved. In order to form this dense metal oxide film, it is preferable to thermally oxidize the upper layer of the adhesion layer 103a to form titanium oxide crystals.
[0036]
The platinum layer 103c is an electrode paired with the upper electrode wiring 11-m for applying a voltage to the ferroelectric layer, and has a conductive material, for example, a titanium (Ti) layer, iridium (Ir), platinum It is composed of a (Pt) layer, a titanium (Ti) layer, or a stack of these oxides (IrOx, etc.). The thickness may be such that it can adhere uniformly and ensure conductivity, for example, about 2000 mm.
[0037]
The ferroelectric layer 104 has a function of recording information in each memory cell in the ferroelectric memory. The ferroelectric layer 104 shifts digital information “0” or “1” in the polarization direction by dielectric polarization in the ferroelectric crystal structure. It is a layer that can be stored in association with it. As a material of the ferroelectric layer, a ferroelectric ceramic suitable for a ferroelectric memory, for example, lead zirconate titanate (Pb (Zr, Ti) O) ₃ : PZT), barium strontium titanate (SBT), BST and the like can be used. The thickness is the amount of polarization from which information can be read as a memory cell of the ferroelectric memory, and is set to a thickness that does not cause any trouble such as generation of cracks due to thickening. Since the ferroelectric layer 104 is crystallized while inheriting the crystal state of the underlying layer in the crystal growth process after the formation of the thin film, a crystal is densely formed at least in a region intersecting with the lower electrode layer 103. A crystal having a uniform orientation and inheriting the crystal state of the titanium oxide layer 103c is sandwiched. The ferroelectric layer 104 is patterned together with the upper electrode layer 105 and extends in a direction crossing the lower electrode group 12.
[0038]
The upper electrode layer 105 is an electrode paired with the lower electrode wiring 12-n for applying a voltage to the ferroelectric layer, and has a conductive material, for example, a titanium (Ti) layer, a platinum (Pt) layer. , And a titanium (Ti) layer. The thickness may be such that it can adhere uniformly and ensure conductivity, for example, about 2000 mm.
[0039]
Next, a method of manufacturing the ferroelectric memory according to the present embodiment will be described with reference to the manufacturing process diagram of FIG. FIG. 6 shows a change in the lamination state in a cross section corresponding to the AA cross section in FIG. Note that the present embodiment relates to a ferroelectric memory. For example, a transistor is provided below a memory cell because it is driven from a peripheral circuit as disclosed in Patent Document 1 (see FIG. 4). Since they are not shown, they are not shown. However, in the case where a transistor is provided in an intersection region between a word line and a bit line as described in Japanese Patent Application Laid-Open No. H11-214642, a transistor for driving a ferroelectric layer in units of cells is provided around a memory cell. Just do it.
[0040]
Here, as the substrate 100, a silicon single crystal substrate is used. Also, as shown in FIG. 5, it is assumed that transistors required for the configuration of the peripheral circuits 2 and 3 are formed in advance on the substrate 100 by a predetermined semiconductor process.
[0041]
First, a barrier layer 102 according to the present invention is formed on an insulating film 101 formed on a substrate 100. A known oxide film forming (ST1) method is applied to a silicon substrate, for example, by applying a thermal oxidation method to SiO ₂ A film (insulating film 101) is formed to a predetermined thickness, for example, about 4000 °. Next, a predetermined metal oxide, here, titanium oxide (TiOx) is formed as a barrier layer 102 on the insulating film 101 to a predetermined thickness, for example, about 3000 to 5000 °. The formation method is suitable as a method for forming a metal oxide thin film and may be any method capable of forming a barrier layer with a uniform thickness, and can be appropriately selected according to various conditions such as the composition and thickness of the layer. . For example, various vapor deposition methods such as CVD (including MOCCVD, low pressure CVD, and ECR-CVD), vapor deposition, molecular beam deposition (MB), sputtering, ion plating, PVD, electroplating, and immersion plating ( Dipping), various plating methods such as electroless plating method, coating methods such as Langmuir-Blodgett (LB) method, spin coating, spray coating method, roll coating method, various printing methods, transfer method, ink jet method, powder jet method And so on. Two or more of these methods may be combined. Here, the barrier layer 102 is formed with a thickness of about 3000 to 5000 ° by a sputtering method or an evaporation method.
[0042]
Next, the lower electrode layer 103 is formed (ST2). First, a metal layer 103a serving as an adhesion layer is formed. Here, titanium is used as the metal having high adhesion, and is formed to have a predetermined thickness, for example, a thickness of 200 ° including the upper layer portion to be thermally oxidized. As the formation method, the above-described method for forming the barrier layer can be used. Subsequently, the upper layer portion of the titanium layer 103a is thermally oxidized to form dense titanium oxide. For example, by performing thermal oxidation in an oxygen atmosphere at 700 ° C. for one hour, a dense titanium oxide layer 103b of about 100 ° is formed. The titanium oxide layer 103b is a dense film and is plane-oriented in the [111] direction. Further, a platinum layer 103c is formed on the titanium oxide layer 103b. Here, platinum is formed to a thickness of about 2000 ° by a sputtering method or the like.
[0043]
Next, when the lower electrode layer 103 is formed, the lower electrode layer 103 is etched to form a wiring shape of the lower electrode group 12 (ST3). This etching is performed by applying a known etching technique after forming a resist pattern by each process such as resist coating by usual photolithography, mask setting, exposure, development, and cleaning. For example, as an etching method, there is a wet method or a dry method, but in accordance with the material of the lower electrode layer to be etched, if an optimum method and conditions are selected in terms of an etching sectional shape, an etching rate, in-plane uniformity, and the like. Good. From the viewpoint of controllability of etching when a plurality of layers are stacked, the dry method is superior. For example, a parallel plate reactive ion etching (RIE) method, an inductive coupling (ICP) method, an electron cyclotron resonance (ECR) method, a helicon wave excitation method, a magnetron method, a plasma etching method, an ion beam etching method, and the like can be used. . As the plasma etching method, high-density plasma such as ICP (Inductive Coupled Plasma) may be used. In order to control the etching, the conditions such as the type of the etching gas, the flow rate of the gas, the pressure of the gas, and the bias voltage are changed. At this time, if the etching amount is adjusted so that the barrier layer 102 is over-etched, patterning of the lower electrode can be surely performed even if there is a difference in the etching rate or a variation in the thickness of the barrier layer 102 and the lower electrode layer 103. I can do it. For example, the amount of over-etching is set to be 1000 to 2000 degrees in terms of the thickness of the barrier layer. This is because overetching to this extent can eliminate variations in thickness.
[0044]
After the formation of the lower electrode group 12, the ferroelectric layer 103 and the upper electrode layer 104 are formed and then patterned to form the upper electrode group 11 (ST4). As a forming method thereof, a known thin film forming method suitable for forming a dense crystalline thin film, for example, a solution coating method (including a sol-gel method and a MOD (Metal Organic Decomposition) method), a sputtering method, or a CVD method. A method (including a MOCVD (Metal Organic Chemical Vapor Deposition) method) is applicable. Here, a ferroelectric material is formed to a predetermined thickness, here, about 2000 °, using a sol-gel method.
[0045]
First, a metal alkoxide solution containing each element constituting PZT is applied to the lower electrode 103 or the substrate surface where the barrier layer 102 is exposed by etching to a certain thickness. After the application, the solvent is dried at a constant temperature for a certain time to evaporate the solvent, and then degreased at a predetermined high temperature for a certain time in an air atmosphere. By degreasing, the organic ligand coordinated to the metal is thermally decomposed, and the metal is oxidized to a metal oxide. The steps of coating, drying, and degreasing are repeated a predetermined number of times as necessary to form a ferroelectric layer. By drying and degreasing, the metal alkoxide in the solution is hydrolyzed or polycondensed to form a metal-oxygen-metal network. Thereafter, in order to promote crystallization of the ferroelectric layer, a high-speed heat treatment may be performed.
[0046]
By the above processing, the ferroelectric layer 104 is formed to a thickness of 2000 °. In the above process, the ferroelectric layer 104 is crystallized while inheriting the crystal state of the underlying layer in the crystal growth process after the formation of the thin film, so that at least a region intersecting with the lower electrode layer 103 In addition, a crystal having a uniform orientation that inherits the crystal state of the titanium oxide layer 103c in which crystals are densely formed is sandwiched. Next, in order to form the upper electrode layer 105, for example, platinum is formed to a thickness of, for example, 2000 ° by a sputtering method.
[0047]
Next, a resist pattern is formed by a photolithography method in the same procedure as the formation of the lower electrode group 12, followed by etching to form a pattern of the upper electrode wiring 11-m which crosses each of the lower electrode wirings 12-n and is parallel to each other. Molding. The thickness of the ferroelectric layer 103c remaining by the under-etching is, for example, about 10% of the thickness of the ferroelectric layer in a region below the upper electrode layer 105. Specifically, the thickness may be about 200 mm or less.
[0048]
Thereafter, as shown in FIG. 5, a first protective layer 109 for protecting the memory cell 10 is formed with a silicon oxide film or the like. Then, a contact hole for connecting the transistors of the peripheral circuits 2 and 3 is formed, and then a metal layer is formed and patterned to form an electrode wiring 108. Finally, the second protective layer 110 is formed of a silicon nitride film or the like, and the formation of the layer structure of the ferroelectric memory 1 is completed.
[0049]
According to the first embodiment, the lower electrode layer 103 is first patterned and then the ferroelectric layer 104 is entirely formed, but the barrier layer 102 is formed between the lower electrode layer 103 and the insulating film 101. In this case, the insulating film and the ferroelectric layer can be prevented from directly contacting and reacting with each other. Therefore, there is no need to go through a complicated step of masking the upper electrode and then patterning the lower electrode, which is conventionally required, and the operation and effect can be simplified as compared with the related art.
[0050]
According to the first embodiment, in the step of forming the lower electrode group 12 (ST3), over-etching is performed up to the upper layer of the barrier layer 102, so that the etching rate varies and the thickness of the lower electrode layer varies. Even if the lower electrode layer is removed even to a portion exceeding the variation width, the lower electrode wiring can be reliably separated.
[0051]
According to the first embodiment, in the step of forming the upper electrode group 11 (ST4), under-etching is performed to such an extent that the lower layer of the ferroelectric layer 103c remains in a region other than the region where the lower electrode layer 103 remains. In addition, it is possible to prevent the lower electrode layer 103 and the like below from being etched by completely removing the ferroelectric layer 104. Further, since the barrier layer 102 prevents the insulating film from being exposed, there is no problem even if the ferroelectric remains.
[0052]
(2nd Embodiment)
The second embodiment of the present invention relates to an electronic apparatus including the ferroelectric memory or the ferroelectric device of the present invention, particularly to a personal computer.
[0053]
FIG. 7 is a perspective view illustrating a configuration of a personal computer 1000 according to the second embodiment. 7, the personal computer 1000 includes a display panel 1001 and a main body 1004 having a keyboard 1002. The ferroelectric device or the dielectric memory of the present invention is used as a memory element or the like of a CPU substrate incorporated in the main body 1004 of the computer display device 1000. Therefore, it is possible to provide a highly reliable storage unit that does not cause deterioration of the ferroelectric layer. Further, since the ferroelectric device is manufactured by a simplified process, the product cost can be kept low.
[0054]
The ferroelectric device and the method of manufacturing the ferroelectric device according to the present invention are not limited to the above example, and can be variously modified and applied without departing from the spirit of the present invention.
[0055]
For example, in the above embodiment, the write circuit and the read circuit are provided in the peripheral circuit so that the word lines and the bit lines cross each other. However, in a form in which a memory cell in which a transistor is provided in an intersection region between the word line and the bit line is provided. There may be.
[0056]
In the above-described embodiment, the configuration as a ferroelectric memory is disclosed. However, a ferroelectric device that does not have a peripheral circuit for reading or writing and that performs a predetermined operation by applying a signal from the outside may be used. Good.
[Brief description of the drawings]
FIG. 1 is a front perspective view of a ferroelectric memory according to a first embodiment.
FIG. 2 is a cross-sectional view as viewed from the AA cross section in FIG.
FIG. 3 is a cross-sectional view as viewed from a cut plane BB in FIG. 1;
FIG. 4 is a schematic plan view of the ferroelectric memory according to the first embodiment.
FIG. 5 is a cross-sectional view as viewed from a CC section plane in FIG. 4;
FIG. 6 is a sectional view of a manufacturing step (corresponding to the AA cross section in FIG. 1) for explaining the method of manufacturing the ferroelectric memory according to the first embodiment.
FIG. 7 is an exemplary perspective view illustrating an electronic device according to a second embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Ferroelectric memory, 10 ... Memory cell array, 11 ... Upper electrode group, 11-1 to 11-X ... Upper electrode wiring, 12 ... Lower electrode group, 12-1 to 12-Y ... Lower electrode wiring, 100 ... Substrate, 101: oxide film (insulating film), 102: TiOx film (barrier layer), 103: lower electrode, 103a: Ti layer, 103b: TiOx layer, 103c: Pt layer, 104: PZT layer (ferroelectric layer) , 105 ... upper electrode

Claims (14)

A method of manufacturing a ferroelectric device having a structure for applying an electric field to a ferroelectric layer formed of a ferroelectric,
Forming a barrier layer on the insulating film;
Forming a lower electrode layer on the barrier layer;
Forming a lower electrode group consisting of a plurality of lower electrode wirings by etching the lower electrode layer;
Forming a ferroelectric layer on the lower electrode group;
Forming an upper electrode layer on the ferroelectric layer,
Etching the upper electrode layer and the ferroelectric layer to intersect the lower electrode group via the ferroelectric layer to form an upper electrode group including a plurality of upper electrode wirings. A method for manufacturing a ferroelectric device, comprising: 2. The method of manufacturing a ferroelectric device according to claim 1, wherein in the step of forming the lower electrode group, over-etching is performed to an upper layer of the barrier layer. 3. The ferroelectric device according to claim 1, wherein in the step of forming the upper electrode group, etching is performed to such an extent that a lower layer of the ferroelectric layer remains in a region other than a region where the lower electrode layer remains. 4. Manufacturing method. The method for manufacturing a ferroelectric device according to claim 1, wherein in the step of forming the barrier layer, a metal oxide is deposited to form the barrier layer. A ferroelectric device having a structure for applying an electric field to a ferroelectric layer formed of a ferroelectric,
An insulating film,
A lower electrode group including a plurality of lower electrode wirings formed on the insulating film;
An upper electrode group consisting of a plurality of upper electrode wires crossing the lower electrode group,
A ferroelectric layer formed at least in an intersection region between the lower electrode wiring and the upper electrode wiring,
A ferroelectric device, wherein a barrier layer is provided between the insulating film and the ferroelectric layer. 6. The ferroelectric device according to claim 5, wherein said ferroelectric layer is also formed in a region other than a lower layer of said upper electrode wiring. 7. The method according to claim 5, wherein the ferroelectric layer formed in a region other than the lower layer of the upper electrode wiring is formed thinner than a ferroelectric layer formed in a lower layer of the upper electrode wiring. The ferroelectric device as described. The ferroelectric layer formed below the intersection region of the upper electrode wiring and the lower electrode wiring is a region other than the lower layer of the intersection region and the ferroelectric layer formed below the upper electrode wiring. The ferroelectric device according to any one of claims 5 to 7, wherein the ferroelectric device is formed to have substantially the same thickness as the dielectric layer. The ferroelectric device according to claim 5, wherein the lower electrode wiring is provided on a projecting structure of the barrier layer. The ferroelectric device according to claim 5, wherein the barrier layer is formed of a metal oxide. The ferroelectric device according to any one of claims 5 to 10, further comprising a peripheral circuit that supplies a word selection signal and a bit selection signal to each of the lower electrode group and the upper electrode group. Dielectric memory. An electronic apparatus comprising a ferroelectric device manufactured by the method of manufacturing a ferroelectric device according to claim 1. An electronic apparatus comprising the ferroelectric device according to claim 5. An electronic device comprising the ferroelectric memory according to claim 11.

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