JP2004094269A - Ac plasma display and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extend a writing voltage operation margin for securing a successful display state by improving a writing failure to be caused by excessive quantity of active particles in address period in an AC plasma display. <P>SOLUTION: In the AC plasma display constituted by dividing one field of time for constituting one screen into sub-fields and dividing each sub-field at least into priming period and address period, etc, period for setting potential of a scanning electrode Sn in the priming period higher than that of the scanning electrode Sn in the address period is set before transition from the priming period to the address period of one field. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a method for driving an AC plasma display panel, and more particularly, to a method for driving an AC plasma display when a sustain voltage is supplied and a transition is made to a new discharge voltage, and an AC plasma using the driving method. Display related.

In general, a plasma display panel has a thin structure, has no flicker, has a large display contrast ratio, can have a relatively large screen, has a fast response speed, is self-luminous, and uses a phosphor. It has many features, such as the ability to emit multicolor light. For this reason, in recent years, it has been widely used as a so-called wall TV such as a thin large-screen display device in a computer-related display device field and a color image display field.

Depending on the operation method, the plasma display has an AC type in which the electrodes are coated with a dielectric and indirectly operates in an AC discharge state, and an AC type in which the electrodes are exposed to a discharge space and are in a DC discharge state. There is a DC type that operates.

Furthermore, the AC type includes a memory operation type using a memory of a discharge cell as a driving method and a refresh operation type not using the memory. The brightness of the plasma display is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage. The above refresh type is mainly used for a plasma display having a small display capacity because the brightness decreases as the display capacity increases.

FIG. 14 is a cross-sectional view illustrating one display cell configuration of an AC plasma display. This display cell comprises two insulating substrates 1 and 2 made of glass, a back surface and a front surface, a transparent scanning electrode 3 and a transparent common electrode 4 formed on the insulating substrate 2, and a scanning device for reducing the electrode resistance. Trace electrodes 5 and 6 arranged so as to overlap with the electrode 3 and the common electrode 4; and a data electrode 7 formed on the insulating substrate 1 of the rear glass substrate so as to be orthogonal to the scan electrode 3 and the common electrode 4. A discharge gas space 8 in which the space between the substrates 1 and 2 is filled with a discharge gas composed of helium, neon, xenon, or the like, or a mixed gas thereof; a partition wall for securing the discharge gas space 8 and separating display cells; 9, a phosphor 21 for converting ultraviolet light generated by the discharge of the discharge gas into visible light 25, a dielectric film 22 covering the scan electrode 3 and the common electrode 4, and protecting the dielectric film 22 from discharge. A protective layer 24 made of magnesium oxide that constituted by a dielectric layer 23 covering the data electrodes 7.

FIG. 15 schematically shows the electrode arrangement of an AC type plasma display panel which is also applied to the present invention and driven. The intersections of the scanning electrodes S1 to Sn and the common electrodes C1 to Cn provided in parallel and the data electrodes D1 to Dm provided in a direction perpendicular to the scanning electrodes S1 to Sn constitute light emitting cells. One scan electrode S, one common electrode C, and one data electrode D constitute one cell. Therefore, the number of cells in one entire screen is n × m, ie, n scanning electrodes and common electrodes × m data electrodes.

書 き 込 み A write selection driving operation of the plasma display in such a configuration will be described with reference to FIG. Each SF includes four periods of a priming period → an address period → a sustain period → a charge erasing period.

First, in the first priming period, a discharge is generated by the priming pulse Ppr-s applied to the scan electrode and the priming pulse Ppr-c applied to the common electrode side. This discharge generates a priming discharge in a discharge space in the vicinity of the gap between the scanning electrode and the common electrode, thereby generating active particles that facilitate the generation of cell discharge. Positive wall charges adhere to the top. Subsequently, a charge adjustment pulse Ppe-s is applied to generate a weak discharge, thereby reducing negative wall charges on the scan electrode and positive wall charges on the common electrode.

The address period is a period for selecting a discharge cell to emit light, and write discharge is performed only in a cell selected by the negative scan pulse Pw-s applied to the scan electrode and the positive data pulse Pd applied to the data electrode. The wall charges are generated and deposited on the electrodes of the cells where the light is to be emitted in the subsequent sustain period. The write discharge occurs only at the intersection of the scan electrode to which the scan pulse Pw-s is applied and the data electrode to which the data pulse Pd is applied. When a discharge occurs, wall charges adhere to the discharge cells. On the other hand, in a discharge cell in which no discharge occurs, the wall charge after charge erasure is small.

The sustain period is a period for display light emission. The sustain period is started from the common electrode side, and thereafter, negative sustain pulses Psus-s and Psus-c alternately applied to the scan electrode side and the common electrode side are applied to the scan electrode. Applied to the common electrode. At this time, since the amount of wall charges of the discharge cells in which writing has not been performed in the address period is very small, no sustain discharge occurs even if a sustain pulse is applied. On the other hand, in a discharge cell in which a write discharge has occurred in the address period, a positive charge is attached to the scan electrode and a negative charge is attached to the common electrode, and a negative sustain pulse voltage and a wall charge voltage are superimposed on the common electrode, Exceeding the discharge starting voltage, discharge occurs. When the discharge occurs, the wall charges are arranged so as to cancel the voltage applied to each electrode. Therefore, negative charges adhere to the common electrode and positive charges adhere to the scan electrode.

(4) Since the next sustain pulse is a pulse of a positive voltage on the scan electrode side, the effective voltage applied to the discharge space exceeds the discharge start voltage due to the superposition with the wall charges, and a discharge occurs. Thereafter, the same is repeated to maintain the discharge. The luminance is determined by the number of times of this discharge.

In the charge erasing period, a negative sustaining erasing pulse Pse-s is applied to the scanning electrode Si to erase the wall charges existing when light was emitted in the sustaining period, thereby making the state of all the discharge cells in the panel uniform. I do.

As described above, by repeating each of the four periods of the priming period, the address period, the sustaining period, and the charge erasing period for each SF in response to the video signal, the display of high-density pixels on a large screen is maintained. I have.

FIG. 17 shows a configuration block diagram of a driving circuit of the plasma display panel for operating this sequence. At the horizontal end of the plasma display panel, there are scanning electrode and sustaining electrode extraction portions, and a drive circuit is connected to the connection portion. The drive circuit on the scan electrode side includes a scan pulse driver 66 for outputting a scan pulse for each scan electrode, a priming driver 65 for outputting a priming pulse, a sustain driver 62 for outputting a sustain pulse, and an erase pulse. The scan electrode driver 60 includes an erase driver 63 for applying, a scan base driver 61 for outputting a scan base pulse, and a scan voltage driver 64 for outputting a scan voltage.

On the other hand, the common electrode driver 40 of the drive circuit on the common electrode side includes a sustain driver 41 for applying a sustain pulse to the entire common electrode. At the end of the plasma display panel 70 in the vertical direction, there is a data electrode take-out portion, and the data driver 50 is connected to this connection portion. Although each driver is shown as a switch in this drawing, it may be constituted by a switching element typified by a transistor or an FET instead of a physical switch.

The gradation expression is performed by dividing one frame into a plurality of subfields, changing the number of sustain pulses for each SF, and combining the SFs. Therefore, if the ratio of the number of sustain pulses in each SF is, for example, 1: 2: 4: 8: 16: 32: 64: 128, 256 (= 2 ⁸ ) gray scales are expressed.

(4) The power consumption is extremely increased when the image display area is large and the average luminance level is high. Therefore, a control method for suppressing an increase in power consumption has been used. This control method is called “Peak Luminance Enhancement” (PLE). The input video signal is converted into a signal for a plasma display by a video signal processing circuit and an SF control circuit. The converted signal is input to an input signal average brightness level calculation circuit, and calculates the brightness level of the entire screen. On the basis of the calculation result, the sustain pulse number control circuit increases the number of sustain pulses to increase the luminance when the average luminance level of the input signal is low (APL (Average Peak Brightness Level): small), that is, when the display area is small. On the other hand, when the average luminance level is high (APL: large), that is, when the display area is large, the number of sustain pulses is reduced to limit the luminance, thereby suppressing power consumption when the display area is large. The number of sustain pulses of each SF is controlled for each frame so that a high peak luminance can be obtained.

In such a method of driving a plasma display, as shown in FIG. 18, the sustaining period is assigned a length long enough to include all the sustaining pulses when the APL is at the minimum. That is, when the APL having a large number of sustain pulses is low, the remaining time Ts-e of the sustain period during the sustain period is supplied as the scan-side electrode waveform and the common-side electrode waveform even during the short period, and the sustain pulse number is reduced. When the small APL is high, it is supplied as a scanning-side electrode waveform and a common-side electrode waveform for a long period. During the charge erasing period, an erasing pulse is supplied to the negative side irrespective of the level of APL. Has been supplied.

Therefore, as shown in FIG. 19, when the APL is high, that is, when the number of sustain pulses is small, a blank time occurs at the end of the period given in the sustain period, and the time from the last sustain pulse to the next charge erase pulse is increased. growing. As a result, the time until charge erasure changes depending on the level of the APL, and it has been difficult to achieve uniform charge erasure.

A main object of the present invention is to provide a driving method and a driving circuit that maintain good driving characteristics by uniform charge erasure in an AC plasma display.

In order to achieve the above object, the present invention provides a front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other, and a plurality of data electrodes arranged to be orthogonal to the plurality of scan electrodes and the common electrode. And a cell arranged at the intersection of the scan electrode and the common electrode with the data electrode, and one frame constituting one screen is divided into subfields (hereinafter, referred to as SF). In an AC plasma display divided into at least a priming period and an address period, each SF changes the scan electrode potential in the priming period before the transition from the priming period to the address period in one field. It is characterized by having a higher setting period.

The present invention also provides a front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other, and a back substrate having a plurality of data electrodes arranged so as to be orthogonal to the plurality of scan electrodes and the common electrode. , An AC-type plasma display panel including a cell disposed at an intersection of the scan electrode and the common electrode with the data electrode, wherein one frame, which is a time for forming one screen, is a subfield (hereinafter, referred to as SF). And a priming period for supplying a priming pulse to the scan electrode and the common electrode in each SF in order to generate a write discharge in an arbitrary cell; and applying a scan pulse line-sequentially to at least the scan electrode in each SF. While applying a data pulse in synchronization with the scan pulse to the selected data electrode, a write discharge occurs in the selected cell, and the wall charge is reduced. In an AC plasma display that is sequentially driven during an address period to be formed, a period in which the scan electrode potential in the priming period is set higher than the scan electrode potential in the address period before shifting from the priming period of one field to the address period. It is characterized by having.

The present invention also provides a front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other, and a back substrate having a plurality of data electrodes arranged so as to be orthogonal to the plurality of scan electrodes and the common electrode. , A cell arranged at the intersection of the scan electrode and the common electrode and the data electrode, and one frame, which is a time forming one screen, is divided into subfields (hereinafter, referred to as SFs). In the driving method of an AC plasma display, which is divided into at least a priming period and an address period, and is sequentially driven during the priming period and the address period, scanning in the priming period is performed before shifting from the priming period of one field to the address period. A period for setting the electrode potential higher than the scanning electrode potential in the address period is provided. It is characterized in.

The present invention also provides a front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other, and a back substrate having a plurality of data electrodes arranged so as to be orthogonal to the plurality of scan electrodes and the common electrode. , A cell arranged at the intersection of the scanning electrode and the common electrode, wherein one frame, which is a time for forming one screen, is divided into subfields (hereinafter, referred to as SF). A priming period for supplying a priming pulse to the scan electrode and the common electrode in each SF in order to generate a write discharge in an arbitrary cell, and selecting at least a line-sequential application of the scan pulse to the scan electrode An address for applying a data pulse synchronized with the scan pulse to the data electrode to cause a write discharge to a selected cell to form a wall charge. In the driving method of the AC type plasma display that is sequentially driven between the priming period and the address period of one field, a period in which the scan electrode potential in the priming period is set higher than the scan electrode potential in the address period is provided. It is characterized by being provided.

According to the present invention, in the plasma display panel driving apparatus or method, when the input average luminance level (APL) of the video signal is high, that is, when the number of sustain pulses is small, a blank is provided at the end of the period given to the sustain period. Time occurs, and the time from the last sustain pulse to the next charge erase pulse increases. This makes it possible to appropriately prevent erroneous discharge from occurring due to the level of the APL until the charge is erased, and to maintain good drive characteristics by uniform charge erasure.

Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

[First Embodiment]
(1) Configuration Description In the first embodiment of the present invention, the interval Tse from the end of the last sustain pulse Psus-cl in the sustain period to the application of the charge erase pulse Pse-s in the charge erase period is 0 μs to 200 μs. Preferably, the delay time of the charge erase driver for driving the charge erase pulse is set to 100 μs.

The configuration of the drive circuit of the AC type plasma display according to the first embodiment of the present invention is the same as the configuration described with reference to FIG. It is very different.

According to FIG. 17, the scanning electrode and the sustain electrode take-out portion are provided at the horizontal end of the plasma display panel, and the driving circuit is connected to the connection portion. The drive circuit on the scan electrode side includes a scan pulse driver 66 for outputting a scan pulse for each scan electrode, a priming driver 65 for outputting a priming pulse, a sustain driver 62 for outputting a sustain pulse, and an erase pulse. The scan electrode driver 60 includes an erase driver 63 for applying, a scan base driver 61 for outputting a scan base pulse, and a scan voltage driver 64 for outputting a scan voltage.

On the other hand, the common electrode driver 40 of the drive circuit on the common electrode side includes a sustain driver 41 for applying a sustain pulse to the entire common electrode. At the end of the plasma display panel 70 in the vertical direction, there is a data electrode take-out portion, and the data driver 50 is connected to this connection portion. Although each driver is shown as a switch in this drawing, it may be constituted by an element typified by a transistor or an FET instead of a physical switch.

The gradation expression is performed by dividing one frame into a plurality of subfields, changing the number of sustain pulses for each SF, and combining the SFs. Therefore, if the ratio of the number of sustain pulses in each SF is, for example, 1: 2: 4: 8: 16: 32: 64: 128, 256 (= 2 ⁸ ) gray scales are expressed.

(4) The power consumption of the driving circuit of the plasma display panel increases significantly when the image display area is large and the average luminance level is high. Therefore, a control method for suppressing an increase in power consumption has been used. This control method is called a lightness peak enhancement method or “Peak Luminance Enhancement” (PLE). The input video signal is converted into a signal for a plasma display by a video signal processing circuit and an SF control circuit. The converted signal is input to an input signal average brightness level calculation circuit, and calculates the brightness level of the entire screen. On the basis of the calculation result, the sustain pulse number control circuit increases the number of sustain pulses to increase the luminance when the average luminance level of the input signal is low (APL (Average Peak Brightness Level): small), that is, when the display area is small. On the other hand, when the average luminance level is high (APL: large), that is, when the display area is large, the number of sustain pulses is reduced to limit the luminance, thereby suppressing power consumption when the display area is large. The number of sustain pulses of each SF is controlled for each frame so that a high peak luminance can be obtained.

(2) Description of Operation FIG. 1 is an example of a driving waveform for implementing the present invention. In FIG. 1, a voltage of GND-Vs-Vp is applied to the rightmost side of the scanning-side electrode waveform, and a voltage of GND-Vs is applied to the common-side electrode waveform. Each SF is composed of a priming period → an address period → a sustain period → a charge erasing period. In the priming period, a positive pulse Ppr-s is applied to the scan electrode and a negative pulse Ppr-c is applied to the common electrode at the same time. Then, a negative Ppe-s is applied to the scanning electrode. In the next address period, a negative polarity pulse Pbw is constantly applied, and further, a negative polarity scan pulse Pw-s, which is applied with a time lag for each scan electrode, is applied, and the scan electrodes in the drawing emit light. In this case, a positive data pulse Pd synchronized with the scan pulse is applied to the data electrode. In the sustain period, a negative sustain pulse Psus-c is alternately applied to the common electrode and a negative sustain pulse Psus-s is applied to the scan electrode. After the last sustain pulse is applied, the sustain period ends, and then, during the charge erase period, a negative sustain erase pulse Pse-s is applied to the scan electrode.

(2) In FIG. 2, the supply voltage to the scanning electrode and the common electrode is shown in chronological order by a dark line, and the movement of the electric charges in the case of the above driving is schematically shown. As shown in FIG. 2A, in the discharge in the priming period, a positive voltage is applied to the scan electrode Sn, a negative charge is applied to the scan electrode Sn, and a negative voltage is applied to the common electrode Cn, and a positive charge is applied to the common electrode Cn. Is accumulated. In the charge adjustment period of FIG. 2B, a negative voltage is applied to the scan electrode Sn and a positive voltage is applied to the common electrode, and the accumulated charge decreases. In the address period of FIG. The discharged cell generates a discharge between the data electrode D and the scan electrode Sn, and further generates a discharge between the surface electrodes between the common electrode Cn and the scan electrode Sn. Negative charge is accumulated. In the first sustain pulse of FIG. 2D, the polarity of the charge accumulated in the address period due to the discharge between the surface electrodes is inverted, and thereafter, the charge on the electrode is inverted for each sustain pulse. After the application of the final sustain pulse, as shown in FIG. 2E, negative charges are accumulated on the scan electrode Sn and positive charges are accumulated on the common electrode Cn side. By discharging in the charge erasing period in FIG. 2F, the accumulated charges are released, and the SF returns to the state before the priming at the head.

As shown in FIG. 2E, in the cell selected in the address period, wall charges adhere to the electrodes due to the discharge in the sustain period. However, immediately after the discharge by the final sustain pulse, the discharge is likely to occur. On the other hand, even if the wall charges are attached similarly, the generation of discharge is delayed after the blank time. This is because the number of excited molecules and atoms existing in the discharge space is large immediately after the discharge, but the number of molecules and atoms in the excited state decreases after the blank time. Therefore, it is effective to perform the charge erasing by reducing the interval between the final sustain pulse and the charge erasing pulse.

(3) Effects of the Present Embodiment FIG. 3 shows a relationship between the time interval Tse from the end of the last sustain pulse Psus-cl to the application of the charge erase pulse Pes-s and the sustain voltage Vs. When the time interval Ts-e is in the range of 0 to 150 μs, the maximum sustain voltage is defined only by erroneous lamps caused by non-selected cells being discharged due to a large potential difference between the surface electrodes in the address period and also being discharged during the sustain period. It is. However, if the time interval Tse exceeds 150 μs, molecules and atoms activated by the discharge during the sustain period gradually decrease, so that at the sustain voltage lower than the erroneous light that starts during the address period, the intrinsic voltage is lower. A strong discharge is generated by a charge erasing pulse that should generate a weak discharge, and a strong discharge also occurs in the next priming and charge adjustment pulse of SF, and an erroneous lamp occurs due to sustain discharge.

(4) FIG. 4 shows a state diagram for each minute voltage drop during the charge erasing period. Time T1 is the end of the sustain period and the start of the charge erasing period, and FIG. 4D shows the state diagram. When the number of activated molecules and atoms is large, as shown on the left side of FIGS. 4D to 4G, discharge starts at time T2, and a weak discharge is caused to reduce the charge amount. However, when the number of activated molecules and atoms decreases, the start of discharge is delayed, and as shown on the right side of FIGS. 4D to 4G, when a discharge is caused at time T3, the potential difference between the applied surface electrodes is reduced. In order to increase the voltage, a strong discharge is performed, and the charge is stored again in a state where the polarity of the stored charge is reversed. The voltage at which an erroneous lamp starting during the charge erasing period occurs decreases as the time interval Ts-e increases. On the other hand, when a voltage equal to or lower than the minimum sustain voltage is applied, even if a discharge is generated in the selected cell during the address period, the amount of electric charge adhering to the surface electrode is small because the potential difference between the surface electrodes during the address period is insufficient. Therefore, in the sustain period, the amount of charge for generating discharge is insufficient, and the sustain discharge may fail even in the selected cell. Therefore, the Vs margin is not less than the minimum sustain voltage and not more than the maximum sustain voltage. The minimum sustain voltage does not depend on Tse, but the maximum sustain voltage decreases as Tse increases. Therefore, by limiting Ts-e to 0 μs to 200 μs, preferably to a transmission delay time of the charge erase driver 63 itself for driving the charge erase pulse to 100 μs, stable erasing can be performed, and the Vs margin can be improved. Can be secured.

[Second embodiment]
The second embodiment according to the present invention combines the first embodiment with a power control method called “Peak Luminance Enhancement” (PLE). The PLE controls the number of sustain pulses of each SF per frame in order to reduce power consumption while increasing peak luminance.

FIG. 5 is a block diagram illustrating the configuration of the plasma display panel driving device according to the present embodiment. The average luminance level (APL) of the input signal is calculated. When the APL is high, the sustain pulse number control circuit outputs a small number of all sustain pulses per frame, and when the APL is low, outputs a large number of all sustain pulses. The length of the sustain period in one subfield (SF) changes depending on the APL. However, even when the APL is high and the number of sustain pulses is reduced as shown in FIG. 6, the charge erasing pulse sets the interval between the sustain period to 0 μs to 200 μs. The characteristic of the second embodiment is that the delay time of the charge erasing driver itself for driving the charge erasing pulse is set to preferably 100 μs during the period. As a result, even when the APL changes, stable charge erasure can always be realized.

[Third Embodiment]
According to the third embodiment of the present invention, as shown in FIG. 7, the priming pulse is a sawtooth wave or a blunt waveform in the second embodiment, and the charge erasing is completely completed by both the charge erasing pulse and the priming pulse. In this case, the time interval Te-p between the charge erasing pulse and the priming pulse is also set between 0 and 200 μs. The priming pulse having such a form also has a function of erasing charges that could not be completely erased by the charge erasing pulse when the previous SF emitted light. As with the first embodiment, the erasing characteristic by the priming pulse can be better obtained by discharging while the space charge exists. FIG. 8 shows the relationship between the interval Te-p between the charge erase pulse and the priming pulse and the priming voltage Vp.

Here, the minimum priming voltage is the minimum Vp voltage value at which priming discharge occurs in all cells, and the maximum priming voltage is that if a Vp voltage higher than that is applied, the amount of charge accumulated during weak discharge in priming increases. , Ppr-s, the upper limit voltage at which erroneous lighting occurs due to the occurrence of a strong discharge (self-erasing discharge) because the potential difference between the surface electrodes due to the accumulated charges is equal to or greater than the dischargeable potential difference. The maximum erroneous lamp voltage means that weak discharge in priming becomes insufficient, the amount of accumulated wall charge becomes insufficient, the potential difference between the surface electrodes at the start of discharge in the next charge adjustment pulse increases, and strong discharge occurs. This is the maximum voltage that will occur and lead to false lights. Therefore, the margin of Vp is the shaded portion in FIG. By reducing Te-p, a wide margin can be secured.

[Fourth embodiment]
According to the fourth embodiment of the present invention, in the third embodiment, as shown in FIG. 9, when the charge adjustment pulse adjusts the charge by weak discharge with a sawtooth wave or a blunt waveform, the charge is adjusted from the priming pulse to the charge adjustment pulse. The time interval Tp-pe until the adjustment pulse is set to 0 to 50 μs, preferably, to the delay time of the priming driver 65 itself to 20 μs.

In such a form of charge adjustment pulse, after the charge is completely erased by the priming pulse, a charge arrangement suitable for the address is created in a state where activated molecules and atoms remain, thereby reducing the variation in charge arrangement. Can be reduced. FIG. 10 shows the relationship between the time Tp-pe from the end of priming to the charge adjustment pulse and the sustain voltage Vs. When Tp-pe is in the vicinity of 0 to 50 μs, when a voltage higher than the maximum sustain voltage is applied, the potential difference between the surface electrodes in the address period is large. Occurs.

However, when the time interval Tp-pe exceeds 50 μs, molecules and atoms activated in the cell during the priming period decrease, so that the potential difference between the surface electrodes at the start of discharge in the charge adjustment pulse increases, and At a voltage lower than the erroneous lamp that starts during the period, a strong discharge is generated by the charge adjustment pulse, and the sustain period is also discharged, which leads to an erroneous lamp. On the other hand, when the voltage is equal to or lower than the minimum sustain voltage, even if a discharge occurs in the selected cell during the address period, the amount of electric charge adhering to the surface electrode is small because the potential difference between the surface electrodes is insufficient.

Therefore, in the sustain period, the amount of charge for generating the discharge is insufficient, and the sustain discharge may fail even in the selected cell. Since the amount of stored charge is small, the voltage for maintaining the voltage is insufficient. Therefore, the margin of the sustain voltage Vs is not less than the minimum sustain voltage and not more than the maximum sustain voltage. The minimum sustain voltage does not depend on Tp-pe, but the maximum sustain voltage decreases as Tp-pe increases. Therefore, a wide Vs margin can be secured by limiting Tp-pe to 0 to 50 μs.

[Fifth Embodiment]
According to a fifth embodiment of the present invention, in the fourth embodiment, the time interval from the charge adjustment pulse to the address period is set to 0 to 50 μs, preferably, the transmission delay time of the scanning voltage driver 64 itself to 20 μs. It is characterized by being between.

With the charge adjustment pulse of the present embodiment, addressing is performed with the molecules and atoms in the cell activated by the discharge of the charge adjustment pulse in a state where the variation of the charge arrangement is reduced as described above. The discharge at the address is stably obtained.

[Sixth Embodiment]
The sixth embodiment according to the present invention is characterized in that, in the fifth embodiment, as shown in FIG. 11, the interval of the entire SF in the field is reduced. This is because, by limiting the intervals between the sustain period, the charge erase period, the next SF priming period, the charge adjustment period, the address period, and the sustain period as in the first to fifth embodiments, stable charge erase and stable charge erase can be performed. Enables stable address discharge. At this time, the above-mentioned PLE control method or lightness peak enhancement method can be used.

In the present embodiment, the sub-field period can be shortened by reducing the blank period due to the difference in the sustain period in the conventional example shown in FIG.

In particular, when the input average luminance level (APL) of the video signal is high, that is, when the number of sustaining pulses is small, a blank time occurs at the end of the period given in the sustaining period, and from the last sustaining pulse to the next charge erasing pulse. Time becomes bigger. This makes it possible to appropriately prevent the occurrence of erroneous discharge during the time until charge erasure due to the level of APL, and to maintain good drive characteristics by uniform charge erasure. Further, the period of the subfield can be shortened without providing this blank time.

On the other hand, during this blank period, as shown in FIG. 12 described later, a charge adjusting pulse and a charge erasing pulse are provided on the common electrode after the priming pulse to prevent erroneous discharge.

[Seventh embodiment]
As a seventh embodiment according to the present invention, in the sixth embodiment, a charge erase pulse, a priming pulse, and a charge adjustment pulse are applied after the last sustain pulse of the last SF in the field as shown in FIG. And a charge erasing pulse, a priming pulse, and a charge adjustment pulse are also applied immediately before the address period of the head SF of the next field.

FIG. 13 shows a state diagram of each APL level in the latter half of the # 1 field. When the APL is high, a blank time is formed at the end of the field, and a charge erase pulse, a priming pulse, and a charge adjustment pulse are applied thereto. The first half of the charge erasing pulse, the priming pulse, and the charge adjusting pulse completely erase the charge in the light emitting cell, and realize a charge arrangement in which discharge is more likely to occur. Further, by discharging with the latter half charge erase pulse, priming pulse, and charge adjustment pulse, molecules and atoms can be activated again and the charge arrangement can be re-arranged, so that a stable address discharge can be achieved even in the first SF of the field. Obtainable.

Since the driving method of the AC plasma display panel in each of the above embodiments can be used in the AC plasma display panel itself, the same driving method is used for the AC plasma display panel according to the present invention. Can be.

FIG. 3 is a drive waveform diagram according to the first embodiment of the present invention. FIG. 4 is a state diagram corresponding to a drive waveform according to the first embodiment of the present invention. FIG. 5 is a performance region diagram based on a drive waveform according to the first embodiment of the present invention. FIG. 3 is a drive waveform diagram according to the first embodiment of the present invention. FIG. 6 is a configuration block diagram according to a second embodiment of the present invention. FIG. 9 is a drive waveform diagram according to a second embodiment of the present invention. FIG. 11 is a drive waveform diagram according to a third embodiment of the present invention. FIG. 13 is a performance region diagram based on drive waveforms according to the third embodiment of the present invention. It is a drive waveform diagram by a 4th embodiment of the present invention. It is a drive waveform diagram by a 4th embodiment of the present invention. FIG. 14 is a time-series diagram of a drive according to a sixth embodiment of the present invention. It is a drive waveform diagram by a 7th embodiment of the present invention. FIG. 14 is a time-series diagram of a drive according to a sixth embodiment of the present invention. FIG. 2 is a configuration diagram of a conventional plasma display pixel. It is a wiring diagram of the plasma display panel of a prior art. It is a drive waveform diagram to the plasma display of a prior art. FIG. 2 is a driving configuration diagram of a plasma display according to the related art and the present invention. FIG. 7 is a drive waveform diagram by a conventional plasma display. FIG. 5 is a time-series diagram of a drive by a plasma display according to the related art.

Explanation of reference numerals

REFERENCE SIGNS LIST 1 back glass substrate 2 front glass substrate 3 scanning electrode 4 common electrode 5 trace electrode 6 trace electrode 7 data electrode 8 discharge glass space 9 partition 11 video signal 12 video signal processing circuit 13 subfield control circuit 14 input signal average luminance level calculation circuit Reference Signs List 15 sustain pulse number control circuit 20 image processing unit 21 phosphor 22 dielectric 23 dielectric 25 visible light 30 drive controller 40 common electrode driver 50 data electrode driver 60 scan electrode driver 61 scan base driver 62 sustain driver 63 charge erase driver 64 scanning Voltage driver 65 Priming driver 66 Scan pulse driver 70 Plasma display panel

Claims (4)

A front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other; a back substrate having a plurality of data electrodes arranged orthogonal to the plurality of scan electrodes and the common electrode; One frame, which is a time constituting one screen, is divided into subfields (hereinafter, referred to as SFs), and each SF includes at least a priming period and an address period. In the AC plasma display divided into a plurality of fields, before the transition from the priming period of one field to the address period, there is a period in which the scan electrode potential in the priming period is set higher than the scan electrode potential in the address period. AC plasma display. A front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other; a back substrate having a plurality of data electrodes arranged orthogonal to the plurality of scan electrodes and the common electrode; An AC plasma display panel including an electrode and a cell disposed at an intersection of the data electrode, wherein one frame, which is a time forming one screen, is divided into subfields (hereinafter, referred to as SF), A priming period for supplying a priming pulse to the scan electrode and the common electrode in each SF in order to generate a write discharge in the cell, and at least the data to be selected while applying a scan pulse line-sequentially to the scan electrode. An address period in which a data pulse synchronized with the scan pulse is applied to an electrode to cause a write discharge in a selected cell to form a wall charge. In the AC type plasma display which is sequentially driven by (1) and (2), before the transition from the priming period of one field to the address period, there is a period in which the scan electrode potential in the priming period is set higher than the scan electrode potential in the address period. AC type plasma display. A front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other; a back substrate having a plurality of data electrodes arranged orthogonal to the plurality of scan electrodes and the common electrode; One frame, which is a time constituting one screen, is divided into subfields (hereinafter, referred to as SFs), and each SF includes at least a priming period and an address period. In the driving method of the AC type plasma display, which is sequentially driven in the priming period and the address period, before shifting from the priming period of one field to the address period, the scan electrode potential in the priming period is changed in the address period. A period in which the potential is set higher than the scanning electrode potential is provided. The driving method of C-type plasma display. A front substrate having a plurality of scan electrodes and a common electrode arranged in parallel with each other; a back substrate having a plurality of data electrodes arranged orthogonal to the plurality of scan electrodes and the common electrode; An AC-type plasma display panel including a cell disposed at an intersection of electrodes, wherein one frame, which is a time for forming one screen, is divided into subfields (hereinafter, referred to as SF) and written into an arbitrary cell. A priming period in which a priming pulse is supplied to the scan electrode and the common electrode in each SF in order to generate a discharge, and the scan is performed on the data electrode selected while applying a scan pulse line-sequentially to at least the scan electrode. A write pulse is generated in a selected cell by applying a data pulse synchronized with the pulse, and the selected cell is sequentially driven in an address period in which wall charges are formed. In the driving method of the AC type plasma display, before the transition from the priming period of one field to the address period, a period for setting the scan electrode potential in the priming period higher than the scan electrode potential in the address period is provided. Characteristic driving method of an AC type plasma display.

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