JP2003271092A - Method for driving plasma display panel and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance display quality by reducing background light emission in a plasma display panel. <P>SOLUTION: In this method for driving the plasma display panel, the panel is driven in a manner such that voltage is applied to address electrodes for each color of emitted light on the basis of discharge start voltage between Y and A electrodes in accordance with the color of the emitted light in the period of writing to a counter electrode by at most (n-1) pieces of sub-frames obtained by dividing one frame into n pieces (n is a natural number equal to or larger than 2), and a potential difference between the Y and the A electrodes is controlled in accordance with the color of the emitted light of cells, so that the potential difference between the Y and the A electrodes becomes a proper potential difference in conformity with the discharge start voltage regardless of the color of the emitted light of cells, to thereby prevent the potential difference between the Y and the A electrodes from reaching the discharge start voltage in the cells whose lights are put out of an immediately preceding sub-frame. Thus, the background light emission in reset periods is reduced. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel and a plasma display device, and is particularly suitable for use in a method of driving an AC drive type plasma display panel.

[0002]

2. Description of the Related Art An AC-driven plasma display panel (Plasma Display P), which is one of the conventional flat panel display devices, has been used.
Anel: PDP) is a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes (first electrode and second electrode) and address discharge using the third electrode. There is a three-electrode type. In the three-electrode PDP, the first and second electrodes (sustain discharge electrodes) that perform sustain discharge are first
The surface discharge structure in which the third electrode (address electrode) is arranged on the second substrate facing the first substrate is adopted. In the surface discharge structure, cells that are unit light emitting elements are formed in regions where a pair of sustain discharge electrodes and address electrodes are orthogonal to each other.

FIG. 14 is a diagram showing an example of a cell structure of a three-electrode surface discharge PDP. As shown in FIG. 14, the sustain discharge electrodes X and Y are parallel to each other and one sustain discharge electrode X and one sustain discharge electrode Y are provided on the inner surface of the front glass substrate 11 (on the side of the rear glass substrate 16 described later). Are formed to approach each other. The sustain discharge electrodes X and Y are composed of a transparent conductive film 12 that forms a surface discharge gap and a metal film 13 that is overlapped on the edge thereof, and are covered with a dielectric layer 14 and a protective film 15.

On the other hand, the address electrode A is formed on the inner surface of the rear glass substrate 16 (on the front glass substrate 11 side) in a direction orthogonal to the sustain discharge electrodes X and Y. The address electrode A is covered with the dielectric layer 17. On the front glass substrate 11 side of the dielectric layer 17, the address electrode A
The barrier ribs 18 that partition the discharge space are provided for each column (provided that the direction in which the address electrodes A extend is a column).

On the surface of the dielectric layer 17 on the front glass substrate 11 side and the side surface of the partition wall 18, phosphors for emitting red, green and blue are arranged and applied in stripes for each color to form a phosphor layer. 19R, 19G, and 19B are formed. The phosphor layers 19R, 19G, and 19B are excited by the discharge between the sustain discharge electrodes X and Y to emit light. The letters "R", "G", and "B" in the figure indicate that the fluorescent colors of the phosphors are red, green, and blue, respectively.

The AC drive type (3-electrode surface discharge type) PDP having the cell structure shown in FIG. 14 is driven as shown in FIG. 15, for example. FIG. 15 shows an AC drive type PD.
FIG. 9 is a drive waveform diagram showing an example of a P driving method, showing one subframe of a plurality of subframes forming one frame. One subframe (subframe period TSF) includes a reset period TR and an address period T.
A and sustain period (sustaining discharge period) TS. In the following description, the last sustain period T
It is assumed that a negative charge remains on the X electrode XE and a positive charge remains on the Y electrode YE of the cell illuminated in S. Similarly, the X electrode X of the cell that is not illuminated
It is assumed that the positive charge remains on E and the negative charge remains on the Y electrode YE.

In the reset period TR, the address electrodes AR, AG and AB for selecting the cells that emit red, green and blue respectively are set to the ground level (0V). Further, the voltage −Vxp ′ is applied to all the X electrodes (sustain discharge electrodes X) XE, and the voltage gradually rises to all the Y electrodes (sustain discharge electrodes Y) YE, and finally the voltage V
A blunt wave reaching y'is applied. Note that the “blunt wave” is a ramp waveform in which the voltage continuously changes with the elapse of a sufficiently long period of time with respect to a waveform in which the voltage changes in a short time such as a sustain pulse described later.

By applying a voltage to each electrode in this way, in each cell, the voltage between the X electrode XE and the Y electrode YE (hereinafter,
It is called "between XY electrodes". ) And the potential difference between the Y electrode YE and the address electrodes AR, AG, and AB (hereinafter referred to as “between YA electrodes”) reach the discharge start voltage, and the discharge occurs between the XY electrodes and the YA electrodes. Is started. As a result, positive charges are written from the Y electrode YE to the X electrode XE and the address electrodes AR, AG, and AB.

Next, after all the X electrodes XE are set to the ground level (0V), the voltage Vxa is applied to all the X electrodes XE, and the voltage gradually drops to all the Y electrodes YE, and finally becomes negative. The obtuse wave that reaches the voltage is applied. As a result, a weak discharge is started between the electrodes exceeding the discharge start voltage due to the voltage of the wall charges themselves accumulated in each electrode. By this weak discharge, the wall charges accumulated on the electrodes are erased except for a part.

As described above, in the reset period TR, regardless of the remaining state of the wall charge of each cell at the end of the immediately preceding sustain period TS (at the start of the reset period TR),
The charged state (wall charge formation state) of all the cells of the PDP is made uniform. As a result, in the next address period TA, the address (write) discharge for selecting the lighted cell can be stably performed.

Next, in the address period TA, each cell is turned on (lighted) / OF according to display data such as a video signal.
In order to select F (light off), address discharge is performed line-sequentially. All the X electrodes XE and all the Y electrodes YE are biased to a predetermined potential, and the Y electrodes YE
Is used as a scan electrode, and a scan pulse (voltage −Vys) is sequentially applied to each Y electrode YE corresponding to the selected row. At the same time as this row selection, an address pulse (voltage Va) is applied to the address electrodes AR, AG, and AB corresponding to the selected cells (cells to be lit in the sustain period TS) that generate address discharge.

As a result, a discharge is generated between the YA electrodes of the selected cell, and the discharge is generated between the XY electrodes of the selected cell by using it as a trigger. As a result, the amount of wall charges capable of sustaining discharge is accumulated in the X electrode XE and the Y electrode YE of the selected cell. Thereafter, similarly, scan pulses are sequentially applied to the Y electrodes YE, and the above-described operation is repeated to obtain the PDP.
ON (lighting) / OFF (lighting off) is selected for all the cells.

In the sustain period TS, the sustain pulse (voltage Vs) is alternately applied to the X electrode XE and the Y electrode YE. As a result, using the wall charges formed in the address period TA, the sustain discharge according to the display brightness is performed in the lighting cell, and the cell is lit.

[0014]

Here, at the start of the reset period TR in the driving method of the AC drive type PDP shown in FIG. 15, the polarity and the amount of the wall charges remaining in each electrode are the same as the immediately preceding subframe. It depends on the status such as whether or not the cell is turned on.

Further, in the AC drive type PDP capable of color (multicolor) display, as shown in FIG.
At least three different phosphors for emitting green and blue are used. Therefore, the discharge characteristics of the cell differ depending on the material of the phosphor, the fineness of the particles, the dielectric constant, the width of the phosphor layer, the filling rate (thickness), the surface state, and the like. Therefore, the discharge start voltage between the YA electrodes of the cell varies depending on the type of the phosphor layer, that is, the emission color of the cell.

However, as shown in FIG. 15, in the reset period TR, the potential difference between all the YA electrodes is irrespective of the state of the cell at the start of the reset period TR and the phosphor layer (emission color) of the cell. The same voltage was applied to all the address electrodes AR, AG, and AB so that the maximum discharge start voltage was reached. Therefore, the potential difference between the YA electrodes is discharged in a cell that emits a specific color whose discharge start voltage of the cell is lower than the highest discharge start voltage, which should not be emitted, which is in the OFF state in the immediately preceding subframe. Discharge was performed over the starting voltage, and a region of the display screen, which should be non-light emitting, sometimes emitted light. This light emission is called background light emission and is one of the causes for lowering the display contrast.

The present invention has been made to solve such a problem, and an object thereof is to reduce background light emission in a plasma display panel and improve display quality. .

[0018]

According to the driving method of the plasma display panel of the present invention, one frame includes n (n) frames.
In the reset period of at least one sub-frame among sub-frames divided into two or more), the same voltage is applied to the Y electrodes, and at least three phosphor layers having different emission colors correspond to each other. The same voltage is applied to the provided address electrodes regardless of the emission color, and the same voltage is applied to the Y electrodes in the reset period of at most (n-1) subframes, and the address electrodes emit the light. A voltage corresponding to the color is applied.

According to the present invention, in the reset period of at most (n-1) subframes, an appropriate voltage is set for each emission color according to the state of the cell in the immediately preceding subframe and the emission color of the cell. It is possible to prevent the discharge cells from being discharged in the unlit cells in the immediately preceding subframe by applying the voltage to the address electrodes so that the potential difference between the YA electrodes in only the lit cells in the immediately preceding subframe becomes higher than the discharge start voltage. .

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description, a cell whose emission color is red is referred to as "cell-R", and a green cell is referred to as "cell-R".
G cells, and the blue cells are called "cell-B". The embodiment of the present invention is applied to, for example, an AC drive type plasma display device 1 as shown in FIG. As shown in FIG. 1, the AC-driven plasma display device 1 has a PD
P2, an X side drive circuit 3, a Y side drive circuit 4, an address drive circuit 5 and a control circuit 6.

The PDP 2 has a plurality of cells, which are unit light emitting elements, arranged in a matrix. The cell structure is
This is the same as the cell structure shown in FIG. 14 described above. In FIG. 1, cells C _ij arranged in a matrix of n rows and m columns.
(I and j are subscripts, i = 1 to n is an integer, j =
It shows an AC drive type PDP consisting of (integer of 1 to m).

As shown in FIG. 14, the PDP 2 is provided with X electrodes X1 to Xn and Y electrodes Y1 to Yn, which are sustain discharge electrodes, on the first substrate (front side) in parallel with each other. , The X electrodes X1 to Xn and the Y electrodes Y1 to Y2 on the second substrate (back surface side) facing the first substrate.
Address electrodes A1 to Am are provided in a direction orthogonal to Yn. The X electrodes X1 to Xn and the Y electrode Y
1 to Yn are a set of an X electrode X1 and a Y electrode Y1, an X electrode X
2 and Y electrode Y2 are arranged so that the X electrode and the Y electrode of a corresponding set such as.

The X electrodes X1 to Xn are connected to the X side drive circuit 3
Of the Y electrodes Y1 to Yn connected to the output terminals of
They are connected to the output terminals of the side drive circuit 4, respectively. The address electrodes A1 to Am are connected to the output terminals of the address drive circuit 5, respectively.

The X-side drive circuit 3 is composed of a circuit that repeats discharge, and the Y-side drive circuit 4 is composed of a circuit that scans line-sequentially and a circuit that repeats discharge. Also, the address drive circuit 5
Consists of a circuit that selects the columns to be displayed. By determining which cell is to be turned on by the line sequential scanning circuit in the address drive circuit 5 and the Y side drive circuit 4, and by repeating the discharge by the circuit that repeats the discharge of the X side drive circuit 3 and the Y side drive circuit 4. , PDP2 display operation is performed. The X-side drive circuit 3, the Y-side drive circuit 4, and the address drive circuit 5 are controlled by a control signal supplied from the control circuit 6.

The control circuit 6 detects the display data D, the horizontal synchronizing signal HS and the vertical synchronizing signal VS based on the video signal VD supplied from the outside. Further, the control circuit 6
Generates the control signal based on the detection result, and supplies the control signal to the X-side drive circuit 3, the Y-side drive circuit 4, and the address drive circuit 5, respectively.

(First Embodiment) FIG. 16 is a diagram for explaining frame division. In an AC drive type PDP, an input image is composed of time-series frames FRM (frame period TF). One frame FRM
Is composed of a plurality of subframes SF (SF _{1 to} SF _q (q is a natural number of 2 or more)). In addition, each subframe SF (subframe period TSF) has a reset period TR.
, And an address period TA and a sustain period TS.

In the driving method of the AC drive type PDP according to the embodiment of the present invention, which will be described in detail below, q sub-frames SF (SF _{1 to} S ₁ ) constituting one frame FRM are formed.
In the reset period TR of r (where r is a natural number of 1 ≦ r <q) subfields SF of F _q ), both the lit cells and the extinguished cells of the immediately preceding subfield SF are reset. Regarding the reset period TR of the (q−r) subfields SF, the immediately preceding subfield SF
Only the lit cells of are reset.

Specifically, during the reset period TR of the r subfields SF, according to the same drive waveform diagram as shown in FIG. Each electrode is driven so that the potential difference between the electrodes becomes the same. Also, (q−r) subfields SF
In the reset period TR of YA, according to the drive waveform diagram as shown in FIG.
Each electrode is driven so as to change the potential difference between the electrodes.
Note that in FIG. 17B, the reset between the in-plane electrodes (XY electrodes), that is, the discharge between the XY electrodes is as shown in FIG.
It is assumed that the operation is performed before driving as shown in (B).

As shown in FIG. 17B, each electrode is driven to reset only the lighted cells of the immediately preceding subfield SF (q-r) in the reset period TR of the subfields SF, the YA electrodes are reset. By setting the potential difference between the cells to a potential difference corresponding to the emission color of the cells, it is possible to prevent background light emission in which the unlit cells in the immediately preceding subfield SF emit light in the reset period TR of the (q−r) subfields SF. The display quality can be improved. In the reset period TR, according to the same drive waveform diagram as the conventional one, the immediately preceding subfield S
At least one of the q subframes SF is provided as a subfield for resetting both the illuminated cells and the extinguished cells of F. Further, when the PDP scanning method is the progressive method, an arbitrary subframe SF in the q subframes SF can be used as a subfield for resetting both the lighted cells and the unlit cells, and the scanning method is In the case of the interlace system, the frame FRM
The first sub-frame SF is set as a sub-field for resetting at least both the lighted cells and the unlit cells.

For example, when one frame FRM is composed of 10 sub-frames SF, in the reset period TR of one sub-field SF, the lighted cells and the extinguished cells of the immediately preceding sub-field SF are the same as in the conventional case. For the reset period TR of the remaining nine subfields SF.
It is assumed that only the lighted cells of F are reset. In this case, the background light emission in the PDP becomes 1/10 of the conventional one, the background light emission during the reset period TR can be significantly reduced, and the display contrast can be enhanced.

The subfield S immediately before in the reset period TR as shown in the example in FIG. 17B will be described below.
A method of driving an AC-driven PDP that resets only the F lit cells will be described in detail.

FIG. 2 is a drive waveform diagram showing an example of a driving method of the AC drive type PDP according to the first embodiment of the present invention, and is a plurality of sub-frames S constituting one frame FRM.
One sub-frame SF of F is shown. In addition,
In FIG. 2, Y corresponding to the emission color of the cell (phosphor layer)
The discharge start voltage between the A electrodes is in the order of red (R) <blue (B) <green (G), and the discharge start voltage Vfg between the YA electrodes of the cell-G is different from that of the YA electrode of the cell-B. The discharge start voltage Vfb between them is only the voltage Va1 (Va1> 0), and the discharge start voltage Vfr between the YA electrodes of the cell-R is the voltage Va2 (Va2).
> Va1), respectively.

As described above, one subframe SF is divided into the reset period TR, the address period TA, and the sustain period TS. In the following description, at the start of the reset period TR, a negative charge remains in the X electrode XE and a positive charge remains in the Y electrode YE of the lighting cell lighted in the immediately previous sustain period TS. I shall. Similarly, the X of unlit cells that are not lit
It is assumed that the positive charge remains on the electrode XE and the negative charge remains on the Y electrode YE.

In the reset period TR, first, an in-plane electrode writing period TRP for resetting between the in-plane electrodes is performed.
At the same time, the voltage −Vxp is applied to all the X electrodes XE, and at the same time, the obtuse wave which gradually increases the voltage and finally reaches the voltage Vyp is applied to all the Y electrodes YE. At this time, all the address electrodes AR, AG, AB are set to the ground level (0
V). In the in-plane electrode writing period TRP, X
Voltage −V applied to each of the electrode XE and the Y electrode YE
In xp and Vyp, since the discharge start voltage Vfp between the XY electrodes does not change according to the emission color of the cell, all the X electrodes XE
The same voltage is applied to the Y electrode YE. Here, the voltages −Vxp and Vyp are determined by the contribution of the wall charges formed on the X electrode XE and the Y electrode YE in accordance with the state (lighting / extinguishing) of the cell in the immediately previous subframe SF, and thus the immediately preceding subframe. In the SF lit cells, the potential difference between the XY electrodes is higher than the discharge start voltage Vfp, and in the unlit cells, the potential difference between the XY electrodes is lower than the discharge start voltage Vfp. As a result, the potential difference between the XY electrodes of the lighted cells in the immediately preceding subframe SF is equal to the discharge start voltage Vfp.
The discharge between the XY electrodes is sequentially started from the cell reaching
Writing of positive charges from the Y electrode YE to the X electrode XE is performed.

Next, all of the X electrode XE and the Y electrode YE are set to the ground level (0V). After that, in the counter electrode writing period TRO in which the reset is performed between the counter electrodes, the voltage Va2 is applied to the address electrode AR and the voltage Va1 is applied to the address electrode AB. The address electrode AG remains at the ground level (0V). Further, the voltage Vxa is applied to all the X electrodes XE, and the obtuse waveform that gradually increases and finally reaches the voltage Vy (for example, after 20 μs or more) is applied to all the Y electrodes YE.

Here, the potential difference between the YA electrodes caused by the voltage applied in the counter electrode writing period TRO is as shown in FIG. 3, as shown in FIG.
The potential difference VDR1 between and becomes (Vy-Va2). In addition, the potential difference VD between the Y electrode YE and the address electrode AB
B1 becomes (Vy-Va1), and the potential difference VDG1 between the Y electrode YE and the address electrode AG becomes (Vy-GND). That is, the potential difference VDR1, VDB between the YA electrodes
1, VDG1 is red (Vy-Va2) <blue (Vy-Va)
1) <Green (Vy-GND).

The Y electrode YE and the address electrode A
Voltages Vy, Va2, Va1 applied to R and AB, respectively
Is due to the contribution of the wall charges formed on each electrode in accordance with the state (lighting / lighting-out) of the cell in the immediately preceding subframe SF, and corresponds to the light emission color of the cell in the lighted cell in the immediately preceding subframe SF. The voltage value is such that the potential difference between the YA electrodes becomes higher than the discharge start voltages Vfr, Vfb, Vfg, and the potential difference between the YA electrodes becomes lower than the discharge start voltages Vfr, Vfb, Vfg in the extinguished cell.

As a result, among the lit cells of the immediately preceding sub-frame SF, the cells of which the potential difference between the YA electrodes has reached the discharge start voltages Vfr, Vfg, Vfb of the respective cells are sequentially started to discharge between the YA electrodes. Then, the positive charge is written from the Y electrode YE to the address electrodes AR, AG, and AB. In all the extinguished cells of the immediately preceding subframe SF, regardless of the emission color, Y
Since the potential difference between the A electrodes is an appropriate potential difference smaller than the discharge start voltage in the cells of each luminescent color, it is possible to prevent the discharge and light emission by reaching the discharge start voltage.

Next, the address electrodes AR, AG, and AB are set to the ground level (0 V), and a blunt wave that finally reaches a negative voltage is applied to all the Y electrodes YE, so that the walls accumulated in each electrode. A weak discharge is started between the electrodes exceeding the discharge start voltage by the voltage of the charge itself. By this weak discharge, the wall charges accumulated on the electrodes are erased except for a part.

In this way, q subframes SF
Among these, in the reset period TR of the (q−r) subframes SF, only the lit cells of the immediately preceding subframe SF are reset (discharged between the YA electrodes) and the unlit cells are not reset. The state of the wall charges on the electrodes of the lighted cells and the light-off cells of the sub-frame SF is made the same. As a result, in the next address period TA, the address (write) discharge for selecting the lighted cell can be stably performed.

Next, in the address period TA, each cell is turned ON (lighted) / OF in accordance with display data such as a video signal.
In order to select F (light off), address discharge is performed line-sequentially. All the X electrodes XE and all the Y electrodes YE are biased to a predetermined potential, and the Y electrodes YE
Is used as a scan electrode, and a scan pulse (voltage −Vys) is applied to one Y electrode YE corresponding to the selected row. Address electrodes AR and A corresponding to a selected cell (cell to be lit) that causes address discharge at the same time as this row selection
The address pulse (voltage Va) is applied only to G and AB.

As a result, discharge is generated between the YA electrodes of the selected cell, and triggered by this, discharge is generated between the XY electrodes of the selected cell. As a result, the amount of wall charges capable of sustaining discharge is accumulated in the X electrode XE and the Y electrode YE of the selected cell. Similarly, the scan pulse (voltage-Vys) is set to 1
By sequentially applying each of the Y electrodes YE and repeating the above-described operation, turning on / off of all cells of the PDP is selected.

In the sustain period TS, all Y
A sustain pulse (voltage Vs) is applied to the electrode YE.
After that, the sustain pulse is alternately applied to the X electrode XE and the Y electrode YE. As a result, using the wall charges formed in the address period TA, the sustain discharge according to the display brightness is performed in the lighting cell, and the cell is lit.

FIGS. 4 (a) to 4 (c) show a configuration example of a voltage output circuit for applying two kinds of voltages to the address electrodes AR, AG, AB like the drive waveforms shown in FIG. It is a figure. FIG. 4A is a voltage output circuit for applying the voltage Va and the voltage RVa to the address electrode AR, and includes four switches RSW1 to RSW4. Each of the switches RSW1 to RSW4 is composed of a transistor (for example, a MOS-FET transistor), and each of the switches RSW1 and RSW2 has one diode.

The other end of the switch RSW1 whose one end is connected to the voltage source supplying the voltage Va and the other end of the switch RSW2 whose one end is connected to the voltage source supplying the voltage RVa are connected to each other, and their interconnection points are connected. Is connected to one end of the switch RSW3. The other end of the switch RSW3 is connected to the other end of the switch RSW4 whose one end is connected to the ground (GND), and is an output signal for outputting the voltage applied to the address electrode AR at the interconnection point between the switches RSW3 and RSW4. The lines are connected.

When the switches RSW1 and RSW3 are turned on and the switches RSW2 and RSW4 are turned off, the voltage of the output signal line becomes the voltage Va. Similarly, turn on the switches RSW2 and RSW3,
When the switches RSW1 and RSW4 are turned off, the voltage of the output signal line becomes the voltage RVa. Further, the switch RSW3 is turned off and the switch RSW4 is turned on.
When in N state, the voltage of the output signal line is ground (0V)
And both switches RSW3 and RSW4 are turned off.
In the F state, the output signal line is in a high impedance state.

In the voltage output circuit shown in FIG. 4A, the voltage RVa is set to the voltage Va2 and the switches RSW1 to RSW are used.
As shown in FIG. 3, it is possible to apply the voltages Va2 and Va to the address electrode AR or to set the address electrode AR to the ground level by controlling 4 appropriately.

FIG. 4B shows the voltage Va and the voltage BVa.
Is a voltage output circuit for applying the voltage to the address electrode AB, and FIG. 4C is a voltage output circuit for applying the voltage Va and the voltage GVa to the address electrode AG. The voltage output circuit shown in FIGS. 4B and 4C is
Since it has the same configuration as the voltage output circuit shown in FIG. 4A, the description thereof will be omitted. In the voltage output circuit shown in FIG. 4 (b), the voltage BVa is set to the voltage Va1, and the voltage source for supplying the voltage GVa in the voltage output circuit shown in FIG. 4 (c) is not connected (or an arbitrary voltage source). And switch G
By setting SW2 to the OFF state at all times), the address electrodes AB and AG can be driven as shown in FIG.

FIG. 5 is a drive waveform diagram showing another example of the driving method of the AC drive type PDP according to the first embodiment of the present invention. In FIG. 5, only the counter electrode writing period TRO within the reset period TR is shown. The drive waveforms are the same as those shown in FIG. 2 except the counter electrode writing period TRO. FIG. 5 shows the discharge start voltage Vfr between the YA electrodes of the cell-R and the cell-B,
Vfb is close to each other, and the discharge start voltages Vfr, V
FIG. 9 is a drive waveform diagram when fb is lower than the discharge start voltage Vfg between the YA electrodes of the cell-G by the same voltage Va as the address pulse voltage. That is, the relationship between the discharge start voltages Vfr, Vfb, and Vfg between the YA electrodes is Vfr = Vfb <
It is a drive waveform diagram in the case of Vfg.

In this case, the counter electrode writing period TR
At O, the address electrode AG is set to the ground level,
The voltage Va is applied to the address electrode AR and the address electrode AB, respectively. In addition, a blunt wave whose voltage gradually rises and finally reaches the voltage Vy is applied to all the Y electrodes YE.
Although not shown, the voltage Vxa is applied to all the X electrodes XE.

Therefore, the counter electrode writing period TRO
The potential difference between the YA electrodes caused by the voltage applied at is the potential difference V between the Y electrode YE and the address electrode AR.
DR2 and the potential difference VDB2 between the Y electrode YE and the address electrode AB are both (Vy-Va). In addition, the potential difference VD between the Y electrode YE and the address electrode AG
G2 becomes (Vy-GND) and becomes larger than the potential differences VDR2 and VDB2 by the voltage Va. Note that, similarly to the example shown in FIG. 2 described above, the voltage Vy is immediately before the voltage Vy due to the contribution of the wall charges formed in each electrode according to the state (lighting / lighting off) of the cell in the immediately previous subframe SF. The voltage value is such that the potential difference between the YA electrodes is higher than the discharge start voltage in the lit cells of the sub-frame SF, and the potential difference between the YA electrodes is lower than the discharge start voltage in the unlit cells.

As a result, even if the voltage output circuit as shown in FIGS. 4 (a) to 4 (c) is not newly provided, the circuit for applying the address pulse can be used to detect the immediately preceding sub-frame SF. Since the potential difference between the YA electrodes in all the extinguished cells becomes an appropriate potential difference according to the discharge start voltage regardless of the emission color, it is possible to prevent reaching the discharge start voltage and reduce the background light emission. You can

FIG. 6 is a block diagram showing a concrete configuration example of the control circuit 6 for realizing the driving method of the AC drive type PDP described above. In FIG. 6, blocks having the same functions as the blocks shown in FIG. 1 are designated by the same reference numerals, and duplicated description will be omitted. Further, FIG. 6 shows components for driving the address electrodes AR, AB, AG.

In FIG. 6, the control circuit 6 includes a sync signal detection circuit 61, a drive signal control circuit 62, and an A / D converter 6.
3, a video signal / subframe correlator 64, a selector 65, and a selective reset generation circuit 66.

The sync signal detection circuit 61 detects sync signals such as the horizontal sync signal HS and the vertical sync signal VS from the video signal VD supplied from the outside, and the drive signal control circuit 6
Supply to 2. The drive signal control circuit 62 responds to the synchronization signals HS and VS supplied from the synchronization signal detection circuit 61,
Control signals CTLX, CTLY, CTLA, and CTLS for controlling the respective functional units for driving the PDP 2 are output to the X-side drive circuit 3, the Y-side drive circuit 4, the address drive circuit 5, and the selector 65, respectively.

The A / D converter 63 converts the externally supplied video signal VD into a digital signal (display data) and supplies it to the video signal / subframe correlator 64. The video signal / sub-frame correlator 64 determines whether to light each cell of the PDP 2 based on the supplied display data, that is, whether to apply an address pulse to the address electrode A in the address period TA. Determined for each subframe. Further, based on the above determination, the selector 6 outputs the control signal CTLD for outputting the address pulse.
Output to 5.

The selector 65, based on the control signal CTLS supplied from the drive signal control circuit 62, outputs a video signal
Control signal C supplied from subframe correlator 64
The control signal RST supplied from the TLD and selective reset generation circuit 66 is selectively output to the address drive circuit 5 as the control signal CTLR. Selective reset generation circuit 6
In the counter electrode writing period TRO, 6 is a voltage corresponding to the emission color of the cell as described above.
A control signal RST to be applied to R, AB and AG is generated and output.

By configuring the control circuit 6 in this way,
Control signal CTLS supplied from drive signal control circuit 62
Based on the above, the control signal RST supplied from the selective reset generation circuit 66 is selected by the selector 65 in the reset period TR (counter electrode writing period TRO), and the video signal / subframe correlator 6 is selected in the address period TA.
The control signal CTLD supplied from 4 is selected by the selector 65. Then, the selected control signal is output to the address drive circuit 5 as the control signal CTLR.

The address drive circuit 5 is responsive to the supplied control signals CTLA and CTLR to reset period TR.
In the (counter electrode writing period TRO), the PDP follows the control signal RST supplied as the control signal CTLR.
The second address electrode A is driven. Also, the address period T
In A, the address electrode A of the PDP 2 is driven according to the control signal CTLD supplied as the control signal CTLR. As described above, according to the control circuit 6, the address electrodes AR, AB,
A predetermined voltage can be applied to AG.

As described above in detail, according to the present embodiment, in the counter electrode writing period TRO of the r subframes SF out of the q subframes SF constituting one frame FRM, the emission color is changed. Regardless, the address electrodes are driven so that the same voltage is applied, and in the counter electrode writing period TRO of (q−r) subframes SF, the discharge start voltage Vfr between the YA electrodes corresponding to the emission color,
The potential difference between the YA electrodes is controlled according to the emission color of the cell by driving the address electrodes so that a voltage is applied for each emission color based on Vfb and Vfg. This allows
In the reset period of the (q−r) subframes SF, in the extinguished cells of the immediately preceding subframe SF, the potential difference between the YA electrodes of the cells becomes the discharge start voltage in the cells of the respective emission colors regardless of the emission color. In addition, since the potential difference becomes appropriate, it is possible to prevent the discharge starting voltage from being reached. Therefore, (q−r) subframes S
Prevent background light emission during the reset period TR in F, and
The background light emission in one frame FRM can be reduced to r / q times that of the conventional case, and the display contrast can be increased.

Further, since it is possible to reset for each emission color by an appropriate potential difference between the YA electrodes, it is possible to reduce the applied voltage difference for each emission color in the address period, so that the PDP can be reduced.
The operating voltage margin can be expanded.

In the first embodiment described above, the case where a voltage is applied to two address electrodes in the counter electrode writing period TRO is shown as an example, but the present invention is not limited to this, and one address is used. The voltage may be applied only to the electrodes.

(Second Embodiment) Also in the second embodiment of the present invention, as in the first embodiment described above, q sub-frames SF constituting one frame FRM.
Of the (SF _{1 to} SF _q ), the reset period TR of the r (r is a natural number of 1 ≦ r <q) subfields SF is similar to the conventional one in the lighting cell and the extinguishing cell of the immediately preceding subfield SF. Both are reset, and during the reset period TR of the (q−r) subfields SF, only the lighted cells of the immediately preceding subfield SF are reset.
The driving method of the AC-driven PDP that resets only the lighted cells of the immediately preceding subfield SF in the reset period TR according to the second embodiment of the present invention will be described in detail below.

FIG. 7 is a drive waveform diagram showing an example of a method of driving an AC drive type PDP according to the second embodiment of the present invention. Note that FIG. 7 shows only the counter electrode writing period TRO within the reset period TR, and the period other than the counter electrode writing period TRO is the same as the drive waveform shown in FIG. FIG. 7 shows that the discharge start voltage Vfr between the YA electrodes of the cell-R is lower than the discharge start voltage Vfg between the YA electrodes of the cell-G by the voltage Va, and
The discharge start voltage Vfb between the A electrodes is the voltage (Vy-Vy1).
It is a drive waveform diagram in the case of being low only by ((Vy-Vy1) <Va).

In the counter electrode writing period TRO, first, the address electrodes AB and AG are set to the ground level, and the voltage Va is applied to the address electrode AR. Also,
The voltage gradually rises to all the Y electrodes YE and finally the voltage V
A blunt wave reaching y is applied. When the voltage applied to the Y electrode YE becomes the voltage Vy1, the voltage Va is applied to the address electrode AB. Although not shown, the voltage Vxa is applied to all the X electrodes XE.

By driving in this manner, Y generated by the voltage applied in the counter electrode writing period TRO.
Regarding the potential difference between the A electrodes, the potential difference VDR3 between the Y electrode YE and the address electrode AR becomes (Vy−Va), and the potential difference VDG3 between the Y electrode YE and the address electrode AG becomes (V
y-GND). The potential difference VDB3 between the Y electrode YE and the address electrode AB becomes (Vy1-GND) when the voltage Va is applied to the address electrode AB,
Immediately before the end of the counter electrode writing period TRO, (Vy−V
a). Since (Vy−Vy1) <Va here, the maximum value of the potential difference VDB3 in the counter electrode writing period TRO is (Vy1−GND). The voltage Vy,
Vy1 is the state of the cell in the immediately preceding subframe (lighting /
Due to the contribution of the wall charges formed on each electrode according to (light off), the potential difference between the YA electrodes in the lighting cell of the immediately preceding subframe becomes higher than the discharge start voltage, and the YA
The voltage value is such that the potential difference between the electrodes becomes lower than the discharge start voltage.

As a result, it is possible to appropriately apply the discharge start voltages Vfr, Vfb, and Vfg corresponding to the emission color of the cell between the YA electrodes by using the circuit for applying the address pulse. Therefore, the potential difference between the respective YA electrodes in all the extinguished cells of the immediately preceding subframe SF becomes an appropriate potential difference in accordance with the discharge start voltage in the cells regardless of the emission color, and therefore the discharge start voltage is reached. It is possible to prevent the light emission and reduce the background light emission.

FIG. 8 is a circuit diagram for explaining the operation when driving the address electrodes AR, AG, and AB like the drive waveforms shown in FIG. In FIG. 8, XE,
YE and AE are an X electrode, a Y electrode, and an address electrode, respectively, and CX, CY, and CA are X electrodes, respectively.
3 schematically shows the capacitance formed by dielectric layers of electrodes, Y electrodes and address electrodes.

The switches SWU and SWD are composed of transistors (for example, MOS-FET transistors). One end of the switch SWU is connected to a voltage source that supplies the voltage Va, and one end of the switch SWD is connected to the ground (GN
D). The other end of the switch SWU and the switch S
The other end of WD is connected, and the address electrode AE is connected to the interconnection point. The circuit shown in FIG.
At least the address electrodes AR, AB, and AG are independent circuits, and the switches SWU and SWD can be independently controlled for the address electrodes AR, AB, and AG, respectively.

In the circuit shown in FIG. 8, the voltage SW is applied to the address electrode AE by turning on the switch SWU and turning off the switch SWD,
Conversely, the switch SWU is turned off and the switch SW
By setting D to the ON state, the address electrode AE becomes the ground level. Further, when both the switches SWU and SWD are turned off, the address electrode AE goes into a high impedance state.

Therefore, when the drive waveform shown in FIG. 7 is realized, the switches SWU of the address electrodes AR, AB, and AG are in the OFF state and the switches SWD are in the ON state at the start of the counter electrode writing period TRO.
In this case, first, the switch SWD of the address electrode AR is turned off and the switch SWU is turned on.
To ON state. After that, when the voltage applied to the Y electrode YE becomes the voltage Vy1, the switch SWD of the address electrode AB is turned off and the switch S
Turn on the WU. Then, at the end of the counter electrode writing period TRO, the switches SWU of the address electrodes AR, AB, and AG are turned off, and the switch SWD.
Are turned on.

FIG. 9 is a drive waveform diagram showing another example of the driving method of the AC drive type PDP according to the second embodiment of the present invention, and shows only the counter electrode writing period TRO.
The drive waveforms are the same as those shown in FIG. 2 except the counter electrode writing period TRO. Figure 9
Similar to FIG. 7, the discharge start voltage Vfr is lower than the discharge start voltage Vfg by the voltage Va, and the discharge start voltage Vf
b is a voltage (Vy-Vy1) ((Vy-Vy1) <Va)
It is a drive waveform diagram in the case of only low.

In the counter electrode writing period TRO, first, the address electrodes AB and AG are set to the ground level. Regarding the address electrode AR, both the switches SWU and SWD shown in FIG. 8 are turned off,
The address electrode AR is set to a high impedance state.
In addition, a blunt wave whose voltage gradually rises and finally reaches the voltage Vy is applied to all the Y electrodes YE. Although not shown, the voltage Vxa is applied to all the X electrodes XE.

As a result, the voltage of the address electrode AR becomes
It is pulled up as the voltage applied to the Y electrode YE rises. Then, when the voltage of the address electrode AR becomes the voltage Va, the voltage of the address electrode AR does not rise and is maintained at the voltage Va due to the action of the diode D1 in the switch SWU shown in FIG.

After that, when the voltage applied to the Y electrode YE becomes the voltage Vy1, the switch S of the address electrode AB shown in FIG.
Both the WU and SWD are turned off, and the address electrode AB is set to the high impedance state. This allows
The voltage of the address electrode AB is raised as the voltage applied to the Y electrode YE rises. Where (Vy-V
Since y1) <Va, the potential of the address electrode AB is
It is pulled up to (Vy-Vy1).

In this way, the switches SWU and SWD of the address electrodes AR and AB are appropriately controlled, and the address electrodes AR and
By setting AB to a high impedance at an appropriate timing, it is possible to generate the same potential difference between the YA electrodes as the potential difference between the YA electrodes according to the drive waveform shown in FIG.

AC drive type P shown in FIGS. 7 and 9 above.
The address drive circuit 5 that realizes the DP driving method will be described with reference to FIGS. 10 and 11. Figure 10
FIG. 3 is a block diagram showing a configuration example of a general address drive circuit 5 used conventionally. Flip flop FF
1 to FFn and the latch LT are control circuits 6 not shown.
Display data supplied from can be shifted or synchronized. Further, the selector SEL, based on the control signals TSC, SUS, STB supplied from the control circuit 6,
High voltage output circuit HOU for outputting high voltage to PDP2
Output control of T is performed.

The control signal TSC is low level (hereinafter,
Write "'L'". ) Is a signal for setting the output of the high voltage output circuit HOUT to high impedance. Control signal SU
S is a signal that outputs a high voltage from the high-voltage output circuit HOUT at a high level (hereinafter, referred to as "'H'") and sets the output of the high-voltage output circuit HOUT at a ground level at "L". The control signal STB is a data enable signal for the high voltage output circuit HOUT, and outputs data at'H '. For example, when the control signals TSC and SUS are both “H” and the control signal STB is “L”, the high voltage output circuit HOU
T outputs the voltage Va, while the control signal STB is'H '.
In this case, the high voltage output circuit HOUT outputs the voltage Va or the ground level according to the data.

Here, in the conventional address drive circuit 5 shown in FIG. 10, the control signals TSC, SUS, S are added.
TB was a signal commonly used for all cells regardless of the emission color of the cells. Therefore, it was not possible to drive the PDP 2 using the drive waveform as shown in FIG.

Therefore, in the address drive circuit 5 for realizing the drive method according to the second embodiment of the present invention, as shown in FIG. 11, control signals TSC, SUS, S are used.
TB is provided for each color of light emitted from the cell, and each cell can be controlled independently. FIG. 11 is a block diagram showing a configuration example of the address drive circuit 5 in the second embodiment. Note that, in FIG. 11, blocks having the same functions as the blocks shown in FIG. 10 are designated by the same reference numerals, and redundant description will be omitted.

The address drive circuit 5 in the second embodiment has a control signal TSC- for controlling the cell-R.
R, SUS-R and STB-R are input. Similarly, control signals TSC-G and SUS- for controlling the cell-G.
Control signals TSC-B, SUS-B, and STB-B for controlling G, STB-G, and cell-B are input.

Accordingly, the address drive circuit 5 in the second embodiment has the R (red) selectors SELR and G.
(Green) selector SELG and B (blue) selector S
Each ELB is provided. And the selector SEL for R
R / G selector SELG and B selector SELB
The control signals TSC, SUS, and STB corresponding to are respectively supplied. By configuring the address drive circuit 5 as described above, control of high impedance and low impedance (voltage Va or output of ground) in the output of the high-voltage output circuit HOUT is possible independently for each emission color of the cell. Becomes As a result, the PDP 2 can be driven using the drive waveform as shown in FIG.

In FIG. 11, the control signals TSC, SUS and STB are input for each color of light emitted from the cell, and the corresponding selectors SEL-R, SEL-G and
Although the SEL-B is provided, the control signals TSC, SUS, and S for any one of the emission colors are output according to the discharge start voltage of the cell-R, the cell-G, and the cell-B.
Only TB may be independently input, and the control signals TSC, SUS, and STB for other emission colors may be input as common signals.

As described above in detail, according to the second embodiment, light is emitted in the counter electrode writing period TRO of r sub-frames SF out of q sub-frames SF constituting one frame FRM. The address electrodes are driven so that the same voltage is applied at the same timing regardless of color, and in the counter electrode writing period TRO of the (q−r) subframes SF, the discharge start voltage between the YA electrodes according to the emission color is generated. Based on Vfr, Vfb, and Vfg, the timing of applying a voltage to the address electrodes is controlled for each emission color, and the potential difference between the YA electrodes is controlled. This gives (q
-R) in the reset period of the subframes SF,
In the light-off cell of the immediately preceding subframe, the potential difference between the YA electrodes of the cells becomes an appropriate potential difference that is the discharge start voltage in the cells of each emission color, regardless of the emission color, and thus does not reach the discharge start voltage. Can be
Background light emission is prevented during the reset period TR, and 1 frame F
It is possible to reduce the background light emission in the RM by r / q times as compared with the conventional one and enhance the display contrast.

In the first and second embodiments described above, the in-plane electrode writing period TRP and the counter electrode writing period TRO are individually and independently provided in the reset period TR. As shown in FIG. 12, the in-plane electrode writing period TRP and the counter electrode writing period TRO may be overlapped and performed in the same period. For example, in the drive waveform of the reset period TR shown in FIG. 12, the in-plane electrode writing period TRP and the counter electrode writing period TRO are simultaneously started. After that, even if the in-plane electrode writing period TRP ends, the counter electrode writing period TRO is continued. In such a case, the reset period TR can be shortened, the number of times the electrodes are driven can be reduced, and the power consumption can be reduced.

Further, in the above-described first and second embodiments, the obtuse wave whose voltage changes with time at a constant change rate is applied to the electrodes. However, the present invention is not limited to this, and obtuse waves as shown in FIG. 13 may be applied to the electrodes. For example, in FIG.
As shown in FIG. 13A, a blunt wave showing a voltage change such that the rate of change of the voltage changes with the passage of time may be applied to the electrodes, or as shown in FIG. Alternatively, the voltage maintenance and the voltage maintenance may be alternately repeated at a constant time interval to apply a blunt wave whose voltage changes with time to the electrodes.

The above-described embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be limitedly interpreted by these. Is. That is, the present invention can be implemented in various forms without departing from its technical idea or its main features. Various aspects of the present invention are shown below as supplementary notes.

(Supplementary Note 1) An address electrode group having a stripe array and a plurality of address electrodes orthogonal to the address electrode group are provided by a plurality of address electrodes provided corresponding to at least three phosphor layers having different emission colors. A method of driving a plasma display panel having a first electrode group including first electrodes of at least one sub-frame among n sub-frames (n is a natural number of 2 or more). During the frame reset period, the same voltage is applied to the plurality of first electrodes, respectively, and the same voltage is applied to the address electrodes regardless of the emission color, and at most (n-1) subframes are applied. In the reset period, the same voltage is applied to the plurality of first electrodes, and a voltage corresponding to the emission color is applied to the address electrodes. The driving method of a plasma display panel, characterized in that the pressure.

(Supplementary Note 2) The plasma display panel is a three-electrode type plasma display panel further having a second electrode group consisting of a plurality of second electrodes respectively parallel to the plurality of first electrodes. The method for driving a plasma display panel according to the additional feature 1. (Supplementary Note 3) In the reset period of at most (n-1) sub-frames, the number of sub-frames corresponding to the discharge start voltage corresponding to the emission color between the address electrode and the first electrode 3. The method for driving a plasma display panel according to appendix 2, wherein a voltage is applied to each of the first electrode and the address electrode.

(Supplementary Note 4) The discharge start voltage in the first emission color is smaller than the discharge start voltage in the second emission color, and the discharge start voltage in the second emission color is in the third emission color. When the discharge start voltage is lower than the discharge start voltage, the first address electrodes provided corresponding to the phosphor layers of the first emission color have the first address electrodes in the reset period of at most (n-1) subframes. A voltage is applied and a second voltage is applied to the second address electrode provided corresponding to the phosphor layer of the second emission color, and the second address electrode is applied corresponding to the phosphor layer of the third emission color. A third voltage is applied to the provided third address electrode, the first voltage is a positive voltage, and the second and third voltages are ground levels. The method of driving the plasma display panel according to attachment 3.

(Supplementary Note 5) The driving method of the plasma display panel according to Supplementary Note 4, wherein the positive voltage is the same voltage as the address pulse. (Supplementary note 6) A drive circuit for driving the first address electrode, comprising a high voltage side switch for outputting the same voltage as the address pulse and a low voltage side switch for outputting the ground level. , Both the high voltage side switch and the low voltage side switch are opened, and the same voltage as the address pulse is applied to the first address electrode by using the voltage applied to the first electrode or the second electrode. The driving method of the plasma display panel according to appendix 4 or 5, wherein the following voltage is applied.

(Supplementary Note 7) The first and second voltages are:
5. The method for driving a plasma display panel according to appendix 4, wherein the voltages have the same positive polarity and the third voltage is a ground level. (Supplementary Note 8) The method of driving the plasma display panel according to Supplementary Note 7, wherein the positive voltage is the same voltage as the address pulse.

(Supplementary note 9) The method for driving a plasma display panel according to supplementary note 8, wherein the same voltage as that of the address pulse is applied simultaneously to the first and second address electrodes. (Supplementary note 10) The method for driving a plasma display panel according to supplementary note 8, wherein the same voltage as the address pulse is applied to the first and second address electrodes at different timings.

(Supplementary Note 11) Before applying the same voltage as the address pulse to the second address electrode, the same voltage as the address pulse is applied to the first address electrode, and the third address electrode is applied. 11. The method for driving a plasma display panel according to supplementary note 10, wherein the method is set to the ground level.

(Supplementary Note 12) Each of the first and second address electrodes is provided with a high voltage side switch for outputting the same voltage as the address pulse and a low voltage side switch for outputting the ground level. In the drive circuit for performing the above, the timing of opening both the high-voltage side switch and the low-voltage side switch is made different between the first address electrode and the second address electrode, and the first electrode or the above Using the voltage applied to the second electrode,
Supplementary Note 8 characterized in that a voltage equal to or lower than the same voltage as the address pulse is applied to the first and second address electrodes.
7. A method for driving a plasma display panel according to [4].

(Supplementary Note 13) Prior to opening both the high-voltage side switch and the low-voltage side switch of the second address electrode, the high-voltage side switch and the low-voltage side switch of the first address electrode are opened. 13. The method for driving a plasma display panel according to appendix 12, wherein both of the above are opened.

(Supplementary Note 14) The first voltage is equal to the second voltage.
5. The method of driving the plasma display panel according to appendix 4, wherein the second voltage is higher than the third voltage and the second voltage is higher than the third voltage. (Supplementary Note 15) The method for driving a plasma display panel according to Supplementary Note 14, wherein the third voltage is at the ground level.

(Supplementary Note 16) When the discharge start voltage in the first emission color, the discharge start voltage in the second emission color, and the discharge start voltage in the third emission color are different from each other, at most In the reset period of the (n-1) subframes, to drive the address electrode group having the high voltage side switch for outputting the high voltage and the low voltage side switch for outputting the low voltage, respectively. In the driving circuit, the timing for opening both the high-voltage side switch and the low-voltage side switch is made different for each of the emission colors, and the voltage applied to the first electrode or the second electrode is used. The method of driving the plasma display panel according to appendix 3, wherein a voltage is applied to the address electrode group.

(Supplementary Note 17) The discharge start voltage in the first emission color is smaller than the discharge start voltage in the second emission color, and the discharge start voltage in the second emission color is the third. When the discharge voltage is lower than the discharge start voltage for the emission color, the first address electrode provided corresponding to the phosphor layer for the first emission color in the reset period of at most (n-1) subframes. , A second address electrode provided corresponding to the phosphor layer of the second emission color, and a third address electrode provided corresponding to the phosphor layer of the third emission color. 17. The method for driving a plasma display panel according to appendix 16, wherein both the voltage side switch and the low voltage side switch are opened.

(Supplementary note 18) The method for driving a plasma display panel according to supplementary note 3, wherein a positive polarity and obtuse waveform of 20 microseconds or more is applied to the first electrode. (Supplementary note 19) A counter initialization period in which initialization is performed by the address electrode group and the first electrode group in the reset period of at most (n-1) subframes, and a counter initialization period. 19. The plasma according to appendix 18, characterized in that an in-plane initialization period for initializing only cells that have been lit before the reset period by the different first electrode group and the second electrode group is provided. Display panel driving method. (Supplementary Note 20) A counter initialization period in which initialization is performed by the address electrode group and the first electrode group in the reset period of at most (n−1) subframes, and a counter initialization period. 19. The in-plane initialization period in which the first electrode group and the second electrode group initialize only the cells that have been turned on before the reset period in the same period. Driving method for plasma display panel.

(Supplementary note 21) In the reset period of at most (n-1) subframes, the first charge caused by the wall charges formed in the cells that were extinguished before the reset period.
Voltage applied between the first electrode and the second electrode, and a voltage obtained by adding a discharge start voltage between the first electrode and the second electrode are applied to the first electrode. 4. The method for driving a plasma display panel according to appendix 3, wherein the initialization is performed by using the second electrode.

(Supplementary Note 22) In the reset period of at most (n-1) subframes, the address electrode and the first electrode due to the wall charges formed in the cells that are extinguished before the reset period. A voltage difference between the address electrode and the first electrode and a discharge start voltage between the address electrode and the first electrode.
4. The method for driving a plasma display panel according to appendix 3, wherein the initialization is performed with the electrodes of.

(Supplementary Note 23) The driving of the plasma display panel according to Supplementary Note 4, wherein the first and second voltages are ground levels and the third voltage is a negative voltage. Method. (Supplementary Note 24) The method for driving a plasma display panel according to Supplementary Note 4, wherein the first voltage is a ground level and the second and third voltages are equal negative voltages. (Supplementary note 25) The plasma display panel driving method according to Supplementary note 23 or 24, wherein the negative voltage is a voltage whose absolute value is equal to the voltage value of the address pulse. (Supplementary note 26) In the supplementary notes 4, 5, 9, and 11, the first emission color is red, the second emission color is blue, and the third emission color is green. The driving method of the plasma display panel according to any one of claims.

(Supplementary Note 27) An address electrode group having a stripe arrangement and a plurality of address electrodes orthogonal to the address electrode group are provided by a plurality of address electrodes provided corresponding to at least three phosphor layers having different emission colors. A plasma display device having a first electrode group including the first electrodes of at least one of subframes obtained by dividing one frame into n (n is a natural number of 2 or more)
In the reset period of one sub-frame, the address electrodes are simultaneously driven with the same voltage regardless of the emission color,
In the reset period of at most (n-1) sub-frames, a control circuit is provided which simultaneously drives the address electrodes provided corresponding to the phosphor layers of the same emission color with a voltage according to the emission color. A plasma display device characterized by the above.

(Supplementary note 28) The plasma display device according to supplementary note 27, wherein the control circuit can drive the address electrodes independently for each of the emission colors. (Supplementary note 29) The plasma display according to supplementary note 28, further comprising a drive circuit capable of driving the address electrodes into a high impedance state for each of the emission colors by a control signal provided for each of the emission colors. apparatus.

(Supplementary note 30) The plasma display device according to supplementary note 29, wherein the operation described in any one of supplementary notes 6, 10, 12 and 16 is realized by using the drive circuit. (Supplementary note 31) The address electrode is independently provided with respect to the other emission colors by a control signal provided separately for one emission color of the emission colors and other emission colors other than the emission color. 30. The plasma display device as set forth in appendix 29, further comprising a second drive circuit capable of driving the device into a high impedance state.

[0107]

As described above, according to the present invention,
In a plasma display panel having an address electrode group having a stripe array and a first electrode group orthogonal to the address electrode group, n frames (n
In the reset period of at least one subframe among subframes divided into two or more), the same voltage is applied to each of the plurality of first electrodes and the same voltage is applied regardless of the emission color of the phosphor layer. A voltage is applied to the address electrodes, and during the reset period of at most (n-1) subframes, the same voltage is applied to the first electrodes, and a voltage according to the emission color of the phosphor layer is applied. It is applied to the address electrode.

As a result, in the reset period of at most (n-1) subframes, an appropriate voltage is applied to the address electrode for each emission color according to the state of the cell in the immediately preceding subframe and the emission color of the cell. Due to the contribution of the wall charges formed corresponding to the state of the cell of the immediately preceding sub-frame, the potential difference between the YA electrodes of the lighted cells of the immediately preceding sub-frame is greater than the discharge start voltage regardless of the color of the applied light. Since the potential difference between the YA electrodes of the extinguished cells can be prevented from becoming higher than the discharge start voltage by increasing the voltage, it is possible to reduce the background emission in the plasma display panel and improve the display quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an AC drive type plasma display device 1.

FIG. 2 is a drive waveform diagram showing an example of a driving method of an AC drive type PDP according to the first embodiment.

FIG. 3 is a drive waveform diagram in a counter electrode writing period in the first embodiment.

FIG. 4 is a diagram showing a configuration example of a voltage output circuit in the first embodiment.

FIG. 5 is a diagram showing another example of drive waveforms in the counter electrode writing period in the first embodiment.

FIG. 6 is a block diagram showing a specific configuration example of a control circuit 6 that realizes the driving method of the AC drive type PDP according to the first embodiment.

FIG. 7 is a diagram showing an example of drive waveforms in a counter electrode writing period in the second embodiment.

FIG. 8 is a circuit diagram for explaining an operation when driving an address electrode in the second embodiment.

FIG. 9 is a diagram showing another example of drive waveforms in the counter electrode writing period in the second embodiment.

FIG. 10 is a block diagram showing a configuration example of a general address drive circuit 5.

FIG. 11 is a block diagram showing a configuration example of an address drive circuit 5 in a second embodiment.

FIG. 12 is a diagram showing another example of drive waveforms in a reset period.

FIG. 13 is a diagram showing another example of an obtuse waveform.

FIG. 14 is a diagram showing an example of a cell structure of a three-electrode surface discharge PDP.

FIG. 15 is a drive waveform diagram showing an example of a driving method of an AC drive type PDP.

FIG. 16 is a diagram for explaining frame division.

FIG. 17 is a diagram for explaining drive waveforms of an AC drive type PDP according to an embodiment of the present invention.

[Explanation of symbols]

1 AC drive type plasma display device 2 Plasma display panel (PDP) 3 X side drive circuit 4 Y side drive circuit 5 Address drive circuit 6 control circuit 61 Sync signal detection circuit 62 Drive signal control circuit 63 A / D converter 64 video signal / subframe correlator 65 Selector 66 Selective reset generation circuit TSF subfield TR reset period TA address period TS sustain period TRP In-plane electrode writing period TRO counter electrode writing period

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takayuki Shimizu             3-2-1 Sakado, Takatsu-ku, Kawasaki City, Kanagawa Prefecture               Fujitsu Hitachi Plasma Display Stock Association             In-house (72) Inventor Tomokatsu Kishi             3-2-1 Sakado, Takatsu-ku, Kawasaki City, Kanagawa Prefecture               Fujitsu Hitachi Plasma Display Stock Association             In-house F-term (reference) 5C080 AA05 BB05 CC03 DD01 EE29                       FF12 GG12 GG17 HH05 HH06                       JJ02 JJ03 JJ04 JJ06

Claims (5)

[Claims] 1. An address electrode group having a stripe arrangement and a plurality of first address electrodes which are orthogonal to the address electrode group, the plurality of address electrodes provided corresponding to at least three phosphor layers having different emission colors. A driving method of a plasma display panel having a first electrode group consisting of one electrode, wherein one frame is divided into n subframes (n is a natural number of 2 or more) and at least one subframe In the reset period, the same voltage is applied to each of the plurality of first electrodes, and the same voltage is applied to the address electrode regardless of the emission color, and at most (n−
1) A plasma display panel, wherein the same voltage is applied to the plurality of first electrodes and a voltage corresponding to the emission color is applied to the address electrodes during a reset period of one subframe. Driving method. 2. The plasma display panel is a three-electrode type plasma display panel further having a second electrode group composed of a plurality of second electrodes respectively parallel to the plurality of first electrodes. Claim 1
7. A method for driving a plasma display panel according to [4]. 3. In the reset period of at most (n−1) subframes, the discharge start voltage according to the emission color between the address electrode and the first electrode is adjusted according to the discharge start voltage. The driving method of the plasma display panel according to claim 2, wherein a voltage is applied to each of the first electrode and the address electrode. 4. The discharge start voltage for the first emission color is the second
The discharge start voltage in the second emission color is smaller than the discharge start voltage in the third emission color, and at most (n-1) subframes are reset. In the period, the first voltage is applied to the first address electrode provided corresponding to the phosphor layer of the first emission color, and the first address electrode is provided corresponding to the phosphor layer of the second emission color. A second voltage is applied to the second address electrode, a third voltage is applied to a third address electrode provided corresponding to the phosphor layer of the third emission color, and the first voltage is applied to the third address electrode. The method of driving a plasma display panel according to claim 3, wherein the voltage is a positive voltage and the second and third voltages are ground levels. 5. An address electrode group having a stripe arrangement and a plurality of first address electrodes which are orthogonal to the address electrode group by a plurality of address electrodes provided corresponding to at least three phosphor layers having different emission colors. A plasma display device having a first electrode group consisting of one electrode, wherein one frame is divided into n (n is a natural number of 2 or more) subframes and at least one subframe is reset in a reset period. Then, the address electrodes are simultaneously driven with the same voltage regardless of the emission color, and at most (n−
1) A control circuit for simultaneously driving the address electrodes provided corresponding to the phosphor layers of the same emission color with a voltage according to the emission color during a reset period of one subframe Plasma display device.