JP2004072019A - Semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a semiconductor package provided with a pattern for high frequency signals and a grounding pattern disposed near the pattern for high frequency signals. <P>SOLUTION: The semiconductor package includes a pattern 1 for high frequency signals, electrically connected to a terminal of a semiconductor device. The pattern 1 for high frequency signals, and an external connection pattern corresponding to it are connected together by a castellation part 13 at the side surface of the package. Thus, the package structure can be miniaturized more than the case wherein the connection is carried out through a via. Further, impedance adjustment is facilitated by providing a GND via 11 in the periphery of the castellation part 13. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a high-frequency signal pattern and a grounding pattern arranged close to the pattern.
[0002]
[Prior art]
FIG. 16 is a plan view of a conventional semiconductor package, and FIG. 17 is an enlarged view of a portion A in FIG. Referring to the drawing, a semiconductor package has a portion for mounting a semiconductor element at a central portion thereof, and has a pattern inside thereof electrically connected to terminals of the semiconductor element.
[0003]
As a pattern electrically connected to the terminal of the semiconductor element, one high-frequency signal (SIG) wire bonding pattern 1 and two ground (GND) wire bonding patterns 3a arranged close to the high-frequency signal pattern , 3b. The SIG wire bonding pattern 1 is electrically connected to the SIG lead 7. The GND wire bonding patterns 3a and 3b are electrically connected to the GND leads 5.
[0004]
FIG. 18 is a diagram showing a structure of the portion A in FIG. 16 as viewed from the back surface. FIG. 19 is a diagram showing a cross section taken along line XX 'of the portion A in FIG.
[0005]
Referring to the figure, an SIG via 31 is provided inside a semiconductor package to achieve conduction between SIG wire bonding pattern 1 and SIG lead 7. Thus, the SIG wire bonding pattern 1 is electrically connected to the SIG lead 7 via the SIG via 31 and the SIG lead bonding conductor pattern 15.
[0006]
Further, the GND wire bonding patterns 3 a and 3 b are connected to the GND lead bonding conductor pattern 9 via the GND via 11. Then, the GND lead 5 is connected to the GND lead bonding conductor pattern 9. Further, a plurality of GND vias 11 are provided, and are configured to surround the SIG via 31.
[0007]
There is also a GND pattern 17 in the package inner layer, which is connected to the GND via 11.
[0008]
[Problems to be solved by the invention]
As shown in FIGS. 16 to 19, in a semiconductor circuit package in which bonding metal leads (SIG lead 7 and GND lead 5) to the external substrate are bonded to the back surface of the package, wire bonding in the package is performed from the package back surface layer. As described above, a method of conducting with the conductive pattern layer is generally a method using a conductive via. Adjustment of the characteristic impedance is usually performed by disposing the GND via 11 around the SIG via 31.
[0009]
In the future, it is considered that miniaturization of semiconductor packages will be required more and more. However, when the above-described structure of the semiconductor package in the related art is adopted, there is a problem that miniaturization is limited. For example, Japanese Patent Application Laid-Open No. 4-336702 discloses the structure of the semiconductor package as described above. FIG. 3 and the 0015 paragraph of this publication disclose a technique of providing a plurality of grounding vias around a signal via to form a coaxial structure. However, since a space for providing the via is required, a small size is required. It is disadvantageous for conversion.
[0010]
The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor package that can be reduced in size.
[0011]
Another object of the present invention is to provide a semiconductor package that can easily adjust characteristic impedance.
[0012]
[Means for Solving the Problems]
According to an aspect of the present invention, there is provided a semiconductor package including a semiconductor mounting portion and a pattern electrically connected to a terminal of a semiconductor element. ) Pattern, a ground (GND) pattern arranged close to the high-frequency signal pattern, and an external connection pattern on the package side surface or the package back surface. The high-frequency signal pattern and the corresponding external connection pattern The ground pattern and the corresponding external connection pattern are connected by a via through a castellation portion on the side surface of the package.
[0013]
According to the present invention, high-frequency signal patterns can be connected by castellations instead of vias, so that the structure of a semiconductor package can be reduced in size. Further, if a ground via is provided around the castellation, it becomes possible to maintain a coaxial structure centered on the castellation.
[0014]
Preferably, the semiconductor package is configured such that grounding patterns are formed on both sides of the high-frequency signal pattern.
[0015]
As described above, by forming the grounding pattern on both sides of the high-frequency signal pattern, the adjustment of the characteristic impedance is further facilitated.
[0016]
Preferably, the semiconductor package further includes a castellation on the side surface of the package for connecting the ground pattern and the corresponding external connection pattern.
[0017]
As described above, by providing the castellations for grounding next to the castellations connecting the high-frequency signal lines, the adjustment of the characteristic impedance is further facilitated.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
FIGS. 1 to 4 are views showing the structure of a semiconductor package according to the first embodiment of the present invention, and correspond to FIGS. 16 to 19.
[0019]
Referring to the drawings, the difference between the structure of the semiconductor package of the present embodiment and the structure of the semiconductor package of the prior art is that, in the present embodiment, the conduction between the package back layer and the SIG wire bonding pattern 1 in the package is different. Is performed by the SIG castellation 13 installed on the side surface of the package. Thus, the SIG castellations 13 and the GND vias 11 for adjusting characteristic impedance can be installed in a smaller area than the structure shown in the related art. This makes it possible to reduce the size of the entire semiconductor package.
[0020]
That is, as compared with the case where the SIG via 31 (FIG. 19) is used, the distance from the GND via 11 to the outer periphery of the package is changed from W1 in FIG. 19 to W2 in FIG. 4 by using the SIG castellation 13 (FIG. 4). It is possible to reduce it.
[0021]
Further, since a via for grounding is provided around the castellation, it is possible to maintain the coaxial structure.
[0022]
In the present embodiment, the GND leads 5 are provided on both sides of the SIG lead 7. However, the GND leads may not be provided on both sides of the SIG lead, and the GND lead may be provided on only one side. .
[0023]
[Second embodiment]
FIGS. 5 to 8 are views showing the structure of the semiconductor package according to the second embodiment of the present invention, corresponding to FIGS. 1 to 4 in the first embodiment. The difference between the semiconductor package of the present embodiment and that of the first embodiment is that the SIG lead 7 is bent into an L-shape to be joined to the side surface of the package (to the portion where the SIG castellation 13 exists). It is.
[0024]
[Third Embodiment]
9 to 12 are views showing the structure of the semiconductor package according to the third embodiment of the present invention, and correspond to FIGS. 1 to 4 in the first embodiment.
[0025]
In the present embodiment, not only the GND via 11 but also GND castellations 21a and 21b are used to connect the GND wire bonding patterns 3a and 3b and the GND conductor pattern 9. Thus, by providing the GND castellations 21a and 21b on the side surface of the package, the adjustment of the characteristic impedance is further facilitated.
[0026]
Further, in the present embodiment, the GND lead 5 is joined to the side surface of the package by bending the L-shaped lead in the same manner as the SIG lead 7. Note that the SIG lead 7 and the GND lead 5 may be joined to the back surface of the package as in the first embodiment.
[0027]
[Fourth Embodiment]
FIG. 13 is a diagram illustrating a structure of a semiconductor package according to a fourth embodiment of the present invention, and is a diagram corresponding to FIG. 1 according to the first embodiment.
[0028]
As shown in the figure, in this embodiment, three GND leads 5 and two SIG leads 7a and 7b protrude from the semiconductor package. That is, the invention of the present application can be implemented as long as the number of pairs of signal lines and GND leads (or GND leads, signal lines, and GND leads) is one or more.
[0029]
FIGS. 14 and 15 are diagrams showing a structure in which a semiconductor package is constituted by two SIG leads and three GND leads. FIG. 14 corresponds to the first embodiment of the present invention, and FIG. 15 corresponds to the second embodiment.
[0030]
Referring to the drawing, the semiconductor package is constituted by the following members.
-Dielectric part (53) which is a package body
.Cavities (61) in which semiconductor integrated circuits are mounted
.Leads for bonding external substrates (5, 7a, 7b)
The leads include a signal line (SIG) lead (5) and a GND lead (7a, 7b). Both ends of the SIG lead (7a, 7b), or a GND lead (5) for adjusting characteristic impedance, are located adjacent to one of the two ends. 5) is installed. Also, a plurality of leads (57) other than the SIG lead and the GND lead are provided. For example, it is a lead for power supply.
[0031]
・ Conductor pattern portions (9, 15) for joining the external substrate joining lead portion and the package with a joining material such as solder.
The SIG lead bonding conductor pattern portion (15) is provided on the back surface of the package or on the side surface of the package, and FIG. 14 shows an example in which it is provided on the back surface of the package. FIG. 15 shows an example of installation on the side of the package.
[0032]
・ Conductor pattern layer (1) to be electrically connected to the semiconductor integrated circuit mounted in the package by wire bonding, flip chip connection, etc.
-The castellation part (13) installed on the side of the package
The castellation portion electrically connects the conductor pattern portion (15) and the conductor pattern layer (1) directly or via a conductor layer provided inside the package. Further, as shown in FIG. 15, the castellation portion (13) can also be a lead bonding pattern for connecting an external substrate of the conductor pattern layer (1).
[0033]
.Hole (55) for inserting an optical fiber from outside the package
A metal or dielectric member (a member for inserting an optical fiber or the like) having a hole connected to the hole (55) (51)
A metal or dielectric member (59) joined to the top of the package by brazing or the like, and a metal or dielectric cover for airtightly sealing the inside of the package is joined to the surface by brazing or the like (59)
・ GND conductive pattern layer (17) installed in package inner layer
A via portion (11) for electrically connecting the GND conductor pattern portion (9) on the back surface of the package to the dielectric member (59);
The via portion is provided around the signal line castellation so as to adjust the characteristic impedance of the signal line castellation portion.
[0034]
[Effects in Embodiment]
As described above, in the embodiment of the present invention, the metal lead for conduction with the external substrate is connected to the back surface or the side surface of the package, and the lead bonding portion and the wire bonding layer conductor pattern provided inside the package are connected. Electrical continuity is achieved by castellation on the side of the package. Thus, the package can be reduced in size, and the characteristic impedance can be easily adjusted because the GND leads are provided on both sides of the external connection leads for the signal lines or only on one side.
[0035]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor package according to a first embodiment of the present invention.
FIG. 2 is an enlarged view of a portion A in FIG.
FIG. 3 is a diagram showing a structure of a back surface of a portion A in FIG. 1;
FIG. 4 is a sectional view taken along line XX ′ of a portion A in FIG.
FIG. 5 is a plan view of a semiconductor package according to a second embodiment of the present invention.
FIG. 6 is an enlarged view of a portion A in FIG. 5;
FIG. 7 is a diagram showing a structure of a back surface of a portion A in FIG. 5;
FIG. 8 is a sectional view taken along the line XX ′ of the portion A in FIG. 5;
FIG. 9 is a plan view of a semiconductor package according to a third embodiment of the present invention.
FIG. 10 is an enlarged view of a portion A in FIG. 9;
FIG. 11 is a diagram showing a structure of a back surface of a portion A in FIG. 9;
FIG. 12 is a sectional view taken along the line XX ′ of the portion A in FIG. 9;
FIG. 13 is a plan view of a semiconductor package according to a fourth embodiment of the present invention.
FIG. 14 is a diagram showing a first structure of a semiconductor package having a plurality of SIG leads.
FIG. 15 is a diagram showing a second structure of a semiconductor package having a plurality of SIG leads.
FIG. 16 is a plan view of a conventional semiconductor package.
FIG. 17 is an enlarged view of a portion A in FIG. 16;
FIG. 18 is a diagram showing a structure of a back surface of a portion A in FIG. 16;
19 is a sectional view taken along the line XX 'of the portion A in FIG.
[Explanation of symbols]
1 SIG wire bonding pattern, 3a, 3b GND wire bonding pattern, 5 GND lead, 7 SIG lead, 9 GND lead bonding conductor pattern, 11 GND via, 13 SIG castellation, 15 SIG lead bonding conductor pattern, 17 package Inner layer GND pattern, 21a, 21b GND castellation.

Claims (3)

A semiconductor package comprising a semiconductor mounting portion and a pattern electrically connected to terminals of the semiconductor element,
A pattern for high frequency signals,
A grounding pattern arranged close to the high-frequency signal pattern,
With external connection patterns on the package side or package back,
The high-frequency signal pattern and the corresponding external connection pattern are connected by a castellation portion on a package side surface,
A semiconductor package, wherein the ground pattern and the corresponding external connection pattern are connected by a via. The semiconductor package according to claim 1, wherein the ground pattern is formed on both sides of the high-frequency signal pattern. 3. The semiconductor package according to claim 1, further comprising a castellation on a side surface of the package that connects the ground pattern and the corresponding external connection pattern. 4.

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