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JP2004047715A - Semiconductor connection relay member and semiconductor device - Google Patents

Semiconductor connection relay member and semiconductor device Download PDF

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Publication number
JP2004047715A
JP2004047715A JP2002202831A JP2002202831A JP2004047715A JP 2004047715 A JP2004047715 A JP 2004047715A JP 2002202831 A JP2002202831 A JP 2002202831A JP 2002202831 A JP2002202831 A JP 2002202831A JP 2004047715 A JP2004047715 A JP 2004047715A
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Prior art keywords
semiconductor chip
semiconductor
substrate
chip
pad
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JP2002202831A
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Japanese (ja)
Inventor
Koichi Ikeda
池田　功一
Hiroshi Miyagawa
宮川　弘志
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2002202831A priority Critical patent/JP2004047715A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor connection relay member which can be widely used further than the past regardless of the size of a semiconductor chip, and to provide a semiconductor device using the same. <P>SOLUTION: In an MCP 100, a universal spacer chip piece 50 is structured in such a way that it does not overhangs the upper surface of a semiconductor chip 120 when it is arranged on the semiconductor chip 120, and that lengths of bonding wires 114 and bonding wires 134 are the minimum, respectively, based on a distance between pads 112 and 132. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、基板と半導体チップとの電気的な接続を中継する半導体接続中継部材及び当該半導体接続中継部材を利用した半導体装置に関する。
【０００２】
【従来の技術】
近年、高速化、小型化、多機能化の要求に応えるべく、複数の半導体チップを１つのパッケージに集約させたマルチチップパッケージ（ＭＣＰ：Ｍｕｌｔｉ　Ｃｈｉｐ　Ｐａｃｋａｇｅ）が実用化されている。特に、基板上に複数の半導体チップを積層させた３次元パッケージは、パッケージの占有面積を小さくすることが可能であるため、広く実用化されている。ＭＣＰに用いられる複数の半導体チップは、メモリチップ同士、メモリチップとロジックチップの組み合わせ等、用途に応じて様々な組み合わせがある。
【０００３】
図１は、２つの半導体チップを積層させた従来のＭＣＰの斜視図である。同図に示すＭＣＰ５００は、基板５０１と、当該基板５０１上に積層される２つの半導体チップ５０２、５０３により構成される。ＭＣＰ５００において、回路構成上の理由により、基板５０１と上部の半導体チップ５０３との電気的な接続が必要となる場合がある。このような場合、ボンディングワイヤ５１０により、基板５０１に形成されたパッド５０５と、半導体チップ５０３に形成されたパッド５０６とが接続される。
【０００４】
しかし、上述したように、ボンディングワイヤ５１０により、基板５０１に形成されたパッド５０５と、半導体チップ５０３に形成されたパッド５０６とが接続される場合、当該ボンディングワイヤ５１０の配線長が長くなる。このため、ボンディングワイヤ５１０が半導体チップ５０２や半導体チップ５０３の縁に接触したり、ボンディングワイヤ５１０同士が接触してショートの原因になりやすいという問題があった。
【０００５】
特に、半導体チップ５０３が小さかったり、パッド５０６が半導体チップ５０３の中央部に形成されていたり、あるいは、パッド５０５が半導体チップ５０３から離れた位置に形成されている場合には、ボンディングワイヤ５１０の配線長が極端に長くなるため、半導体チップ５０２の縁への接触や、ボンディングワイヤ５１０同士の接触が起こりやすい。このため、ボンディングワイヤの配線長をできるだけ短くすることが要求される。
【０００６】
このような要求に応じた従来技術としては、特開平１１−２２４９１４号公報において開示された「半導体接続用基板」がある。当該公報における半導体接続用基板は、半導体チップの搭載面から所定距離離れた外周に、外側に延在する電極を設け、当該電極の一端と半導体チップ上のパッドとをボンディングワイヤにより接続する（当該公報の図２参照）。
【０００７】
【発明が解決しようとする課題】
しかしながら、上述した特開平１１−２２４９１４号公報における半導体接続用基板の構成では、半導体チップが小さい場合、ボンディングワイヤの配線長を短くして半導体チップへの接触やボンディングワイヤ同士の接触を防止するためには、電極の延在方向を長くする必要がある。即ち、当該半導体接続用基板は、搭載する半導体チップの大きさに応じて、電極の延在方向の長さを変えなければならない。換言すれば、当該半導体接続用基板は、半導体チップの大きさに応じて複数の種類を用意しなければならず、汎用的な利用を行うことができない。
【０００８】
本発明は、上記問題点を解決するものであり、その目的は、半導体チップの大きさに関わらず、従来よりも汎用的な利用が可能な半導体接続中継部材及び当該半導体接続中継部材を適用した半導体装置を提供することにある。
【０００９】
【課題を解決するための手段】
上記の目的を達成するため、本発明の半導体接続中継部材は、請求項１に記載されるように、半導体装置を構成する基板と半導体チップとの電気的な接続を中継する半導体接続中継部材において、板状部材と、前記板状部材の中心近傍から外縁に向けて放射状に延在する複数の配線パターンと、を備え、前記基板と前記半導体チップとの間、及び又は、前記半導体チップ上に、所定部分が配置されて、前記基板上のパッドに接続される導電性ワイヤと、前記半導体チップ上のパッドに接続される導電性ワイヤとを前記配線パターンを介して接続することを特徴とする。
【００１０】
また、本発明の半導体装置は、請求項２に記載されるように、基板と、前記基板上に配置される第１の半導体チップと、板状部材と、前記板状部材の中心近傍から外縁に向けて放射状に延在する複数の配線パターンとを備える半導体接続中継部材の所定部分により構成され、前記基板と前記第１の半導体チップの間、及び又は、前記第１の半導体チップ上に配置される中継手段と、前記基板上のパッドと、前記配線パターンとを接続する第１の導電性ワイヤと、前記第１の半導体チップ上のパッドと、前記第１の導電性ワイヤが接続された配線パターンとを接続する第２の導電性ワイヤとを備えることを特徴とする。
【００１１】
また、本発明は請求項３に記載されるように、請求項２に記載の半導体装置において、前記基板と前記第１の半導体チップの間に配置される第２の半導体チップを備え、前記中継手段は、前記第１の半導体チップと前記第２の半導体チップの間に配置されることを特徴とする。
【００１２】
また、本発明は請求項４に記載されるように、請求項２又は３に記載の半導体装置において、前記中継手段は、前記基板上のパッドの配置間隔と前記第１の半導体チップ上のパッドの配置間隔とに基づいて、前記第１及び第２の導電性ワイヤの配線長が最短になるように配置されることを特徴とする。
【００１３】
本発明によれば、複数の配線パターンを板状部材の中心近傍から外縁に向けて放射状に延在させた半導体接続中継部材を構成し、この半導体接続中継部材の所定部分を、基板と半導体チップとの間、及び又は、半導体チップ上に配置し、基板上のパッドに接続される導電性ワイヤと、半導体チップ上のパッドに接続される導電性ワイヤとを配線パターンを介して接続しており、半導体チップの大きさに応じて、適宜、半導体接続中継部材の所定部分を選択して用いることにより、導電性ワイヤの配線長を短くすることが可能となる。換言すれば、本発明の半導体接続中継部材は、搭載される半導体チップの大きさについての制限が従来よりも小さく、汎用的な利用が可能となる。
【００１４】
【発明の実施の形態】
本発明の半導体接続中継部材は、板状部材と、この板状部材の中心近傍から外縁に向けて放射状に延在する複数の配線パターンとを備え、基板と、基板上に配置される半導体チップとを含む半導体装置において、基板と半導体チップとの間、及び又は、半導体チップ上に配置されて、基板上のパッドに接続される導電性ワイヤと、半導体チップ上のパッドに接続される導電性ワイヤとを配線パターンを介して接続することを特徴とする。
【００１５】
以下、本発明の実施の形態を、図面に基づいて説明する。
【００１６】
図２は、本実施形態における半導体接続中継部材としてのユニバーサルスペーサチップの構成例を示す上面図である。同図に示すユニバーサルスペーサチップ１は、板状部材１０と、複数の配線パターン２０とにより構成される。
【００１７】
板状部材１０の材質は、例えばシリコン、ポリカーボネード（ＰＣＢ）等である。一方、各配線パターン２０の材質は、例えばアルミニウム、銅等である。各配線パターン２０は、板状部材１０の中央近傍から外縁に向けて延在する。また、各配線パターン２０は、ワイヤボンディングが可能な幅及び間隔を有する。
【００１８】
ユニバーサルスペーサチップ１は、基板と半導体チップとの間、及び又は、半導体チップ上に配置される際に、適当な大きさに切り出されて用いられる。以下、このユニバーサルスペーサチップ１を利用した半導体装置であるＭＣＰの例（第１及び第２実施例）について説明する。
【００１９】
まず、第１実施例について説明する。図３は、第１実施例におけるＭＣＰの構成例を示す斜視図、図４は、側面図である。これらの図に示すＭＣＰ１００は、基板１１０、当該基板１１０上に積層される半導体チップ１２０、中継手段としてのユニバーサルスペーサチップ片５０、半導体チップ１３０、パッド１１２及び１３２、ボンディングワイヤ１１４及び１３４を備える。
【００２０】
ユニバーサルスペーサチップ片５０は、半導体チップ１３０の大きさに応じて、ユニバーサルスペーサチップ１から切り出され、半導体チップ１３０上に配置される。
【００２１】
図５は、第１実施例におけるユニバーサルスペーサチップ片５０の上面図である。同図に示すユニバーサルスペーサチップ片５０は、半導体チップ１２０上に配置したときに、当該半導体チップ１２０の上面からはみ出さないように、且つ、パッド１１２及び１３２の間隔に基づいて、ボンディングワイヤ１１４及びボンディングワイヤ１３４の配線長が最小となるように、ユニバーサルスペーサチップ１の周囲を切り取って構成される。
【００２２】
再び、図３及び図４に戻って説明する。基板１１０上に形成された各パッド１１２には、ボンディングワイヤ１１４が接続されている。また、最上層の半導体チップ１３０上の外縁近傍に形成された各パッド１３２には、ボンディングワイヤ１３４が接続されている。
【００２３】
ユニバーサルスペーサチップ片５０の１本の配線パターン２０に着目すると、この配線パターン２０は、基板１１０上に形成されたパッド１１２に接続されているボンディングワイヤ１１４の一端を接続するとともに、半導体チップ１３０に形成されたパッド１３２に接続されているボンディングワイヤ１３４の一端を接続している。これにより、基板１１０と半導体チップ１３０とが電気的に接続される。
【００２４】
このように、ユニバーサルスペーサチップ片５０は、基板１１０と半導体チップ１３０との電気的な接続を中継する役割を果している。このため、１本のボンディングワイヤにより基板１１０上のパッド１１２と、半導体チップ１３０上のパッド１３２とを直接に接続する場合におけるボンディングワイヤの配線長よりも、接続に用いられる各ボンディングワイヤの配線長が短くなり、ボンディングワイヤが安定するため、半導体チップ１２０及び１３０の縁に接触したり、ワイヤボンディング同士が接触して、ショートすることを防止することができる。
【００２５】
次に、第２実施例について説明する。図６は、第２実施例におけるＭＣＰの構成例を示す斜視図、図７は、側面図である。これらの図に示すＭＣＰ２００は、基板２１０、当該基板２１０上に積層される半導体チップ２２０及び２３０、半導体チップ２３０上に配置される中継手段としてのユニバーサルスペーサチップ片６０、パッド２１２及び２３２、ボンディングワイヤ２１４及び２３４を備える。
【００２６】
ユニバーサルスペーサチップ片６０は、半導体チップ２２０の大きさに応じて、ユニバーサルスペーサチップ１から切り出され、半導体チップ２２０上に配置される。
【００２７】
図８は、第２実施例におけるユニバーサルスペーサチップ片６０の上面図である。同図に示すユニバーサルスペーサチップ片６０は、半導体チップ２３０上に配置したときに、パッド２３２が露出するように、且つ、パッド２１２及び２３２の間隔に基づいて、ボンディングワイヤ２１４及びボンディングワイヤ２３４の配線長が最小となるように、ユニバーサルスペーサチップ１の１辺に沿って切り出されて構成される。
【００２８】
再び、図６及び図７に戻って説明する。第１実施例と同様、基板２１０上に形成された各パッド２１２には、ボンディングワイヤ２１４が接続されている。また、最上層の半導体チップ２３０上の中央近傍に形成された各パッド２３２には、ボンディングワイヤ１３４が接続されている。
【００２９】
ユニバーサルスペーサチップ片６０の１本の配線パターン２０に着目すると、この配線パターン２０は、基板２１０上に形成されたパッド２１２に接続されているボンディングワイヤ２１４の一端を接続するとともに、半導体チップ２３０に形成されたパッド２３２に接続されているボンディングワイヤ２３４の一端を接続している。これにより、基板２１０と半導体チップ２３０とが電気的に接続される。
【００３０】
なお、本実施例において、第１実施例と異なり、ユニバーサルスペーサチップ片６０が最上層の半導体チップ２２０上に配置されるのは、以下の理由による。即ち、半導体チップ２３０の中央近傍にパッド２３２が形成されているため、第１実施例と同様に、半導体チップ２２０と半導体チップ２３０の間にユニバーサルスペーサチップ片６０を配置したのでは、ボンディングワイヤ２３４の配線長が長くなり、半導体チップ２３０の縁に接触したり、ボンディングワイヤ２３４同士が接触する可能性が高い。一方、半導体チップ２２０は、半導体チップ２３０より若干大きいだけであるため、ボンディングワイヤ２１４が半導体チップ２３０の外縁近傍上の配線パターン２０に接続されれば、当該ボンディングワイヤ２１４が半導体チップ２２０に接触する可能性は小さい。そこで、本実施例では、ユニバーサルスペーサチップ片６０を最上層の半導体チップ２２０上に配置する構成とした。
【００３１】
このように、ユニバーサルスペーサチップ片６０は、基板２１０と半導体チップ２３０との電気的な接続を中継する役割を果している。このため、第１実施例と同様、１本のボンディングワイヤにより基板２１０上のパッド２１２と、半導体チップ２３０上のパッド２３２とを直接に接続する場合におけるボンディングワイヤの配線長よりも、接続に用いられる各ボンディングワイヤの配線長が短くなり、ボンディングワイヤが安定するため、半導体チップ２２０及び２３０の縁に接触したり、ワイヤボンディング同士が接触して、ショートすることを防止することができる。
【００３２】
以上、説明したように、第１実施例では、同図に示すユニバーサルスペーサチップ片５０は、半導体チップ１２０上に配置したときに、当該半導体チップ１２０の上面からはみ出さないように、且つ、パッド１１２及び１３４の間隔に基づいて、ボンディングワイヤ１１４及びボンディングワイヤ１３４の配線長が最小となるように、ユニバーサルスペーサチップ１の周囲を切り取って構成され、半導体チップ１２０上に配置される。一方、第２実施例では、ユニバーサルスペーサチップ片６０は、半導体チップ２３０上に配置したときに、パッド２３２が露出するように、且つ、パッド２１２及び２３２の間隔に基づいて、ボンディングワイヤ２１４及びボンディングワイヤ２３４の配線長が最小となるように、ユニバーサルスペーサチップ１の１辺に沿って切り出されて構成され、半導体チップ２３０上に配置される。
【００３３】
即ち、ユニバーサルスペーサチップ片５０及び６０は、何れもユニバーサルスペーサチップ１の所定部分を切り出して構成されている。従って、ユニバーサルスペーサチップ１は、従来よりも、搭載される半導体チップの大きさのついての制限が小さく、汎用的な利用が可能となる。
【００３４】
なお、上述した実施形態では、第１実施例において、半導体チップ１２０と半導体チップ１３０の間にユニバーサルスペーサチップ片５０を配置する場合を説明し、第２実施例において、最上層の半導体チップ２３０上にユニバーサルスペーサチップ片６０を配置する場合を説明したが、これら実施例を組み合わせて、２つの半導体チップの間にユニバーサルスペーサチップ片を配置するとともに、最上層の半導体チップ上にユニバーサルスペーサチップ片を配置するようにしてもよい。
【００３５】
【発明の効果】
上述の如く、本発明によれば、複数の配線パターンを板状部材の中心近傍から外縁に向けて放射状に延在させた半導体接続中継部材を構成し、この半導体接続中継部材の所定部分を、基板と半導体チップとの間、及び又は、半導体チップ上に配置し、基板上のパッドに接続される導電性ワイヤと、半導体チップ上のパッドに接続される導電性ワイヤとを配線パターンを介して接続しており、半導体チップの大きさに応じて、適宜、半導体接続中継部材の所定部分を選択して用いることにより、導電性ワイヤの配線長を短くすることが可能となる。換言すれば、本発明の半導体接続中継部材は、搭載される半導体チップの大きさについての制限が従来よりも小さく、汎用的な利用が可能となる。
【図面の簡単な説明】
【図１】従来のＭＣＰの斜視図である。
【図２】ユニバーサルスペーサチップの上面図である。
【図３】第１実施例におけるＭＣＰの斜視図である。
【図４】第１実施例におけるＭＣＰの側面図である。
【図５】第１実施例におけるユニバーサルスペーサチップ片の上面図である。
【図６】第２実施例におけるＭＣＰの斜視図である。
【図７】第２実施例におけるＭＣＰの側面図である。
【図８】第２実施例におけるユニバーサルスペーサチップ片の上面図である。
【符号の説明】
１　ユニバーサルスペーサチップ
１０　板状部材
２０　導電性プレート線
５０、６０　ユニバーサルスペーサチップ片
１１０、２１０　基板
１１２、１３２、２１２、２３２　パッド
１１４、１３４、２１４、２３４　ボンディングワイヤ
１２０、１３０、２２０、２４０　半導体チップ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor connection relay member that relays electrical connection between a substrate and a semiconductor chip, and a semiconductor device using the semiconductor connection relay member.
[0002]
[Prior art]
In recent years, a multi-chip package (MCP: Multi Chip Package) in which a plurality of semiconductor chips are integrated into a single package has been put into practical use in order to meet demands for speeding up, downsizing, and multifunctional functions. In particular, a three-dimensional package in which a plurality of semiconductor chips are stacked on a substrate has been widely put into practical use because the area occupied by the package can be reduced. There are various combinations of semiconductor chips used in the MCP depending on applications, such as memory chips and combinations of memory chips and logic chips.
[0003]
FIG. 1 is a perspective view of a conventional MCP in which two semiconductor chips are stacked. The MCP 500 shown in the figure includes a substrate 501 and two semiconductor chips 502 and 503 stacked on the substrate 501. In the MCP 500, there may be a case where electrical connection between the substrate 501 and the upper semiconductor chip 503 is required for reasons of circuit configuration. In such a case, the pad 505 formed on the substrate 501 and the pad 506 formed on the semiconductor chip 503 are connected by the bonding wire 510.
[0004]
However, as described above, when the pad 505 formed on the substrate 501 and the pad 506 formed on the semiconductor chip 503 are connected by the bonding wire 510, the wiring length of the bonding wire 510 becomes long. For this reason, there existed a problem that the bonding wire 510 contacted the edge of the semiconductor chip 502 or the semiconductor chip 503, or the bonding wires 510 contacted each other easily to cause a short circuit.
[0005]
In particular, when the semiconductor chip 503 is small, the pad 506 is formed at the center of the semiconductor chip 503, or the pad 505 is formed at a position away from the semiconductor chip 503, the bonding wire 510 is wired. Since the length becomes extremely long, contact with the edge of the semiconductor chip 502 and contact between the bonding wires 510 are likely to occur. For this reason, it is required to make the wiring length of the bonding wire as short as possible.
[0006]
As a prior art meeting such a requirement, there is a “semiconductor connection substrate” disclosed in Japanese Patent Laid-Open No. 11-224914. The semiconductor connection substrate in this publication is provided with an electrode extending outwardly on the outer periphery at a predetermined distance from the mounting surface of the semiconductor chip, and one end of the electrode and a pad on the semiconductor chip are connected by a bonding wire ( See FIG. 2 of the publication).
[0007]
[Problems to be solved by the invention]
However, in the configuration of the substrate for semiconductor connection in the above-mentioned Japanese Patent Application Laid-Open No. 11-224914, when the semiconductor chip is small, the wiring length of the bonding wire is shortened to prevent contact with the semiconductor chip or contact between the bonding wires. Therefore, it is necessary to lengthen the extending direction of the electrode. That is, in the semiconductor connection substrate, the length in the extending direction of the electrodes must be changed according to the size of the semiconductor chip to be mounted. In other words, the semiconductor connection substrate must be prepared in a plurality of types according to the size of the semiconductor chip, and cannot be used for general purposes.
[0008]
The present invention solves the above-mentioned problems, and the object thereof is to apply a semiconductor connection relay member that can be used more versatilely than before and the semiconductor connection relay member regardless of the size of the semiconductor chip. It is to provide a semiconductor device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor connection relay member according to the present invention is a semiconductor connection relay member that relays an electrical connection between a substrate and a semiconductor chip constituting a semiconductor device. A plate-like member and a plurality of wiring patterns extending radially from the vicinity of the center of the plate-like member toward the outer edge, and between the substrate and the semiconductor chip and / or on the semiconductor chip. The conductive wire connected to the pad on the substrate and the conductive wire connected to the pad on the semiconductor chip are connected to each other through the wiring pattern. .
[0010]
According to a second aspect of the present invention, a semiconductor device includes a substrate, a first semiconductor chip disposed on the substrate, a plate member, and an outer edge from the vicinity of the center of the plate member. And a plurality of wiring patterns extending radially toward the semiconductor device, the semiconductor connection relay member including a predetermined portion, and disposed between the substrate and the first semiconductor chip and / or on the first semiconductor chip. Connected, the first conductive wire connecting the pad on the substrate and the wiring pattern, the pad on the first semiconductor chip, and the first conductive wire are connected. And a second conductive wire connecting the wiring pattern.
[0011]
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the second semiconductor chip is disposed between the substrate and the first semiconductor chip, and the relay is provided. The means is arranged between the first semiconductor chip and the second semiconductor chip.
[0012]
According to a fourth aspect of the present invention, in the semiconductor device according to the second or third aspect, the relay means includes an arrangement interval of pads on the substrate and a pad on the first semiconductor chip. Based on the arrangement interval, the first and second conductive wires are arranged so as to have the shortest wiring length.
[0013]
According to the present invention, a semiconductor connection relay member is formed by extending a plurality of wiring patterns radially from the vicinity of the center of the plate-shaped member toward the outer edge, and a predetermined portion of the semiconductor connection relay member is formed on a substrate and a semiconductor chip. And / or a conductive wire that is disposed on a semiconductor chip and connected to a pad on a substrate and a conductive wire that is connected to a pad on the semiconductor chip via a wiring pattern The length of the conductive wire can be shortened by appropriately selecting and using a predetermined portion of the semiconductor connection relay member according to the size of the semiconductor chip. In other words, the semiconductor connection relay member of the present invention has a smaller limit on the size of a semiconductor chip to be mounted than before, and can be used for general purposes.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor connection relay member of the present invention includes a board and a semiconductor chip disposed on the board, including a plate-like member and a plurality of wiring patterns extending radially from the vicinity of the center of the plate-like member toward the outer edge. A conductive wire disposed between and / or on the semiconductor chip and connected to a pad on the substrate; and a conductive wire connected to a pad on the semiconductor chip. The wire is connected via a wiring pattern.
[0015]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
FIG. 2 is a top view showing a configuration example of a universal spacer chip as a semiconductor connection relay member in the present embodiment. A universal spacer chip 1 shown in FIG. 1 includes a plate-like member 10 and a plurality of wiring patterns 20.
[0017]
The material of the plate-like member 10 is, for example, silicon, polycarbonate (PCB) or the like. On the other hand, the material of each wiring pattern 20 is, for example, aluminum or copper. Each wiring pattern 20 extends from the vicinity of the center of the plate-shaped member 10 toward the outer edge. In addition, each wiring pattern 20 has a width and an interval that allow wire bonding.
[0018]
When the universal spacer chip 1 is disposed between the substrate and the semiconductor chip and / or on the semiconductor chip, the universal spacer chip 1 is cut into an appropriate size and used. Hereinafter, examples (first and second embodiments) of an MCP that is a semiconductor device using the universal spacer chip 1 will be described.
[0019]
First, the first embodiment will be described. FIG. 3 is a perspective view showing a configuration example of the MCP in the first embodiment, and FIG. 4 is a side view. The MCP 100 shown in these drawings includes a substrate 110, a semiconductor chip 120 stacked on the substrate 110, a universal spacer chip piece 50 as a relay means, a semiconductor chip 130, pads 112 and 132, and bonding wires 114 and 134.
[0020]
The universal spacer chip piece 50 is cut out from the universal spacer chip 1 according to the size of the semiconductor chip 130 and disposed on the semiconductor chip 130.
[0021]
FIG. 5 is a top view of the universal spacer chip piece 50 in the first embodiment. When the universal spacer chip piece 50 shown in the figure is arranged on the semiconductor chip 120, the universal spacer chip piece 50 does not protrude from the upper surface of the semiconductor chip 120, and based on the distance between the pads 112 and 132, The universal spacer chip 1 is cut out so that the wiring length of the bonding wire 134 is minimized.
[0022]
Again, it returns and demonstrates to FIG.3 and FIG.4. A bonding wire 114 is connected to each pad 112 formed on the substrate 110. A bonding wire 134 is connected to each pad 132 formed near the outer edge on the uppermost semiconductor chip 130.
[0023]
When attention is paid to one wiring pattern 20 of the universal spacer chip piece 50, the wiring pattern 20 connects one end of the bonding wire 114 connected to the pad 112 formed on the substrate 110 and also connects to the semiconductor chip 130. One end of the bonding wire 134 connected to the formed pad 132 is connected. Thereby, the substrate 110 and the semiconductor chip 130 are electrically connected.
[0024]
Thus, the universal spacer chip piece 50 plays a role of relaying the electrical connection between the substrate 110 and the semiconductor chip 130. For this reason, the wiring length of each bonding wire used for the connection is longer than the wiring length of the bonding wire when the pad 112 on the substrate 110 and the pad 132 on the semiconductor chip 130 are directly connected by one bonding wire. Since the bonding wire is stabilized, it is possible to prevent short circuit due to contact with the edges of the semiconductor chips 120 and 130 or contact between the wire bonds.
[0025]
Next, a second embodiment will be described. FIG. 6 is a perspective view showing a configuration example of the MCP in the second embodiment, and FIG. 7 is a side view. The MCP 200 shown in these drawings includes a substrate 210, semiconductor chips 220 and 230 stacked on the substrate 210, universal spacer chip pieces 60 as relay means disposed on the semiconductor chip 230, pads 212 and 232, bonding wires. 214 and 234.
[0026]
The universal spacer chip piece 60 is cut out from the universal spacer chip 1 according to the size of the semiconductor chip 220 and disposed on the semiconductor chip 220.
[0027]
FIG. 8 is a top view of the universal spacer chip piece 60 in the second embodiment. The universal spacer chip piece 60 shown in the figure is arranged so that the pads 232 are exposed when arranged on the semiconductor chip 230, and the bonding wires 214 and the bonding wires 234 are wired based on the distance between the pads 212 and 232. It is cut out along one side of the universal spacer chip 1 so as to minimize the length.
[0028]
Again, it returns and demonstrates to FIG.6 and FIG.7. As in the first embodiment, a bonding wire 214 is connected to each pad 212 formed on the substrate 210. A bonding wire 134 is connected to each pad 232 formed near the center on the uppermost semiconductor chip 230.
[0029]
When attention is paid to one wiring pattern 20 of the universal spacer chip piece 60, the wiring pattern 20 connects one end of the bonding wire 214 connected to the pad 212 formed on the substrate 210, and is connected to the semiconductor chip 230. One end of the bonding wire 234 connected to the formed pad 232 is connected. Thereby, the substrate 210 and the semiconductor chip 230 are electrically connected.
[0030]
In the present embodiment, unlike the first embodiment, the universal spacer chip piece 60 is disposed on the uppermost semiconductor chip 220 for the following reason. That is, since the pad 232 is formed near the center of the semiconductor chip 230, the bonding wire 234 is formed when the universal spacer chip piece 60 is disposed between the semiconductor chip 220 and the semiconductor chip 230 as in the first embodiment. Therefore, there is a high possibility that the wiring length of the semiconductor chip 230 contacts with the edge of the semiconductor chip 230 or the bonding wires 234 contact each other. On the other hand, since the semiconductor chip 220 is only slightly larger than the semiconductor chip 230, if the bonding wire 214 is connected to the wiring pattern 20 near the outer edge of the semiconductor chip 230, the bonding wire 214 comes into contact with the semiconductor chip 220. The possibility is small. Therefore, in this embodiment, the universal spacer chip piece 60 is arranged on the uppermost semiconductor chip 220.
[0031]
As described above, the universal spacer chip piece 60 plays a role of relaying electrical connection between the substrate 210 and the semiconductor chip 230. Therefore, as in the first embodiment, it is used for connection rather than the wire length of the bonding wire when the pad 212 on the substrate 210 and the pad 232 on the semiconductor chip 230 are directly connected by one bonding wire. Since the length of each bonding wire to be formed is shortened and the bonding wire is stabilized, it is possible to prevent the semiconductor chips 220 and 230 from coming into contact with each other and the wire bondings from being brought into contact with each other to be short-circuited.
[0032]
As described above, in the first embodiment, when the universal spacer chip piece 50 shown in the figure is disposed on the semiconductor chip 120, the universal spacer chip piece 50 does not protrude from the upper surface of the semiconductor chip 120, and the pad Based on the distance between 112 and 134, the periphery of the universal spacer chip 1 is cut out and disposed on the semiconductor chip 120 so that the wiring length of the bonding wire 114 and the bonding wire 134 is minimized. On the other hand, in the second embodiment, the universal spacer chip piece 60 is disposed on the semiconductor chip 230 so that the pad 232 is exposed and the bonding wire 214 and the bonding wire are bonded based on the distance between the pads 212 and 232. The wire 234 is cut and configured along one side of the universal spacer chip 1 so as to minimize the wiring length of the wire 234 and is disposed on the semiconductor chip 230.
[0033]
That is, each of the universal spacer chip pieces 50 and 60 is configured by cutting out a predetermined portion of the universal spacer chip 1. Therefore, the universal spacer chip 1 has a smaller limit on the size of a semiconductor chip to be mounted than before, and can be used for general purposes.
[0034]
In the above-described embodiment, the case where the universal spacer chip piece 50 is disposed between the semiconductor chip 120 and the semiconductor chip 130 in the first example will be described. In the second example, the top layer of the semiconductor chip 230 is described. In the above description, the universal spacer chip piece 60 is disposed. However, by combining these embodiments, the universal spacer chip piece is disposed between two semiconductor chips, and the universal spacer chip piece is disposed on the uppermost semiconductor chip. It may be arranged.
[0035]
【The invention's effect】
As described above, according to the present invention, a semiconductor connection relay member is formed by extending a plurality of wiring patterns radially from the vicinity of the center of the plate-shaped member toward the outer edge, and a predetermined portion of the semiconductor connection relay member is Between the substrate and the semiconductor chip and / or on the semiconductor chip, the conductive wire connected to the pad on the substrate and the conductive wire connected to the pad on the semiconductor chip via the wiring pattern It is possible to shorten the wiring length of the conductive wire by appropriately selecting and using a predetermined portion of the semiconductor connection relay member according to the size of the semiconductor chip. In other words, the semiconductor connection relay member of the present invention has a smaller limit on the size of a semiconductor chip to be mounted than before, and can be used for general purposes.
[Brief description of the drawings]
FIG. 1 is a perspective view of a conventional MCP.
FIG. 2 is a top view of a universal spacer chip.
FIG. 3 is a perspective view of the MCP in the first embodiment.
FIG. 4 is a side view of the MCP in the first embodiment.
FIG. 5 is a top view of a universal spacer chip piece according to the first embodiment.
FIG. 6 is a perspective view of the MCP in the second embodiment.
FIG. 7 is a side view of the MCP in the second embodiment.
FIG. 8 is a top view of a universal spacer chip piece according to a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Universal spacer chip 10 Plate-shaped member 20 Conductive plate wire 50, 60 Universal spacer chip piece 110, 210 Board | substrate 112,132,212,232 Pad 114,134,214,234 Bonding wire 120,130,220,240 Semiconductor chip

Claims (4)

半導体装置を構成する基板と半導体チップとの電気的な接続を中継する半導体接続中継部材において、
板状部材と、
前記板状部材の中心近傍から外縁に向けて放射状に延在する複数の配線パターンと、
を備え、前記基板と前記半導体チップとの間、及び又は、前記半導体チップ上に、所定部分が配置されて、前記基板上のパッドに接続される導電性ワイヤと、前記半導体チップ上のパッドに接続される導電性ワイヤとを前記配線パターンを介して接続することを特徴とする半導体接続中継部材。In the semiconductor connection relay member that relays the electrical connection between the substrate and the semiconductor chip constituting the semiconductor device,
A plate-like member;
A plurality of wiring patterns extending radially from the vicinity of the center of the plate-shaped member toward the outer edge;
A conductive wire disposed between the substrate and the semiconductor chip and / or on the semiconductor chip and connected to a pad on the substrate; and a pad on the semiconductor chip. A semiconductor connection relay member, wherein a conductive wire to be connected is connected via the wiring pattern. 基板と、
前記基板上に配置される第１の半導体チップと、
板状部材と、前記板状部材の中心近傍から外縁に向けて放射状に延在する複数の配線パターンとを備える半導体接続中継部材の所定部分により構成され、前記基板と前記第１の半導体チップの間、及び又は、前記第１の半導体チップ上に配置される中継手段と、
前記基板上のパッドと、前記配線パターンとを接続する第１の導電性ワイヤと、
前記第１の半導体チップ上のパッドと、前記第１の導電性ワイヤが接続された配線パターンとを接続する第２の導電性ワイヤと、
を備えることを特徴とする半導体装置。A substrate,
A first semiconductor chip disposed on the substrate;
A plate-like member, and a plurality of wiring patterns extending radially from the vicinity of the center of the plate-like member toward the outer edge. The semiconductor connection relay member includes a predetermined portion, and the substrate and the first semiconductor chip And / or relay means arranged on the first semiconductor chip,
A first conductive wire connecting the pad on the substrate and the wiring pattern;
A second conductive wire connecting the pad on the first semiconductor chip and the wiring pattern to which the first conductive wire is connected;
A semiconductor device comprising: 請求項２に記載の半導体装置において、
前記基板と前記第１の半導体チップの間に配置される第２の半導体チップを備え、
前記中継手段は、前記第１の半導体チップと前記第２の半導体チップの間に配置されることを特徴とする半導体装置。The semiconductor device according to claim 2,
A second semiconductor chip disposed between the substrate and the first semiconductor chip;
The semiconductor device according to claim 1, wherein the relay means is disposed between the first semiconductor chip and the second semiconductor chip. 請求項２又は３に記載の半導体装置において、
前記中継手段は、前記基板上のパッドの配置間隔と前記第１の半導体チップ上のパッドの配置間隔とに基づいて、前記第１及び第２の導電性ワイヤの配線長が最短になるように配置されることを特徴とする半導体装置。The semiconductor device according to claim 2 or 3,
The relay means makes the wiring length of the first and second conductive wires the shortest based on the arrangement interval of the pads on the substrate and the arrangement interval of the pads on the first semiconductor chip. A semiconductor device which is arranged.
JP2002202831A 2002-07-11 2002-07-11 Semiconductor connection relay member and semiconductor device Pending JP2004047715A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729502B1 (en) 2005-11-01 2007-06-15 매그나칩 반도체 유한회사 Carrier for multi chip package, multi chip package and method for fabricating the same
US7667331B2 (en) 2007-07-09 2010-02-23 Samsung Electronics Co., Ltd. Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
US7786601B2 (en) 2005-08-12 2010-08-31 Samsung Electronics Co., Ltd Semiconductor chip and multi-chip package
US7888806B2 (en) 2007-07-23 2011-02-15 Samsung Electronics Co., Ltd. Electrical connections for multichip modules
US7972902B2 (en) 2007-07-23 2011-07-05 Samsung Electronics Co., Ltd. Method of manufacturing a wafer including providing electrical conductors isolated from circuitry
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7786601B2 (en) 2005-08-12 2010-08-31 Samsung Electronics Co., Ltd Semiconductor chip and multi-chip package
KR100729502B1 (en) 2005-11-01 2007-06-15 매그나칩 반도체 유한회사 Carrier for multi chip package, multi chip package and method for fabricating the same
US7667331B2 (en) 2007-07-09 2010-02-23 Samsung Electronics Co., Ltd. Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
US7888806B2 (en) 2007-07-23 2011-02-15 Samsung Electronics Co., Ltd. Electrical connections for multichip modules
US7972902B2 (en) 2007-07-23 2011-07-05 Samsung Electronics Co., Ltd. Method of manufacturing a wafer including providing electrical conductors isolated from circuitry
US8207617B2 (en) 2007-07-23 2012-06-26 Samsung Electronics Co., Ltd. Electrical connections for multichip modules
US8217519B2 (en) 2007-07-23 2012-07-10 Samsung Electronics Co., Ltd. Electrical connection for multichip modules
US8742593B2 (en) 2007-07-23 2014-06-03 Samsung Electronics Co., Ltd. Electrical connection for multichip modules
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package

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