JP2003242047A - Hardware system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hardware system in which memory data in a FIFO memory can be easily checked from the outside. <P>SOLUTION: This hardware system provided with a CPU 1 connected to each data bus 5, a first function block 2, a second function block 3, and the FIFO memory 4 connected between the first function block 2 and the second function block 3, storing the data from the first function block 2 in a memory unit once, and transmitting the data from a memory unit 204 to the second function block 3. The FIFO memory 4 has a test window 203 capable of writing/ reading the memory data for the entire area in the memory unit 204, the test window 203 is connected to the data bus 5, and the CPU 1 can write/read the data of the test window 203 via the data bus 5. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hardware system provided with a FIFO memory, and more particularly, it is capable of externally confirming the situation in the FIFO memory.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a hardware system including a conventional FIFO (first-in first-out, first-in first-out) memory.
FIG. 5 is a block diagram showing the configuration of the FIFO memory of the hardware system shown in FIG. In the figure, 10
Reference numeral 1 is a CPU, and 102 is a first functional block, which is, for example, a storage unit.

Reference numeral 104 denotes a FIFO memory connected to the first functional block 102, which is the first functional block 10.
It has a memory unit 403 for temporarily storing data from No. 2. A second functional block 103 is connected to the FIFO memory 104, and stores the data stored in the first functional block 102 in the memory unit 403 of the FIFO memory 104.
Is a conversion unit that obtains from the above, converts it into desired data, and outputs it.

A data bus 105 includes a CPU 101, a first functional block 102 and a second functional block 10.
3 are connected to each other. 106 is a first FIFO bus for connecting between the first functional block 102 and the FIFO memory 104, and 107 is the FIFO memory 10.
4 is a second FIFO bus for connecting between the second functional block 103 and the second functional block 103; 401 is a light window provided in the FIFO memory 104;
This is for writing one data from 02 to the memory unit 403. A read window 402 provided in the FIFO memory 104 is for reading one data in the memory unit 403 to the second functional block 103.

Next, the operation of the conventional hardware system configured as described above will be described. First, various data is stored in the first functional block 102 in advance. Then, the CPU 101 sends the necessary data to the first
The second functional block 103 is instructed to transmit from the second functional block 102. Next, the first functional block 1
02 indicates the required data one by one in the first FI
It transmits to the write window 401 of the FIFO memory 104 via the FO bus 106.

Then, this one data is written from the write window 401 to the memory unit 403 and temporarily stored in the memory unit 403. Next, the memory data stored in the memory unit 403 is read out from the FIFO memory 104 on a first-in first-out basis, that is, the oldest one data written by the write window 401 is read into the read window 402.

Next, one piece of data read by the read window 402 is input to the second functional block 103 via the second FIFO bus 107. Then the second
In the functional block 103, desired processing is performed on the input data, for example, data transmission to a communication line is performed. In this way, by transmitting and receiving data between the first functional block 102 and the second functional block 103 via the FIFO memory 104, the first functional block 102 and the second functional block 102
The difference in the data processing speed from the functional block 103 is absorbed.

[0008]

In the conventional hardware system, the CPU cannot directly read the data in the FIFO memory or write any test data in the FIFO memory. There is a problem that it is not possible to easily confirm the contents of the above, and to test each block connected to the FIFO memory.

The present invention has been made to solve the above problems, and hardware capable of writing / reading data to / from an arbitrary area of memory data in a FIFO memory and easily performing a test. The purpose is to realize the system.

[0010]

[Means for Solving the Problems] Claim 1 according to the present invention
The hardware system is connected between the CPU, the first functional block, the second functional block, and the first functional block and the second functional block respectively connected to the data bus, and the first functional block In a birdware system including a FIFO memory that temporarily stores data from the block in the memory unit and then transmits the data from the memory unit to the second functional block, the FIFO memory writes the memory data in an arbitrary area in the memory unit. / Has a test input / output unit which can be read, and the test input / output unit is connected to a data bus, and the CPU can write / read data of the test input / output unit via the data bus.

The hardware system according to a second aspect of the present invention is the hardware system according to the first aspect, wherein the test input / output section can write / read all areas in the memory section.

A hardware system according to a third aspect of the present invention is the hardware system according to the first or second aspect, wherein the second functional block has an erroneous data detection means.
The CPU sets arbitrary test data in the test input / output unit, confirms whether or not the erroneous detection unit has detected the test data, and determines whether the erroneous detection unit is normal or abnormal.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing a configuration of a hardware system including a FIFO memory according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing a configuration of a FIFO memory of the hardware system shown in FIG. In the figure, 1 is a CPU, and 2 is a first functional block, which comprises, for example, a storage unit.

Reference numeral 4 is a FIFO memory connected to the first functional block 2 and has a memory section 204 for temporarily storing the data from the first functional block 2. 3 is this F
The second functional block connected to the IFO memory 4 is a conversion unit that obtains the data stored in the first functional block 2 from the memory unit 204 of the FIFO memory 4, converts the data into desired data, and outputs the data. .

A data bus 5 is connected to the CPU 1, the first functional block 2 and the second functional block 3, respectively. 6 is a first FIFO bus for connecting between the first functional block 2 and the FIFO memory 4, and 7 is a second FIFO bus for connecting between the FIFO memory 4 and the second functional block 3. A bus, 201, is a write window provided in the FIFO memory 4, and is for writing one data from the first functional block 2 to the memory unit 204. A read window 202 provided in the FIFO memory 4 is for reading one data in the memory unit 204 to the second functional block 3.

Reference numeral 203 denotes a test window as a test input / output unit provided in the FIFO memory 4, which is configured so that memory data for all areas in the memory unit 204 can be written / read. Reference numeral 8 denotes a test bus for connecting the test window 203 and the data bus 5, which can operate independently of the first FIFO bus 6 and the second FIFO bus 7. As a result, the CPU 1 can write / read test window data from the data bus 5 via the test bus 8.

Next, the first embodiment configured as described above
The operation of the hardware system will be described. First, as in the conventional case, various data is stored in the first functional block 2 in advance. Then, the CPU 1 instructs the first functional block 2 to transmit the necessary data to the second functional block 3. Next, the first functional block 2 outputs the required data specified one by one,
It is transmitted to the write window 201 of the FIFO memory 4 via the first FIFO bus 6.

Then, this data is stored in the light window 2
01 is written to the memory unit 204, and once the memory unit 2
It is stored in 04. Next, the data stored in the memory unit 204 is read in first-in first-out from the FIFO memory 4, that is, the oldest one data written by the write window 201 is read to the read window 202.

Next, the data read in the read window 202 is input to the second functional block 3 via the second FIFO bus 7. Next, the second functional block 3 converts the input data into desired data and outputs it to the data bus 5. In this way, the first functional block 2
FIFO for transmitting and receiving data between the second functional block 3 and
By performing the processing via the memory 4, the difference in data processing speed between the first functional block 2 and the second functional block 3 is absorbed.

The memory section 20 of the FIFO memory 4
When the writing / reading to 4 is not performed in the write window 201 and the read window 202, the memory data for all areas in the memory unit 204 is read to the test window 203. Then, the CPU 1 transmits the test window 2 via the data bus 5 and the test bus 8.
By reading the contents of 03, the transition of data transmission / reception between the first functional block 2 and the second functional block 3 can be confirmed.

As a result, the arrangement of data in the FIFO memory 4 can be confirmed, data omission, data duplication, etc. can be confirmed, and it can be confirmed whether the first functional block 2 is operating correctly. Further, the CPU 1 writes the test data in the test window 203 via the test bus 8. Next, the test data is read from the test window 203 to the memory unit 204. Then, the test data is transmitted from the memory unit 204 to the second functional block 3 by a normal operation, and the second functional block 3 can be tested.

Since the hardware system of the first embodiment configured as described above is provided with the test window, the contents of the memory data in the memory portion of the FIFO memory can be easily confirmed from the outside. 1
It is possible to easily confirm the transition of the data transmission / reception between the function block and the second function block. Further, since the test data can be easily written in the memory unit from the outside, the second functional block can be easily tested.

In the first embodiment described above, the test window can be written / read over the entire area of the memory portion of the FIFO memory. However, the present invention is not limited to this, and the FIFO memory required by the CPU is not limited to this. It goes without saying that the memory data may be configured to be written / read only at an arbitrary address.

Embodiment 2. 3 is a block diagram showing a configuration of a hardware system according to a second embodiment of the present invention,
FIG. 4 is a block diagram showing the structure of the FIFO memory shown in FIG. In the figure, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 303 denotes a bit error detection unit as an error detection means provided in the first functional block 3.

Next, the operation of the hardware system of the second embodiment configured as described above will be described. Here, since the normal operation is the same as that in the first embodiment, the bit error detection unit 303 in the second functional block 3
Only the test will be explained. First, in the test of the bit error detection unit 303 of the second functional block 3, it is necessary to intentionally input test data including a bit error.

Therefore, the memory unit 20 of the FIFO memory 4
When the write / read to 4 is not performed in the write window 201 and the read window 202, the CP
U1 writes the test data including the bit error to the desired address in the test window 203 via the data bus 5 and the test bus 8 and sets it. Then, the test data is read from the test window 203 onto the normal data in the memory unit 204.

Next, the test data is transmitted from the memory section 204 to the second functional block 3 by a normal operation,
The CPU 1 confirms whether or not the test data is detected by the bit error detector 303 of the second function block 3. Then, it is possible to perform a test by determining whether the bit error detection unit 303 detects that the test data is normal, and when the bit error detection unit 303 does not detect the test data, is abnormal.

The hardware system according to the second embodiment configured as described above writes the test data in the test window and reads the test data from the memory section, thereby the bit error detection section of the second functional block. The normality / abnormality of can be easily determined.

[0029]

As described above, according to claim 1 of the present invention, the CPU, the first functional block, the second functional block, the first functional block and the second functional block which are respectively connected to the data bus. FI connected to the second functional block after the data is temporarily stored in the memory unit from the first functional block and is then transmitted from the memory unit to the second functional block.
In a birdware system equipped with FO memory, F
The IFO memory has a test input / output unit capable of writing / reading memory data in an arbitrary area in the memory unit,
The test input / output unit is connected to the data bus, and the CP
Since U can write / read the data of the test input / output unit via the data bus, it is necessary to provide a hardware system capable of confirming the data in the FIFO memory and writing the test data in the FIFO memory. Is possible.

According to a second aspect of the present invention, in the first aspect, since the test input / output unit can write / read all areas in the memory section, all data in the FIFO memory is confirmed. It is possible to provide a hardware system capable of doing so.

According to a third aspect of the present invention, in the first or second aspect, when the second functional block has an erroneous data detection means, the CPU has an optional test input / output section. Since the normality / abnormality of the false detection means is determined by setting the test data and checking whether or not the false detection means has detected the test data, it is possible to easily confirm the normality / abnormality of the false detection means. It becomes possible to provide a hardware system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a hardware system according to a first embodiment of the present invention.

FIG. 2 is a FIF of the hardware system shown in FIG.
It is a block diagram which shows the structure of O memory.

FIG. 3 is a block diagram showing a configuration of a hardware system according to a second embodiment of the present invention.

FIG. 4 is a FIF of the hardware system shown in FIG.
It is a block diagram which shows the structure of O memory.

FIG. 5 is a block diagram showing a configuration of a conventional hardware system.

FIG. 6 is a FIF of the hardware system shown in FIG.
It is a block diagram which shows the structure of O memory.

[Explanation of symbols]

1 CPU, 2 1st functional block, 3 2nd functional block, 4 FIFO memory, 5 data bus, 8
Test bus, 201 write window, 202 read window, 203 test window, 204 memory section, 303-bit error detection section.

Claims (3)

[Claims] 1. CPs each connected to a data bus
U, a first functional block, a second functional block, and is connected between the first functional block and the second functional block, and the data from the first functional block is temporarily stored in the memory unit. In a birdware system including a FIFO memory that transmits the data from the memory unit to the second functional block after the test, the FIFO memory is a test device capable of writing / reading memory data in an arbitrary area in the memory unit. A hardware having an input / output unit, the test input / output unit being connected to the data bus, and the CPU being capable of writing / reading data of the test input / output unit via the data bus. Wear system. 2. The hardware system according to claim 1, wherein the test input / output unit can write / read all areas in the memory unit. 3. When the second functional block has a data erroneous detection unit, the CPU sets arbitrary test data in the test input / output unit, and whether or not the erroneous detection unit detects the test data. The hardware system according to claim 1 or 2, wherein whether the erroneous detection means is normal or abnormal is determined by confirming whether or not.