JP2003123465A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric storage device capable of taking out signals of a potential sufficient for reading a data from micronized capacitors (memory cells), whose power consumption at the time of writing data can be reduced, and in which an area for all chips can be reduced. SOLUTION: An amplifier circuit unit 110 is connected between a bit line B101 and a memory unit 106 having a plurality of ferroelectric capacitors C101-C104 connected across a plurality of independent plate lines P101-P104 each and a common node electrode E101. This amplifier circuit unit 110 amplifies data signals (sense signals) of the common node electrode E101 and transmits them to the bit line B101 at the time of reading data from each of the capacitors C101-C104, and charges and discharges the common node electrode E101 with the power source voltage Vcc according to the signals received from the bit kine B101 at the time of writing the data to each of the capacitors C101-C104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device having a large number of ferroelectric capacitors for data storage.

[0002]

2. Description of the Related Art FeRAM (Ferroelectric Random Access Memor) using a ferroelectric material as a semiconductor memory device
y) is attracting attention as a user-friendly device that has both high-speed access and non-volatile memory, and its capacity is expected to increase. FeRAM is small in size, low in power consumption, and resistant to shocks, and is promising as a recording medium for audio and images if the bit unit price is reduced due to the increase in capacity.

The cell structure and operation of a ferroelectric memory device, which is currently the mainstream, is described in US Pat. S
It was proposed by Hefffield and others. FIG. 8 shows an example of the circuit configuration of a ferroelectric memory device realized based on this proposal.

This ferroelectric memory device stores data of 1 bit by complementary writing of data to two ferroelectric capacitors forming a pair through a transistor, and a pair of word lines. Word line decoder / driver 10 to which W1 and W2 are connected, and each word line W
1, W2, a pair of plate lines P1, which are arranged in parallel with each other.
Plate line decoder / driver 12 to which P2 is connected
And each word line W1, W2 and each plate line P1, P
2 is connected to a pair of bit lines B1 and B2 having an orthogonal arrangement relationship with each other, and the word lines W1 and W.
2 and a differential sense amplifier 16 in which a pair of bit lines B3 and B4 in an orthogonal arrangement relation are connected to each plate line P1 and P2, and further, a pair of ferroelectric capacitors C1, C2, C3 and C4, respectively. , C5, C6, C7, C8,
It is configured to include transistors T1 to T8 that perform switching control when writing data to these capacitors C1 to C8.

Each capacitor C1 to C8 and transistor T
The connection relationship with 1 to T8 is as follows. That is, one end of the capacitor C1 is connected to the plate line P1 and the other end thereof is connected to the bit line B1 via the source-drain of the transistor T1 whose gate end is connected to the word line W1. The capacitor C2 has one end connected to the plate line P1 and the other end connected to the bit line B2 via the source-drain of the transistor T2 whose gate end is connected to the word line W1. Similarly, the other pair of capacitors C3 and C4 has one end connected to the plate line P2 and the other end connected to the bit lines B1 and B2 through the transistors T3 and T4.
C6 has one end connected to the plate line P1 and the other end connected to the bit lines B3 and B4 through the transistors T5 and T6. The pair of capacitors C7 and C8 also has one end connected to the plate line P2.
The other end through the transistors T7 and T8 to the bit line B
3 and B4.

In such a structure, the operation will be described focusing on, for example, the pair of capacitors C1 and C2. A transistor operating voltage is applied to the word line W1 under the control of the word line decoder / driver 10, and the plate line P1 is under control of the plate line decoder / driver 12.
Supply pulse voltage to. By this control, complementary data is read out from the pair of capacitors C1 and C2 to the pair of bit lines B1 and B2 via the transistors T1 and T2, respectively, and thus the data is sensed by the differential sense amplifier 14. can get.

That is, both capacitors C1 and C2 are polarized in different directions depending on the stored data, and are "1".
The polarization of the capacitor storing the data of
It is inverted by a plate pulse of 1. On the other hand, the polarization state of the capacitor storing the data of "0" does not change. As a result, larger charges are discharged on the "1" side, and the bit line potential becomes higher.

As a technique for further miniaturizing memory cells and promoting large capacity, Japanese Patent Laid-Open No. 09-121032 proposes a cross-point type memory device (ferroelectric memory device). FIG. 9 shows an example of the circuit configuration of this cross point type memory device.

This cross-point type memory device includes a word line decoder / driver 2 to which a word line W11 is connected.
0, a plate line decoder / driver 22 to which a plurality of plate lines P11 to P14 having a parallel arrangement relation with the word line W11 are connected, and a pair of orthogonal arrangement relations to the word line W11 and each plate line P11 to P14. A memory including a differential sense amplifier 24 to which bit lines B11 and B12 are connected, and a plurality of ferroelectric capacitors C11 to C14 connected between the plate lines P11 to P14 and the common node electrode E11. A plurality of ferroelectric capacitors C15 to C1 connected between the unit 26, the plate lines P11 to P14 and the common node electrode E12.
8 and a common node electrode E1
1 and the bit line B11, the source-drain end is connected and the gate end is connected to the word line W11. The transistor (FET) T11 is connected between the common node electrode E12 and the bit line B12. Of the transistor (F
ET) T12.

In such a structure, the capacitors C11 to C18 in the memory units 26 and 28 are provided.
Respectively store separate data and are controlled by the plate line decoder / driver 22 via independent plate lines P11 to P14. For example, a transistor operating voltage is applied to the word line W11 under the control of the word line decoder / driver 20, and the plate line decoder / driver 2
The potential of the plate lines P12 to P14 is set to 0 by the control of 2.
When a pulse voltage is applied to the plate line P11 in a state of being fixed to V, the pair of capacitors C11 and C15 causes the common node electrodes E11 and E12 and the transistors T11 and T11.
The electric charges are discharged to the pair of bit lines B11 and B12 via 12. Data can be read by sensing the potential difference caused by this with the differential sense amplifier 24. In such a cross-point type storage device, since one transistor T11 is shared by the plurality of capacitors C11 to C14, the number of elements per bit is effectively reduced, which is effective in cost reduction.

[0011]

By the way, in the conventional ferroelectric memory device, when the chip cost is taken into consideration, not only the cell area is simply reduced but also more cells or memory units are connected to the bit lines. Then, it is advantageous to reduce the number of peripheral circuits such as sense amplifiers and decoders. However, in this case, the bit line capacitance becomes large and the sense signal becomes small. That is, there is a problem that a signal having a sufficient potential for reading data cannot be taken out.

Particularly, in a ferroelectric memory device, for example, DR
Even if the ferroelectric film is made thin like an insulating film in AM (Dynamic Random Access Memory), the signal charge does not increase. Therefore, as the cell becomes finer, the signal charge becomes smaller, and the number of cells connected to the bit line needs to be reduced. For this reason, when the number of cells is increased, the number of bit lines must be increased, and the peripheral circuits such as sense amplifiers and decoders are also increased accordingly. As a result, the area of the peripheral circuits is increased and the chip area is increased. There is a problem that it gets bigger.

Further, when writing data in the ferroelectric memory device, the potential of the bit line must be made to have a full amplitude, but there is a problem that the power consumption becomes large if the bit line capacitance is large. Since the ferroelectric memory device is designed to always rewrite after reading, the current consumption required for charging / discharging the bit line is directly connected to the operating current. Therefore, also in this respect, the number of cells connected to the bit line cannot be increased in order to prevent the bit line capacitance from increasing.

The present invention has been made in view of such problems, and an object thereof is to be able to take out a signal having a sufficient potential for reading data from a miniaturized capacitor (memory cell), and at the time of writing data. Another object of the present invention is to provide a ferroelectric memory device capable of reducing the power consumption of the device and further reducing the area of the entire chip.

[0015]

A ferroelectric memory device of the present invention is connected between a plurality of independent plate lines and a common node electrode, and is independently connected according to voltage application to the plate lines. A bit line is connected between a memory unit having a plurality of ferroelectric capacitors for controlling data storage and a bit line, and amplifies a data signal of a common node electrode when reading data from the capacitor. And an amplifier circuit unit that charges and discharges the common node electrode in accordance with a signal transmitted from the bit line when writing data to the capacitor.

In this ferroelectric memory device, since the data signal of the common node electrode is amplified and transmitted to the bit line when the data is read from the capacitor, the data signal transmitted from the capacitor to the common node electrode is a minute signal. Even if there is, a signal capable of sufficiently determining "1" or "0" of data is transmitted to the bit line. Also, since the common node electrode is charged / discharged in the amplifier circuit unit according to the signal received from the bit line when writing data to the capacitor, the common node electrode is charged / discharged only in the amplifier circuit unit, and the bit line itself is As with the common node electrode, it is not necessary to charge and discharge.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows a circuit configuration of a cross-point type memory device according to the embodiment of FIG.

This cross-point type memory device is for a word line decoder driver 100 to which a word line W101 is connected, and a plate line to which a plurality of plate lines P101 to P104 in parallel arrangement with the word line W101 are connected. A decoder / driver 102 and a sense amplifier 104 to which a word line W101 and a bit line B101 in an orthogonal arrangement relationship with the plate lines P101 to P104 are connected.
And a memory unit 106 including a plurality of ferroelectric capacitors C101 to C104 connected between the plate lines P101 to P104 and the common node electrode E101, and further includes a bit line B101 and a word line W101.
Between the NMOS-type transistor TN0 connected to the common node electrode E101 and the common node electrode E101 connected to the memory unit 106, which is a characteristic element of the present invention.
It is configured by connecting.

The amplifier circuit unit 110 includes three NMOs.
It comprises S-type transistors TN1 to TN3 and three PMOS type transistors TP1 to TP3.
The NMOS transistor TN2 and the PMOS transistor TP1 form a pair to form an inverter circuit 112, and charge and discharge the common node electrode E101 connected to the output terminal of the inverter circuit 112. The NMOS type transistor and the PMOS type transistor may be simply abbreviated as transistors in the following description.

Further, an NMOS type transistor TN1 is connected between one transistor TN2 constituting the inverter circuit 112 and the ground, and the other transistor Tn.
A PMOS transistor T is connected between P1 and the Vcc power supply.
P3 is connected. A write control line WC is connected to the gate terminal of the transistor TN1 and the transistor TP
The write control line WC is connected to the gate end of the transistor 3 through the inverter circuit 114, and both the transistors TN are connected.
1, TP3 plays a role of a switch for activating or inactivating the inverter circuit 112.

That is, the write control line WC is connected to the word line decoder / driver 100, and signals are supplied from the driver 100 via the write control line WC to the gate ends of both transistors TN1 and TP3 complementarily. If the signal level is "H", the inverter circuit 112 is in the active state, and if the signal level is "L", it is in the inactive state.

The transistor TN3 connected between the memory unit 106 and the ground serves as a reset switch, and the reset line R connected to the gate terminal thereof.
By setting the signal level of the common node electrode E1 to "H"
The potential of 01 is dropped to 0V. The reset line R is connected to the word line decoder / driver 100, and the signal level of the reset line R is controlled by the driver 100.

The transistor TP2 connected between the Vcc power supply and the transistor TN0 is a sense transistor, and receives the potential of the common node electrode E101 at the gate end thereof, so that a sense signal is transmitted to the bit line B101 via the transistor TN0. introduce. Further, the gate ends (input ends) 116 of the transistors TN2 and TP1 forming the inverter circuit 112 are connected between the transistors TP2 and TN0.

The data read and data rewrite operations in the cross-point type memory device having such a configuration will be described with reference to the timing chart shown in FIG.

First, the data read operation will be described. In the initial state at time t1, the signal level of the write control line WC is “L”, and this “L” is supplied to the gate end of the transistor TN1 and the gate end of the transistor TP3 via the inverter circuit 114, so that both The transistors TN1 and TP3 are turned off, and the inverter circuit 112 connected between the transistors TN1 and TP3.
Becomes inactive.

Further, at the same time t1, the signal level of the reset line R is "H", and this "H" is the transistor TN3.
Is supplied to the gate end of the transistor TN3
Is on, the common node electrode E101 is 0
Equalized to V. The signal level of the word line W101 is "L", and this "L" is the transistor TN.
0 is supplied to the gate end of the transistor TN
Since 0 is off, the bit line B101 and the amplifier circuit unit 110 are separated from each other.
Further, the signal levels of the plate lines P101 to P104 are all set to 0V.

At time t2, the signal level of the reset line R is set to "L" to turn off the transistor TN3, which brings the common node electrode E101 into a floating state.

At time t3, for example, the plate line P101
Is selected, and time t3 to t9 is added to the plate line P101.
When a pulse of the power supply voltage Vcc which becomes "H" between is given, the voltage is applied to the ferroelectric capacitor C101,
As shown in FIG. 2, the potential of the common node electrode E101 rises. The degree of this increase becomes large (data becomes “1”) when the capacitor C101 is accompanied by polarization reversal, and becomes small (data becomes “0”) when the capacitor C101 is not reversed.

At time t4, the signal level of the word line W101 becomes "H", so that the transistor TN0
Is turned on, and the bit line B101 and the amplifier circuit unit 110 are turned on.
And connect. At this time, since the voltage of the common node electrode E101 is supplied to the gate end of the transistor TP2, the bit line B101 is charged according to the current flowing through the transistor TP2 in the ON state, and its potential rises as shown in FIG. To start. Here, the degree of increase is "1"
Becomes smaller when reading "0" and becomes larger when reading "0".

At time t5, the sense amplifier 104 connected to the bit line B101 is activated and data "
1 "or" 0 "is judged. When making this judgment,
The sense amplifier 104 performs by comparing the potential of the bit line B101 and the reference potential. This completes the data read operation from the capacitor C101.

Next, the data rewriting operation will be described. At time t6, the bit line B101 changes to data "
If the potential corresponds to 1 ″, the sense amplifier 104
Is discharged to 0V. On the other hand, when the bit line B101 has the potential corresponding to the data “0”,
Sense transistor TP2 or sense amplifier 10
4 is charged to about 1V. However, Vcc = 3V
And The voltage of the bit line B101 is the same as that of the word line W.
Since the signal level of 101 is "H" and the transistor TN0 is in the ON state, it is supplied to the input terminal 116 of the inverter circuit 112.

At time t7, the non-selected plate line P
The potential of 102 to P104 is set to Vcc / 2 (= 1.5V). At this time, the potential of the selected plate line P101 is Vcc (= 3V).

At time t8, the signal level of the write control line WC is set to "H" to activate the inverter circuit 112. The threshold value of the inverter circuit 112 is set to about 0.5V here, and when the data "1" is written by setting the bit line B101 to 0V, the common node electrode E101 becomes the potential of Vcc and the bit line B101. Is set to 1V, the common node electrode E101 is 0V when writing data "0".
It becomes the electric potential of. This allows the capacitor C101 to
When "0" is written, the potential of the common node electrode E101 becomes 0 V, so that there is a negative voltage between both electrodes of the capacitor C101.
Vcc is applied and "0" is written. At this time, the voltage applied to the non-selected capacitors c12 to C14 is −
(Vcc / 2), and the polarization direction is maintained if the coercive electric field is set lower than that.

At time t9, the signal level of the selected plate line P101 is set to "L", that is, the potential is set to 0V. As a result, for example, by setting the bit line B101 to 0 V, the common node electrode E101 becomes the potential of Vcc, the voltage of Vcc is applied to the selection capacitor C101, and "1" is written. At this time, the non-selected capacitors C12 to C1
The voltage applied to 4 is Vcc / 2, and the polarization direction is maintained if the coercive electric field is set lower than that.

At time t10, when the signal level of the word line W101 becomes "L", the transistor TN0 is turned off, and the bit line B101 and the amplifier circuit unit 110 are separated. Further, the signal level of the write control line WC is set to "L", so that the inverter circuit 112 becomes inactive.

Finally, at time t11, the signal level of the reset line R is set to "H" to return the potential of the common node electrode E101 to 0V. Further, the potentials of the non-selected plate lines P102 to P104 are returned to 0V, the bit line B101 is also equalized to 0V, and the data rewriting operation is completed.

Further, in the case of writing data, after performing the above-mentioned data reading operation, the sense amplifier 10
Of the plurality of bit lines connected to No. 4, only the desired bit line may be inverted to "1" or "0" and the above data rewriting operation may be performed.

There is no limitation on the structure of the sense amplifier 104 connected to the bit line B101 and the method of judging data "1" or "0". For example, a differential sense amplifier is used and the pair of bit lines is used. A dummy amplifier circuit unit 120 as shown in FIG. 3 may be attached. In the dummy amplifier circuit unit 120 shown in FIG. 3, the dummy word line W
The NMOS-type transistor TN0a having the gate terminal 101a connected to the transistor TN0 of FIG.
The type transistor TP2a has the same size as the PMOS type transistor TP2 of FIG. 1, and "1" or "" from the memory unit 106 supplied to the gate end of the transistor TP2a shown in FIG.
The intermediate potential Vref of the sense signal of 0 "is supplied. This dummy amplifier circuit unit 110 is a bit line B101a.
When connected to the selected bit line B10a, the rising speed of the bit line B101a becomes an intermediate value between "1" and "0".
It becomes possible to detect and amplify the potential difference with respect to 1.

As described above, according to the cross-point type memory device of the first embodiment, a plurality of ferroelectric substances connected between the plurality of independent plate lines P101 to P104 and the common node electrode E101 are provided. Capacitors C101 to C
Memory unit 106 having 104 and bit line B10
The amplifier circuit unit 110 is connected between the capacitors C1 and C1.
The data signal (sense signal) of the common node electrode E101 is amplified when the data is read from the bit line B101.
And the common node electrode E101 is charged and discharged with the power supply voltage Vcc in accordance with the signal received from the bit line B101 when writing data to the capacitors C101 to C104.

According to this structure, the capacitors C101 to C101.
Even if the data signal transmitted from the C104 to the common node electrode E101 is a very small signal, a signal that can sufficiently determine "1" or "0" of the data is the bit line B1.
01 is transmitted. Therefore, even if the data signal becomes small due to the increase in the bit line capacitance, a signal having a sufficient potential for reading data can be taken out to the bit line B101.

From this, one bit line B101
Since more capacitors can be connected to and the number of peripheral circuits such as sense amplifiers and decoders can be reduced,
The area of the entire chip (the area of the entire crosspoint type memory device) can be reduced.

Further, since the common node electrode E101 is charged / discharged by the power supply voltage Vcc according to the signal received from the bit line B101 when writing data to the capacitors C101 to C104, the common circuit electrode E101 is charged / discharged. Bit line B101
As with the common node electrode E101, it does not have to be charged and discharged. Further, in order to charge / discharge the common node electrode E101, the amplifier circuit unit 110 is removed from the bit line B101.
The voltage of the signal supplied to is required to be lower than the power supply voltage.
For these reasons, it is possible to reduce power consumption when writing data.

(Second Embodiment) FIG. 4 shows a circuit configuration of a cross-point type memory device according to a second embodiment of the present invention. Here, parts corresponding to the respective parts of the first embodiment of FIG. 1 are designated by the same reference numerals, and description thereof will be omitted.

The cross point type memory device of this embodiment is different from the cross point type memory device of the first embodiment in that the amplifier circuit unit 110 is shared by the two memory units 106 and 130. is there. That is, the memory unit 106 and the amplifier circuit unit 1 described above.
An NMOS transistor TN4 is connected between 10 and
Further, the common node electrode E101 and each plate line P10
A memory unit 130 including a plurality of capacitors C111, C112, ... Between electrodes 1, P102, ... Connected to the amplifier circuit unit 110 via an NMOS transistor TN5. The gate ends of the transistors TN4 and TN5 are connected to the word line decoder / driver 100 by the unit selection word lines W102 and W103.
Connected by the driver 1
It is controlled by 00.

With such a configuration, for example, when data is read from the capacitor C101, the driver 10
By controlling 0, the signal level of the unit selection word line W102 is set to "H" and the signal level of the unit selection word line W103 is set to "L", so that only the transistor TN4 is turned on. Further, as in the case of the first embodiment described above, a “H” pulse is applied to the plate line P101 to transmit the data signal to the amplifier circuit unit 110.
This data signal is amplified by the sensing transistor TP2 and transmitted to the bit line B101 via the transistor TN0.

When reading data from the capacitor C111, the signal level of the unit selection word line W102 is set to "L" and the signal level of the unit selection word line W103 is set to "H" under the control of the driver 100, so that only the transistor TN5 is turned on. Turn on. Further, a “H” pulse is applied to the plate line P101 to transmit a data signal to the amplifier circuit unit 110, and then the transistor TP2.
Is amplified by the bit line B10 via the transistor TN0.
Propagate to 1.

Also when writing data, the transistor TN4 or transistor TN5 connected to the memory unit 106 or 130 to be written is turned on, and the writing operation is performed as in the first embodiment.

As described above, in the cross point type storage device of this embodiment, the plurality of memory units 106 and 13 are provided.
0 is connected to the amplifier circuit unit 110 via the transistors TN4 and TN5, and one of the memory units 106 and 130 is connected to the amplifier circuit unit 110. With this configuration, more memory units 106 and 130 can be connected to the bit line B101 via the amplifier circuit unit 110, so that the area of the entire chip (the area of the entire cross-point type storage device) is further reduced. be able to.

(Third Embodiment) FIG. 5 shows a circuit configuration of a cross-point type memory device according to a third embodiment of the present invention. Again, similarly, the first of FIG.
The same reference numerals are given to the portions corresponding to the respective portions of the embodiment, and the description thereof will be omitted.

The cross-point type memory device of the present embodiment is different from the cross-point type memory device of the first embodiment in that the amplifier circuit unit 110 is replaced by an amplifier circuit unit 140 of another configuration. Especially.

The amplifier circuit unit 140 includes a pull-down transistor TN from the above amplifier circuit unit 110.
1 and TN2 are omitted. Further, the gate end of the transistor TP3 is not connected to the inverter circuit 114 as shown in FIG. 1, but is directly connected to the write control line WC as shown in FIG.

The data read and data rewrite operations in the cross-point type memory device having such a configuration will be described with reference to the timing chart shown in FIG.

First, the data read operation will be described. In the initial state at time t21, the signal level of the write control line WC is “H”, and the transistor TP3 is turned off by supplying “H” to the gate terminal of the transistor TP3. Further, the signal level of the reset line R is “H”, and the transistor TN3 is turned on by supplying this “H” to the gate end of the transistor TN3, so that the common node electrode E101 is equalized to 0V. There is. Further, the signal level of the word line W101 is “L”, and the transistor TN0 is turned off by supplying this “L” to the gate end of the transistor TN0. Therefore, the bit line B101 and the amplifier circuit unit 140 are separated from each other. It is in a separated state. Further, the signal levels of the plate lines P101 to P104 are all set to 0V.

At time t22, the signal level of the reset line R is set to "L", so that the transistor TN is turned on.
3 is turned off, which causes the common node electrode E101.
Becomes a floating state.

At time t23, for example, the plate line P
101 is selected and the time t23 is displayed on the plate line P101.
When a pulse of the power supply voltage Vcc which becomes “H” is given between to t29, the voltage is applied to the ferroelectric capacitor C101, and the potential of the common node electrode E101 rises as shown in FIG. The degree of this increase depends on the capacitor C101.
Becomes large (data becomes "1") with polarization inversion, and becomes small (data becomes "0") without inversion.

At time t24, the signal level of the word line W101 becomes "H", so that the transistor TN0 is turned on, and the bit line B101 and the amplifier circuit unit 140 are turned on.
And connect. At this time, since the voltage of the common node electrode E101 is supplied to the gate end of the transistor TP2, the bit line B101 is charged according to the current flowing through the transistor TP2 in the ON state, and its potential rises as shown in FIG. start. Here, the degree of increase becomes small when reading "1" and becomes large when reading "0".

At time t25, the sense amplifier 104 connected to the bit line B101 is activated and data "
1 "or" 0 "is determined. When this determination is performed, the sense amplifier 104 compares the potential of the bit line B101 with the reference potential, thereby completing the data read operation from the capacitor C101. .

Next, the data rewriting operation will be described. At time t26, the bit line B101 has data “1”.
When the potential is equivalent to, the voltage is discharged by the sense amplifier 104 and becomes 0V. On the other hand, the bit line B1
When 01 is the potential corresponding to the data “0”, the sense transistor TP2 or the sense amplifier 104 is charged to about 1V. However, Vcc = 3V. The voltage of the bit line B101 is the same as that of the word line W10.
Since the signal level of 1 is "H" and the transistor TN0 is in the ON state, it is supplied to the gate terminal of the transistor TP1.

At time t27, the potentials of the non-selected plate lines P102 to P104 are Vcc / 2 (= 1.5V).
Becomes At this time, the selected plate line P101
Has a potential of Vcc (= 3V).

At time t28, the signal level of the reset line R is set to "H", so that the transistor TN3
Is turned on, and the potential of the common node electrode E101 is dropped to 0V. As a result, -Vcc is applied to the capacitor C101, and "0" is written first. On the other hand, the voltage applied to the non-selected capacitors c12 to C14 is-(Vcc /
2), and if the coercive electric field is set lower than that, the polarization direction is maintained.

At time t29, the selected plate line P101
And the potential of the reset line R is set to "L". At time t30, when the transistor TP3 is turned on by setting the signal level of the write control line WC to “L”, the potential of the common node electrode E101 is applied to the gate end of the transistor TP1 via the transistor TN0. The rise starts at a speed depending on the voltage (data) on the line B101. Here, the current capability of the transistor TP1 is proportional to the square of (Vg-Vth). However,
Vth is a threshold value, and Vg is a voltage applied to the gate end with the source (here, Vcc) as a reference. For example, Vth-
If it is 1.5V, the current capacity when writing "1" is "
It is 9 times as much as when writing 0 ".

At time t31, the signal level of the word line W101 is set to "L" at the timing when the potential of the common node electrode E101 at the time of writing "1" reaches Vcc.
The transistor TN0 is turned off. At this time, the common node electrode E10 in "1" write and "0" write
The potential of 1 is as follows. First, the potential of the common node electrode E101 at the time of writing "1" is latched at Vcc. On the other hand, the common node electrode E101 at the time of writing "0"
Is still 1 V or less, and the sensing transistor TP2 remains on.

As a result, the potential of the node 116 rapidly rises to V.
Since it is charged up to cc and is supplied to the gate terminal of the transistor TP1, the current supply of the transistor TP1 is stopped. That is, the common node electrode E101 at the time of writing "0"
Is maintained in a floating state of 1 V or less.

Through the above process, in the case of writing "1", the voltage of Vcc is applied to the selection capacitor C101, and the writing of "1" is performed. On the other hand, at the time of writing "0", only the potential of 1 V or less is applied to the selection capacitor C101. Further, the non-selected capacitors C102 to
The voltage applied to C104 is Vcc / 2, and the polarization direction is maintained if the coercive electric field is set lower than that.

At time t32, the write control line WC
Is set to "H" to turn off the transistor TP3. At time t33, the signal level of the reset line R is set to “H” to return the potential of the common node electrode E101 to 0V. Further, the potentials of the non-selected plate lines P102 to P104 are returned to 0V, the bit line B101 is also equalized to 0V, and the data rewriting operation is completed.

As described above, according to the cross-point type memory device of this embodiment, the amplifier circuit unit 140 is not
Since the number of transistors is smaller than that of the amplifier circuit unit 110 of the embodiment, the area of the entire chip (the area of the entire cross-point type storage device) can be further reduced.

If the amplifier circuit units 110 and 140 described in the first to third embodiments are formed in the unused silicon region in the conventional cross point type memory device,
The area of the entire chip (the area of the entire cross-point type storage device) can be further reduced. This will be described with reference to FIG. 7, which is a cross-sectional view of the cross-point type memory device shown in FIG.

That is, each of the capacitors C101 to C10
4 is formed by sandwiching the ferroelectric film 150 between the plate lines (plate electrodes) P101 to P104 and the common node electrode E101. The common node electrode E101 is connected to the diffusion layer 154 of the transistor TN0 via the plug 153 formed in the interlayer insulating film 153. The bit line B101 and the word line W101 are formed in a layer between the common node electrode E101 and the transistor TN0. Since most of the constituent elements of this cell are capacitors, the area occupied by them is not that of the transistor TN0 but the plate lines P101 to P101 forming the capacitor group.
It depends on 104. That is, there is a large unused region 152 on the silicon semiconductor substrate 151 in the cell. If the amplifier circuit unit 110 is formed in the unused area 152, the area of the entire chip can be further reduced.

[0070]

As described above, according to the ferroelectric memory device of the present invention, a memory having a plurality of ferroelectric capacitors connected between a plurality of independent plate lines and a common node electrode, respectively. An amplifier circuit unit is connected between the unit and the bit line, and this amplifier circuit unit amplifies the data signal of the common node electrode when reading data from the capacitor and transmits it to the bit line, and when writing data to the capacitor The common node electrode is charged and discharged according to the signal received from the line. As a result, a signal having a sufficient potential for reading data can be taken out from a miniaturized capacitor (memory cell), power consumption at the time of writing data can be reduced, and the area of the entire chip can be further reduced. be able to.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a cross-point type memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining data read and data rewrite operations in the cross point type memory device shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of a dummy amplifier circuit unit.

FIG. 4 is a diagram showing a circuit configuration of a cross point type memory device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a cross point type memory device according to a third embodiment of the present invention.

6 is a timing chart for explaining a data read operation and a data rewrite operation in the cross point type memory device shown in FIG.

FIG. 7 is a diagram showing a cross section of a cross-point type storage device.

FIG. 8 is a diagram showing a circuit configuration of a conventional ferroelectric memory device.

FIG. 9 is a diagram showing a circuit configuration of a conventional cross-point type memory device.

[Explanation of symbols]

100 ... Word line decoder driver, 102 ... Plate line decoder driver, 104 ... Sense amplifier,
106, 130 ... Memory units 110, 140 ... Amplifier circuit units 112, 114 ... Inverter circuit 116 ... Gate end connection node 120 of transistors TP1 and TN2 ... Dummy amplifier circuit units TN0 to TN5 ... NMOS type transistors TP1 to TP3 ... PMOS type Transistor Vcc ... Power supply voltage R ... Reset line WC ... Write control line W101 ... Word lines W102, W103 ... Unit selection word line B101 ... Bit lines P101 to P104 ... Plate lines C101 to C104, C111, C112 ... Capacitor E101 ... Common node electrode 150 ... Ferroelectric film 151 ... Silicon semiconductor substrate 152 ... Unused region

Claims (4)

[Claims] 1. A plurality of ferroelectrics, each of which is connected between a plurality of independent plate lines and a common node electrode, and in which storage control of data is performed independently in response to voltage application to the plate lines. A memory unit having a capacitor, which is connected between the memory unit and a bit line, amplifies a data signal of the common node electrode when reading data from the capacitor, transmits the amplified signal signal to the bit line, and outputs data to the capacitor. A ferroelectric memory device, comprising: an amplifier circuit unit that charges and discharges the common node electrode according to a signal received from a bit line during writing. 2. The ferroelectric memory device according to claim 1, further comprising a plurality of the memory units, and a switch means for connecting any one of the plurality of memory units to the amplifier circuit unit. 3. A strong signal according to claim 1, wherein a voltage of a signal supplied from the bit line to the amplifier circuit unit for charging and discharging the common node electrode is lower than a power supply voltage. Dielectric storage device. 4. The memory unit is formed on an interlayer insulating film on a semiconductor substrate, and the amplifier circuit unit is formed using a region corresponding to a formation region of the memory unit on the semiconductor substrate. The ferroelectric memory device according to any one of claims 1 to 3, wherein