JP2003121878A - Electro-optical device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix driven electro-optical device such as a liquid crystal device which can add sufficient storage capacitance to pixel electrodes and can decrease the diameter of contact holes connecting with the pixel electrodes even when a fine pixel pitch is employed. SOLUTION: The liquid crystal device is provided with TFTs (30), data lines (6a), scanning lines (3a), storage capacitor lines (3b) and the pixel electrodes (9a) on a TFT array substrate (10). Each of the pixel electrodes is electrically connected to one of the TFTs by two contact holes (8a, 8b) through a barrier layer (80). Part of a semiconductor layer and each of the storage capacitor lines sandwich a first dielectric film (2) and constitute a first storage capacitor (70a), while part of the barrier layer and each of the storage capacitor lines sandwich a second dielectric film (81) and constitute a second storage capacitor (70b).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technical field of an electro-optical device of an active matrix driving system and a method of manufacturing the same, and in particular, it is provided with a storage capacitor electrode for adding a storage capacitor and is used for pixel electrodes and pixel switching. Thin film transistor (TFT)
(Hereinafter referred to as)), which belongs to the technical field of an electro-optical device including a conductive layer referred to as a barrier layer for achieving good electrical conduction between the device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in an electro-optical device of an active matrix driving system driven by TFTs, a large number of TFTs are arranged on a TFT array substrate in correspondence with a large number of scanning lines and data lines arranged vertically and horizontally and their intersections. It is provided in. In each TFT, the gate electrode is connected to the scanning line, the source region of the semiconductor layer is connected to the data line, and the drain region of the semiconductor layer is connected to the pixel electrode. Here, in particular, since the pixel electrode is provided on various layers forming the TFT or wiring or on the interlayer insulating film for insulating the pixel electrode from each other, the contact hole formed in the interlayer insulating film is used. And is connected to the drain region of the semiconductor layer that constitutes the TFT. When a scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on, and the image signal supplied to the source region of the semiconductor layer via the data line is the source-drain of the TFT. It is supplied to the pixel electrode through the space. Such an image signal is supplied to each pixel electrode through each TFT only for an extremely short time. Therefore, in order to hold the voltage of the image signal supplied through the TFT that has been turned on for an extremely short time for a far longer time than the time that the pixel is turned on, each pixel electrode is held. In general, the storage capacitor is formed in parallel with the liquid crystal capacitor. On the other hand, in this type of electro-optical device, the semiconductor layer formed on the TFT array substrate constitutes the source region and drain region of the pixel switching TFT and the channel region therebetween. The pixel electrode includes a scanning line, a capacitance line, and a laminated structure.
It is necessary to be connected to the drain region of the semiconductor layer through wirings such as data lines and a plurality of interlayer insulating films for electrically insulating them from each other. Here, particularly in the case of a positive stagger type or coplanar type polysilicon TFT having a top gate structure in which a gate electrode is provided on the semiconductor layer when viewed from the TFT array substrate side, especially from the semiconductor layer to the pixel electrode in the laminated structure. The inter-layer distance is 100
Since the length is about 0 nm or longer, it is difficult to open a contact hole for electrically connecting the both. More specifically, as the depth of etching deepens, the precision of etching deteriorates, and there is a possibility that the target semiconductor layer may be penetrated to open a hole. It becomes extremely difficult to open the holes. For this reason, dry etching and wet etching may be combined, but this time, the diameter of the contact hole becomes large due to the wet etching, and it is necessary to lay out as many wirings and electrodes as necessary in a limited area on the substrate. It will be difficult.

Therefore, recently, when an electrical connection is made between a data line and a source region by opening a contact hole reaching a source region of a semiconductor layer in an interlayer insulating film formed on a scanning line, A contact hole reaching the drain region of the semiconductor layer is opened, and a conductive layer for relay called a barrier layer made of the same layer as the data line is formed on the interlayer insulating film. A technique has been developed in which a contact hole from the pixel electrode to the barrier layer is opened in the interlayer insulating film formed on the barrier layer. In this way, if the barrier layer formed of the same layer as the data line is relayed to electrically connect the pixel electrode to the drain region, it is possible to open contact holes from the pixel electrode to the semiconductor layer all at once. However, the process of opening the contact holes is facilitated and the diameter of each contact hole can be made small.

[0004]

In the electro-optical device of this type, there is a strong general demand for high quality display images. To this end, the image display area is made finer or the pixel pitch is made finer. And high pixel aperture ratio (that is, in each pixel, for a non-pixel aperture region where display light does not pass,
It is extremely important to increase the ratio of the pixel opening area through which the display light is transmitted.

However, as the pixel pitch becomes finer, the electrode size, the wiring width, the contact hole diameter, etc. are essentially limited by the manufacturing technology.
Since the ratio of these wirings and electrodes occupying the image display area relatively increases, there is a problem that the pixel aperture ratio becomes low.

Further, as the pixel pitch becomes finer in this way, it becomes difficult to make the above-mentioned storage capacitance, which must be built in a limited region on the substrate, sufficiently large.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and even if the pixel pitch is miniaturized, the pixel electrode and the thin film transistor are satisfactorily relayed by using a relatively simple structure. It is an object of the present invention to provide an electro-optical device capable of displaying a high-quality image and a method of manufacturing the same, which can be configured and configured to increase the storage capacity.

In order to solve the above-mentioned problems, an electro-optical device of the present invention is an electro-optical device having a pixel electrode provided corresponding to a thin film transistor and a storage capacitor connected to the pixel electrode. A first storage capacitor electrode formed on the drain region side of the semiconductor layer of the thin film transistor, and the same layer as the gate electrode of the thin film transistor,
A second storage capacitor electrode formed to face the first storage capacitor electrode, and electrically connected to a drain region of the semiconductor layer formed above the second storage capacitor electrode via an insulating film And a pixel electrode formed above the conductive film via an insulating film and electrically connected to the conductive film, and the insulating film under the pixel electrode is a planarization film. Is characterized in that.

Further, the conductive film is a third storage capacitor electrode formed so as to face the second storage capacitor electrode.

The electronic equipment of the present invention is characterized by having the above-mentioned electro-optical device.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. Figure 1
FIG. 2 is an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. 2 shows data lines, scanning lines, pixel electrodes, light shielding films, etc. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate, and FIG. 3 is a sectional view taken along line AA ′ of FIG. 2. In FIG. 3, the scales of the layers and members are made different so that the layers and members are recognizable in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix form the image display area of the liquid crystal device according to the present embodiment includes a TFT 3 for controlling a pixel electrode 9a.
A plurality of 0s are formed in a matrix, and the data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The pixel electrode 9a and the TFT 30 are
It is arranged corresponding to the intersection of the scanning line 3a and the data line 6a. Image signals S1, S2 to be written to the data line 6a,
, Sn may be supplied line-sequentially in this order,
The data lines 6a adjacent to each other may be supplied for each group. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1 and G are pulsed to the scanning line 3a at a predetermined timing.
, ..., Gm are applied line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30 and serves as a switching element TF.
By closing the switch of T30 for a certain period, the image signals S1, S2 supplied from the data line 6a,
..., Sn is written at a predetermined timing. Pixel electrode 9a
The image signal S of a predetermined level written in the liquid crystal through the
, S2, ..., Sn are held for a certain period of time with a counter electrode (described later) formed on a counter substrate (described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly depending on the applied voltage level, and enables gradation display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage, and in the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. Light that can pass therethrough is emitted from the liquid crystal device as a whole with a contrast according to the image signal. Here, in order to prevent the held image signal from leaking, the storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is stored in the storage capacitor 7 for a time that is three orders of magnitude longer than the time when the source voltage is applied.
It is held by 0. As a result, the holding characteristic is further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on the TFT array substrate of the liquid crystal device.
The data line 6a, the scanning line 3a and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film or the like through the contact hole 5, and the pixel electrode 9a is a region shown by an oblique line rising to the right in the drawing. And a conductive layer 80 (hereinafter, referred to as a barrier layer) that is formed in each of the layers and functions as a buffer.
Via the first contact hole 8a and the second contact hole 8b, and is electrically connected to a drain region of the semiconductor layer 1a described later. In addition, the semiconductor layer 1
The scanning line 3a is arranged so as to face the channel region 1a '(the region of the oblique line on the lower right in the drawing) of a, and the scanning line 3a functions as a gate electrode. In this way, the TFTs 30 in which the scanning lines 3a are opposed to each other as the gate electrodes are provided in the channel regions 1a 'at the intersections of the scanning lines 3a and the data lines 6a, respectively.

The capacitance line 3b has a main line portion extending substantially linearly along the scanning line 3a, and a protruding portion protruding from a position intersecting the data line 6a to the front side (upward in the figure) along the data line 6a. Have and.

Further, the first light-shielding film 11a is provided so as to pass under the scanning line 3a, the capacitance line 3b and the TFT 30, respectively, in the regions shown by thick lines in the figure. More specifically, referring to FIG. 2, the first light-shielding film 11a has scanning lines 3a.
Is formed in a striped pattern along with, and a portion that intersects with the data line 6a is formed wide downward in the drawing, and the channel portion 1a ′ of each TFT is formed by TF by this wide portion.
It is provided at a position to cover each when viewed from the T array substrate side.

Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device has an example of a transparent TFT array substrate 10 and an example of the other transparent substrate arranged opposite to the TFT array substrate 10. And a counter substrate 20 that operates. The TFT array substrate 10 is made of, for example, a quartz substrate, and includes a counter substrate 20.
Is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is made of a transparent conductive thin film such as an ITO film. Alignment film 1
6 is made of an organic thin film such as a polyimide thin film.

On the other hand, the counter substrate 20 is provided with a counter electrode 21 over the entire surface thereof, and an alignment film 22 subjected to a predetermined alignment treatment such as rubbing treatment is provided below the counter electrode 21. There is. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is formed on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to a.

As shown in FIG. 3, the counter substrate 20 may be provided with a second light shielding film 23 in the non-opening area of each pixel. Therefore, incident light does not enter the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Further, the second light shielding film 23 is
It has functions of improving contrast and preventing color mixture of color materials when a color filter is formed.

Between the TFT array substrate 10 and the counter substrate 20, which are arranged in this way and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, the space surrounded by the sealing material described later is electrically connected. A liquid crystal, which is an example of an optical material, is encapsulated to form a liquid crystal layer 50. The liquid crystal layer 50 is formed on the alignment film 16 in a state where the electric field from the pixel electrode 9a is not applied.
And 22 take a predetermined orientation state. The liquid crystal layer 50 is
For example, it is composed of a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive for bonding the TFT array substrate 10 and the counter substrate 20 around their periphery, which is made of, for example, a photocurable resin or a thermosetting resin,
A gap material such as glass fiber or glass beads for mixing the two substrates to a predetermined value is mixed.

Further, as shown in FIG. 3, a first light-shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each pixel switching TFT 30. First light-shielding film 1
1a is Ti, C which is preferably an opaque refractory metal
It is composed of a simple metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo and Pb. With such a material, the first light-shielding film 11a is not destroyed or melted by the high temperature treatment in the process of forming the pixel switching TFT 30 performed after the process of forming the first light-shielding film 11a on the TFT array substrate 10. You can Since the first light-shielding film 11a is formed, reflected light (return light) from the TFT array substrate 10 side
TFTs for pixel switching that are easily excited by light
It is possible to prevent incidents on the channel region 1a ′, the low-concentration source region 1b, and the low-concentration drain region 1c of 30 from occurring, and the characteristics of the pixel switching TFT 30 change due to the generation of photocurrent due to this. It does not deteriorate.

Further, a base insulating film 12 is provided between the first light shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 includes the semiconductor layer 1a forming the pixel switching TFT 30 as the first light shielding film 11a.
It is provided to electrically insulate from. Further, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10, so that the pixel switching TFT 30 is formed.
Also has a function as a base film. That is, TFT
It has a function of preventing the characteristics of the pixel switching TFT 30 from deteriorating due to surface roughness of the array substrate 10 during polishing, stains remaining after cleaning, and the like. The base insulating film 12 is, for example, NSG (non-doped tosilicate glass), PSG.
(Phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphosilicate glass), or other high insulating glass, or a silicon oxide film, a silicon nitride film, or the like. The base insulating film 12 allows the first light-shielding film 1
It is also possible to prevent the situation where 1a contaminates the pixel switching TFT 30 and the like.

In this embodiment, the semiconductor layer 1a is extended from the high-concentration drain region 1e to form the first storage capacitance electrode 1f, and a part of the capacitance line 3b facing the first storage capacitance electrode 1f serves as the second storage capacitance electrode. The first storage capacitor 70a is formed by extending 2 from the position facing the scanning line 3a to form the first dielectric film sandwiched between these electrodes. Further, a part of the barrier layer 80 facing the second storage capacitor electrode is used as the third storage capacitor electrode, and the first interlayer insulating film 81 is provided between these electrodes. The first interlayer insulating film 81 also functions as a second dielectric film, and the second storage capacitor 70b is formed. Then, the first storage capacitor 70a and the second storage capacitor 70b are connected in parallel via the first contact hole 8a to form the storage capacitor 70.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is extended below the data line 6a and the scanning line 3a to form the pixel switching TFT 30, and the data line 6a and the scanning line 3a are also formed. Capacitance line 3 extending along
The first dielectric film 2 and the first dielectric film 2 are arranged so as to face each other in the portion b.
The storage capacitor electrode 1f is used. Particularly, the first dielectric film 2 is a TFT 3 formed on the polysilicon film by high temperature oxidation or the like.
Since it is nothing but the insulating thin film 2 of 0, it can be a thin and high breakdown voltage insulating film, and the first storage capacitor 70a can be configured as a large storage capacitor with a relatively small area. Also, the second
Since the dielectric film 81 can be formed thin similarly to the insulating thin film 2, the second storage capacitance 70b is relatively small by utilizing the region between the adjacent data lines 6a as shown in FIG. It can be configured as a large-capacity storage capacitor in area. Therefore,
The storage capacitor 70 formed three-dimensionally from the first storage capacitor 70a and the second storage capacitor 70b is a region below the data line 6a or a region where liquid crystal disclination occurs along the scanning line 3a (that is, the capacitance). Area where line 3b is formed)
By effectively utilizing the space outside the pixel opening region, it is possible to form a large-capacity storage capacitor with a small area.

In FIG. 3, a pixel switching TFT
Reference numeral 30 has an LDD structure, and includes the scanning line 3a, a channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, the scanning line 3a and the semiconductor layer 1.
Insulating thin film 2 for insulating from a, data line 6a, semiconductor layer 1
a low-concentration source region 1b and low-concentration drain region 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
A corresponding one of the plurality of pixel electrodes 9a is connected to e via the barrier layer 80. The low-concentration source region 1b, the high-concentration source region 1d, the low-concentration drain region 1c, and the high-concentration drain region 1e are as described below.
The semiconductor layer 1a is formed by doping an impurity for n-type or p-type with a predetermined concentration according to whether an n-type or p-type channel is formed. n-type channel T
The FT has an advantage of high operation speed and is often used as the pixel switching TFT 30 which is a pixel switching element. In this embodiment, in particular, the data line 6a is composed of a light-shielding and conductive thin film such as a low resistance metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 is formed on the barrier layer 80 and the second dielectric film (first interlayer insulating film) 81. The contact hole 5 communicates with the high-concentration source region 1d and the contact hole 8b communicates with the barrier layer 80. The interlayer insulating film 4 is formed. Through the contact hole 5 to the high concentration source region 1d, the data line 6a is connected to the high concentration source region 1d.
Electrically connected to. Further, on the data line 6a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8b to the barrier layer 80 is formed is formed. Through the contact hole 8b, the pixel electrode 9
a is electrically connected to the barrier layer 80, and further relays the barrier layer 80 and is electrically connected to the high-concentration drain region 1e through the contact hole 8a. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.

Although the pixel switching TFT 30 preferably has an LDD structure as described above, it may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c, or the scanning line 3a.
It may be a self-aligned TFT in which a high-concentration source and drain region is formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode which is a part of the above as a mask.

Further, in the present embodiment, the single gate structure in which only one gate electrode which is a part of the scanning line 3a of the pixel switching TFT 30 is arranged between the high concentration source region 1d and the high concentration drain region 1e, is used. Two or more gate electrodes may be arranged between them. At this time, the same signal is applied to each gate electrode. As described above, if the TFT is configured with dual gates or triple gates or more, it is possible to prevent a leak current at the junction between the channel and the source-drain region, and reduce the current when off. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.

As shown in FIGS. 2 and 3, in the liquid crystal device of this embodiment, the data lines 6 a and the scanning lines 3 b are three-dimensionally arranged on the TFT array substrate 10 via the second interlayer insulating film 4. It is provided to intersect. The barrier layer 80 is interposed between the semiconductor layer 1a and the pixel electrode 9a, and the high-concentration drain region 1e and the pixel electrode 9a are formed in the first layer.
Electrical connection is made via the contact hole 8a and the second contact hole 8b.

Therefore, from the pixel electrode 9a to the semiconductor layer 1a
The diameters of the first contact hole 8a and the second contact hole 8b can be made smaller than in the case where one contact hole is opened up to the drain region. That is, when one contact hole is opened, if the selection ratio during etching is low, the deeper the contact hole is, the lower the etching accuracy becomes. Therefore, for example, penetration of a very thin semiconductor layer 1a of about 50 nm is prevented. In order to do so, it is necessary to stop the dry etching which can reduce the diameter of the contact hole on the way and finally to perform the step of wet etching so as to open up to the semiconductor layer 1a. Alternatively, it is necessary to separately provide a polysilicon film for preventing punch-through by dry etching.

On the other hand, in the present embodiment, the pixel electrode 9
a and the high-concentration drain region 1e may be connected by two series-connected first contact holes 8a and second contact holes 8b.
The second contact hole 8b and the second contact hole 8b can be opened by dry etching. Alternatively,
At least it is possible to shorten the distance of opening by wet etching. However, in order to slightly taper the first contact hole 8a and the second contact hole 8b, respectively, the wet etching may be intentionally performed for a relatively short time after the dry etching.

As described above, according to the present embodiment, the diameters of the first contact hole 8a and the second contact hole 8b can be made smaller, and the depressions and irregularities formed on the surface of the barrier layer 80 in the first contact hole 8a can be reduced. Since the size is also small, the flattening of the portion of the pixel electrode 9a located thereabove is promoted. Furthermore, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the second contact hole 8b can be small, the flattening of the portion of the pixel electrode 9a is promoted. As a result, disclination in the liquid crystal layer 50 due to the depressions and projections on the surface of the pixel electrode 9a is reduced, and finally the liquid crystal device can display a high-quality image. For example, the second interlayer insulating film 4 interposed between the barrier layer 80 and the pixel electrode 9a.
If the total film thickness of the third interlayer insulating film 7 is suppressed to about several hundreds nm, the second contact hole 8 that more directly affects the above-mentioned depressions and irregularities on the surface of the pixel electrode 9a.
The diameter of b can be made very small.

In this embodiment, since the barrier layer 80 is composed of the refractory metal film or its alloy film, the etching selectivity between the metal film and the interlayer insulating film is largely different. There is almost no possibility of penetration of the barrier layer 80 due to etching.

In the present embodiment, particularly, in the storage capacitor 70 formed three-dimensionally with the barrier layer 80 at the center,
Each of the dielectric film 2 and the second dielectric film 81 is a dielectric provided in a layer different from the second interlayer insulating film 4 interposed between the data line 6a and the scanning line 3b that three-dimensionally intersect each other. It is a body membrane. Therefore, in order to suppress the parasitic capacitance between the data line 6a and the scanning line 3a that causes the voltage drop of the image signal that causes flicker and the like, the barrier layer 80 is provided via a layer different from the second interlayer insulating film 4. Since the storage capacitor is added, in the case of the present embodiment, it is possible to make the first dielectric film 2 and the second dielectric film 81 thin to the technical limit. As a result, it is possible to extremely efficiently increase the capacitance value that is inversely proportional to the thickness of the second dielectric film 81, particularly in the second storage capacitor 70b. Particularly, if the pixel switching TFT 30 is made too thin like the insulating thin film 2, a peculiar phenomenon such as a tunnel effect does not occur. Ultrathin second with a thickness of 10 nm or more and 50 nm or less thinner than 2
By forming the dielectric film 81, it is possible to form the very large second storage capacitor 70b in a relatively small region. This not only suppresses the occurrence of flicker but also enhances the voltage holding ability,
An electro-optical device having high contrast can be provided.

According to experiments and studies by the inventors of the present application, it is assumed that this barrier layer is used as one electrode of the storage capacitor in the above-described conventional technique in which the barrier layer is formed of the same conductive layer as the data line 6a. Assuming that the interlayer insulating film between the data line 6a and the scanning line 3a is used as a dielectric film, in order to prevent the parasitic capacitance between the data line 6a and the scanning line 3a from becoming a problem, the dielectric film ( A film corresponding to the second interlayer insulating film of this embodiment) needs to have a thickness of about 800 nm. Therefore, in the present embodiment, in the present embodiment, the second storage capacitor 70b having a capacitance value of several times to more than ten times or more can be realized, which is extremely advantageous.

It is to be noted that the TFT array substrate 10 having a limited structure is formed by further forming another barrier layer or layers between the barrier layer 80 and the pixel electrode 9a via an interlayer insulating film.
It is possible to increase the storage capacity three-dimensionally by utilizing the upper region.

As described above, the second dielectric film 81 constituting the second storage capacitor 70b may be a silicon oxide film, a silicon nitride film, or the like, or may be a multilayer film in which a plurality of these films are laminated. Various known techniques generally used for forming the insulating thin film 2 (low pressure CVD method, atmospheric pressure CVD method, plasma CVD method, thermal oxidation method, sputtering method, ECR
The second dielectric film 81 can be formed by a plasma method, a remote plasma method, or the like). However, in place of or in addition to the storage capacitance adding function of the barrier layer 80, the light shielding function of the barrier layer 80 formed of a light shielding film, the layout of the first contact hole 8a and the second contact hole 8b, and the like are particularly emphasized. In the case of forming the barrier layer 80 and the second dielectric film 81 up to the scanning line 3a, the second dielectric film 81 should be thick enough so that the parasitic capacitance between the barrier layer 80 and the scanning line 3a does not matter. It is preferably formed.

On the other hand, the thickness of the barrier layer 80 is, for example, 50.
It is preferable to set the thickness to not less than 500 nm and not more than 500 nm. Fifty
If the thickness is about nm, the possibility of penetrating through when the second contact hole 8b is opened in the manufacturing process is low, and if it is about 500 nm, the unevenness of the surface of the pixel electrode 9a does not pose a problem or is relatively easy. This is because it can be flattened.

Further, in the present embodiment, by forming the first interlayer insulating film (second dielectric film) 81 thin in this way, the diameter of the first contact hole 8a can be further reduced. The depressions and irregularities of the barrier layer 80 in the holes 8a can be made smaller, and the flattening of the pixel electrodes 9a located thereabove can be further promoted. Therefore, the discnation of the liquid crystal due to the depressions and protrusions in the pixel electrode 9a is reduced, and finally the liquid crystal device can display a higher quality image.

In the structure of the liquid crystal device of this embodiment, as in the conventional case, the parasitic capacitance between the two wirings is a problem for the second interlayer insulating film 4 interposed between the scanning line 3b and the data line 6a. Thickness (eg 800
(thickness of about nm) is required.

In the present embodiment configured as described above, in particular, the stripe-shaped first light-shielding film 11a is extended below the scanning line 3a and electrically connected to the constant potential source or the large capacity portion. May be connected to. According to this structure, the pixel switching TFT arranged to face the first light shielding film 11a
The potential fluctuation of the first light shielding film 11a does not adversely affect 30. In this case, as the constant potential source, a negative power source, a constant potential source such as a positive power source, and a ground power source that are supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, etc.) for driving the liquid crystal device. , A constant potential source supplied to the counter electrode 21, and the like.

The capacitance line 3b and the scanning line 3a are made of the same polysilicon film, and the first storage capacitor 70a has the first storage capacitor 70a.
The dielectric film 2 and the insulating thin film 2 of the pixel switching TFT 30 are made of the same high-temperature oxide film or the like, and the first storage capacitor electrode 1f and the channel region 1a ′ of the pixel switching TFT 30, the low concentration source region 1b, and the low concentration are formed. Drain region 1
c, the high-concentration source region 1d, the high-concentration drain region 1e, etc. are formed of the same semiconductor layer 1a. Therefore, the TFT
The laminated structure formed on the array substrate 10 can be simplified,
Further, in the manufacturing method of the electro-optical device described later, the capacitance line 3b and the scanning line 3a can be simultaneously formed in the same thin film forming step, and the first dielectric film and the insulating thin film 2 of the storage capacitor 70a can be simultaneously formed.

Particularly in this embodiment, the barrier layer 80 is made of a conductive light shielding film. Therefore, by the barrier layer 80,
It is possible to at least partially define each pixel opening area. Further, the TFT array substrate 10 of the wiring having a light shielding property such as the barrier layer 80 or the data line 6a.
It is also possible to omit the second light-shielding film on the counter substrate 20 side by defining the pixel opening portion in combination with the film having a light-shielding property formed in the above. Second on the counter substrate 20
The configuration in which the barrier layer 80 is provided as the built-in light-shielding film on the TFT array substrate 10 instead of the light-shielding film 23 is that the pixel aperture ratio does not decrease due to the positional shift between the TFT array substrate 10 and the counter substrate 20 in the manufacturing process. It is extremely advantageous.

The second light-shielding film 23 on the counter substrate 20 is
Mainly for the purpose of suppressing the temperature rise of the liquid crystal device due to incident light,
It may be formed small (narrow) so as not to define the pixel opening region. In this case, the second light-shielding film 23 is made of Al.
If it is made of a material having a high reflectance such as a film, the temperature rise can be suppressed more efficiently. In this way, the second light-shielding film 2
If 3 is formed smaller than the light-shielding region in the TFT array substrate, the pixel opening region does not become small due to some positional deviation between the two substrates in the manufacturing process.

The barrier layer 80 made of a light shielding film is, for example,
Opaque refractory metals such as Ti, Cr, W, Ta, Mo
And at least one of Pb and a simple metal, an alloy, a metal silicide, or the like. According to this structure, the barrier layer 80 can be prevented from being broken or melted by the high temperature treatment performed after the barrier layer 80 forming step.

Further, the refractory metal and the pixel electrode 9a are used.
The refractory metal does not melt due to the difference in ionization rate even when it comes into contact with the ITO film that constitutes the barrier layer 80 and the pixel electrode 9a through the second contact hole 8b.
Good electrical connection between them.

Further, particularly in this embodiment, as shown in FIG. 2, the barrier layer 80 made of a light-shielding film extends along the scanning line 3a between the data lines 6a whose planar shapes on the TFT array substrate 10 are adjacent to each other. , Each pixel unit is formed in an island shape. Thereby, the stress due to the light shielding film can be relaxed. It is also possible to define a part or all of the side of the pixel opening region along the scanning line 3a by the barrier layer 80. Here, when the parasitic capacitance between the scanning line 3a and the barrier layer 80 becomes a problem depending on a specific circuit design, the barrier layer 8 is formed on the scanning line 3a as in the present embodiment.
It is preferable that the side along the scanning line 3a of the pixel opening region on the side where the capacitance line 3b and the pixel electrode 9a are adjacent to each other is defined by the barrier layer 80 without providing 0. Alternatively,
The scanning line 3a and the barrier layer 80 are selected according to the specific circuit design.
If the parasitic capacitance between them does not matter, the barrier layer 8
0 may also be formed at a position facing the scanning line 3a with the second dielectric film 81 interposed therebetween. According to this structure, the light-shielding barrier layer 80 that at least partially covers both the scanning lines 3a and the capacitance lines 3b defines more of the side of the pixel opening region along the scanning lines 3a. It becomes possible. In other words, in the case of such a configuration, it is preferable that the second dielectric film 81 is configured to be thick so that the parasitic capacitance of the scanning line 3a and the barrier layer 80 does not matter. Or, in order to keep this parasitic capacitance small,
It is preferable that the barrier layer 80 covers the scanning line 3a only in an area necessary for defining the pixel opening area.

The scanning line 3a in the pixel opening region on the side where the scanning line 3a and the pixel electrode 9a are adjacent to each other (lower side in FIG. 2).
The side along the line may be defined by the first light-shielding film 11a and the second light-shielding film 23. The side of the pixel opening region along the data line 6a may be defined by the data line 6a made of Al or the like, or the first light-shielding film 11a or the second light-shielding film 23.

Further, as shown in FIG. 2, the island-shaped barrier layer 8
It is preferable that each end of the 0 line in the scanning line 3a direction and the edge of the data line 6a slightly overlap each other when viewed two-dimensionally. According to this structure, it is not necessary to form a gap for transmitting incident light between them, and it is possible to prevent display defects such as light leakage in this portion. Here, the data line 6a, the barrier layer 80, the first light-shielding film 11a, or the data line 6a.
The pixel opening portion can be defined by a light-shielding film such as the barrier layer 80. In such a case, since it is not necessary to form the second light shielding film 23 on the counter substrate 20, it is possible to reduce the step of forming the second light shielding film 23 on the counter substrate 20. Furthermore, it is possible to prevent the pixel aperture ratio from decreasing or varying due to misalignment between the counter substrate 20 and the TFT array substrate 10. When the second light-shielding film 23 is provided on the counter substrate 20, the TFT array substrate 10
Although it is formed in a large size in consideration of the misalignment with the above, as described above, since the pixel opening is defined by the light-shielding film formed on the TFT array substrate 10 side such as the data line 6a and the barrier layer 80, the pixel opening is accurately formed. The pixel aperture can be defined, and the aperture ratio can be improved as compared with the case where the pixel aperture is determined by the second light shielding film 23 provided on the counter substrate 20.

As described above, particularly in this embodiment,
Although the barrier layer 80 is made of a conductive light-shielding film, various advantages can be obtained. However, even if the barrier layer 80 is made of, for example, a conductive polysilicon film doped with phosphorus or the like instead of the refractory metal film. Good. According to this structure, the barrier layer 80 does not function as a light-shielding film, but can sufficiently exhibit the function of increasing the storage capacitance 70 and the original relay function of the barrier layer. Further, stress due to heat or the like is less likely to occur between the barrier layer 8 and the second interlayer insulating film 4.
Helps prevent cracks in and around 0. On the other hand,
Light shielding for defining the pixel opening region may be performed separately by the first light shielding film 11a and the second light shielding film 23.

Further, in the present embodiment, a part or all of the pixel opening region may be defined by the first light shielding film 11a formed below the TFT 30. For example, the first light shielding film 11
By arranging a on the side of the barrier layer 80 in plan view in FIG. 2 or so as to slightly overlap with each other, the side along the scanning line 3a in the pixel opening region is formed by the first light-shielding film 11a and the barrier layer 80. Can be specified.

Particularly in this embodiment, as shown in FIGS. 2 and 3, the first contact hole 8a and the second contact hole 8b are opened at different plane positions on the TFT array substrate 10. ing. Therefore, the first contact hole 8a and the second contact hole 8
It is possible to avoid a situation in which the unevenness generated at the plane position where b is opened overlaps each other and the unevenness is amplified. Therefore, good electrical connection can be expected in these contact holes.

The planar shapes of the contact holes 8a, 8b and 5 may be circular, quadrangular or other polygonal shapes, but the circular shape is particularly useful for preventing cracks in the interlayer insulating film around the contact holes. Then, in order to obtain a good electrical connection, wet etching is performed after dry etching to remove these contact holes 8
It is preferable to slightly taper a, 8b, and 5, respectively.

(Manufacturing Process of First Embodiment of Electro-Optical Device) Next, the manufacturing process of the liquid crystal device in the embodiment having the above-mentioned configuration will be described with reference to FIGS.
Will be described with reference to. 4 to 7, the layers on the TFT array substrate side in each process are shown in FIG.
It is a process drawing shown corresponding to a section A-A '.

First, as shown in step (1) of FIG. 4, a TFT array substrate 10 such as a quartz substrate, a hard glass or a silicon substrate is prepared. Here, it is preferable to perform heat treatment at a high temperature of about 900 to 1300 ° C. in an atmosphere of an inert gas such as N ₂ (nitrogen), and to perform a TFT in a high temperature process performed later.
Pretreatment is performed so that the strain generated in the array substrate 10 is reduced. That is, the TFT array substrate 10 is previously prepared in accordance with the highest temperature in the manufacturing process and the high temperature.
Are heat-treated at the same temperature or higher. Then, a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal alloy film such as metal silicide is formed on the entire surface of the TFT array substrate 10 thus treated by sputtering or the like to have a thickness of about 100 to 500 nm. Thick, preferably about 20
A light shielding film 11 having a film thickness of 0 nm is formed. The light-shielding film 11
An antireflection film such as a polysilicon film may be formed on the surface of the film in order to reduce surface reflection.

Next, as shown in step (2), a resist mask corresponding to the pattern (see FIG. 2) of the first light shielding film 11a is formed on the formed light shielding film 11 by a photolithography process, and the resist is formed. Light-shielding film 11 through the mask
By etching the first light-shielding film 11a
To form.

Next, as shown in step (3), TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl) is formed on the first light-shielding film 11a by, for example, a normal pressure or low pressure CVD method.・ Boat rate) Gas, T
A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using MOP (tetramethyl oxyfoslate) gas or the like. The film thickness of the base insulating film 12 is, eg, about 500-2000 nm. If the return light from the back surface of the TFT array substrate 10 does not matter, it is not necessary to form the first light shielding film 11a.

Next, as shown in step (4), on the base insulating film 12, about 450 to 550 ° C., preferably about 500.
Flow rate of about 400-600cc /
An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using min monosilane gas or disilane gas. Then, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 1 is solid-phase grown to a thickness of about 50 to 200 nm, preferably about 100 nm by performing heat treatment for 4 to 6 hours. As a method for solid phase growth, RTA (Rapid Thermal Anneal)
al) or a laser heat treatment using an excimer laser or the like.

At this time, when an n-channel type pixel switching TFT 30 is prepared as the pixel switching TFT 30 shown in FIG. 3, S is formed in the channel region.
V such as b (antimony), As (arsenic), P (phosphorus)
The impurities of the group element may be slightly doped by ion implantation or the like. When the pixel switching TFT 30 is a p-channel type, impurities of a group III element such as B (boron), Ga (gallium) and In (indium) may be slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by the low pressure CVD method or the like to once make it amorphous and then recrystallizing it by heat treatment or the like.

Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed by a photolithography step, an etching step, and the like.

Next, as shown in the step (6), the semiconductor layer 1a constituting the pixel switching TFT 30 is covered with about 900.
By thermal oxidation at a temperature of ˜1300 ° C., preferably at a temperature of about 1000 ° C., a thermally oxidized silicon film 2a having a relatively thin thickness of about 30 nm is formed, and as shown in step (7), low pressure CVD is performed. Pixel switching having a multilayer structure including a thermally oxidized silicon film 2a and an insulating film 2b by depositing an insulating film 2b made of a high temperature silicon oxide film (HTO film) or a silicon nitride film to a relatively thin thickness of about 50 nm by a method or the like. A first dielectric film 2 for forming a storage capacitor is formed simultaneously with the insulating thin film 2 of the TFT 30 for use. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating thin film (first dielectric film) 2 has a thickness of about 20 to 150 nm. It will have a thickness, preferably about 30-100 nm. By shortening the high temperature thermal oxidation time in this way, it is possible to prevent warpage due to heat, particularly when a large substrate of about 8 inches is used. However, the insulating thin film 2 having a single layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Next, as shown in step (8), the resist layer 50 is formed by a photolithography process, an etching process, and the like.
0 is the semiconductor layer 1 excluding the portion to be the first storage capacitor electrode 1f
After being formed on a, for example, P ions are dosed at about 3 × 1.
The first storage capacitor electrode 1f may be made low in resistance by doping with 0 ¹² / cm ² .

Next, as shown in step (9), after removing the resist layer 500, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and then P is thermally diffused to form the polysilicon film 3.
Is made conductive. Alternatively, a doped polysilicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The film thickness of the polysilicon film 3 is about 100 to 500 n.
It is deposited to a thickness of m, preferably about 300 nm.

Next, as shown in step (10) of FIG. 5, the capacitance line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 2 by a photolithography process using a resist mask, an etching process and the like. . The scanning lines 3a and the capacitance lines 3b may be formed of a metal alloy film such as a refractory metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, first, in the semiconductor layer 1a, a low concentration source region 1b and a low concentration source region 1b are formed. In order to form the concentration drain region 1c, an impurity of a group V element such as P is used at a low concentration (for example, P ions are 1 to 3 × 10 ¹³ / cm 3) by using a gate electrode that is a part of the scanning line 3a as a mask. Dope (with a dose of ² ). As a result, the semiconductor layer 1a below the scanning line 3a becomes the channel region 1a '.

Next, as shown in step (12), the high-concentration source region 1d forming the pixel switching TFT 30.
In order to form the high-concentration drain region 1e, the resist layer 600 is formed on the scanning line 3a with a mask wider than the scanning line 3a, and then the impurity of the group V element such as P is also highly concentrated (for example, , P ion of 1 to 3 × 10 ¹⁵ / c
Dope (with a dose of m ² ). When the pixel switching TFT 30 is a p-channel type, in order to form the low concentration source region 1b and the low concentration drain region 1c and the high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, B, etc. Doping with impurities of Group III element. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a as a mask. The resistance of the capacitance lines 3b and the scanning lines 3a is further reduced by the doping of the impurities.

Incidentally, in parallel with the device forming process of these TFTs 30, an n-channel type TFT and a p-channel type TFT are formed.
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of may be formed in the peripheral portion on the TFT array substrate 10. As described above, if the semiconductor layer 1a forming the pixel switching TFT 30 is formed of the polysilicon film in the present embodiment, the peripheral circuit can be formed in almost the same step when the pixel switching TFT 30 is formed. It is advantageous.

Next, as shown in step (13), after removing the resist layer 600, the low pressure CVD method and the plasma CVD method are performed on the capacitance line 3b, the scanning line 3a and the insulating thin film (first dielectric film) 2. High temperature silicon oxide film (HTO
Film) or a first interlayer insulating film 81 made of a silicon nitride film.
It is deposited in a relatively thin thickness of 0 nm or more and 200 nm or less. However, as described above, the first interlayer insulating film 81 may be formed of a multi-layer film, and the first interlayer insulating film 81 may be formed by various known techniques generally used for forming an insulating thin film of a TFT. Can be formed. In the case of the first interlayer insulating film 81, the parasitic capacitance between the data line 6a and the scanning line 3a does not become large if it is made too thin as in the case of the second interlayer insulating film 4, and the insulating thin film in the TFT 30 is not increased. If it is made too thin as in No. 2, a peculiar phenomenon such as a tunnel effect does not occur. In addition, the first interlayer insulating film 81
Is the second storage capacitor electrode that is a part of the capacitor line and the barrier layer 8
Between 0, it functions as a second dielectric film. And the second
The thinner the dielectric film 81 is, the larger the second storage capacitance 70b is. Therefore, an extremely thin insulating film having a thickness of 50 nm or less, which is thinner than the insulating thin film 2, is eventually provided that defects such as film breakage do not occur. When the second dielectric film 81 is formed so as to have the above-described effect, the effect of the present embodiment can be enhanced.

Next, as shown in step (14), the contact hole 8a for electrically connecting the barrier layer 80 and the high-concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching. It is formed by etching. Since such dry etching has high directivity, the contact hole 8a having a small diameter can be formed. Alternatively, wet etching, which is advantageous for preventing the contact hole 8a from penetrating the semiconductor layer 1a, may be used together. This wet etching is also effective from the viewpoint of providing the contact hole 8a with a taper for better electrical connection.

Next, as shown in step (15), Ti, Cr, W, Ta, and Ta are formed on the entire surface of the high-concentration drain region 1e which is viewed through the first interlayer insulating film 81 and the contact hole 8a.
50 to 500 nm by depositing a metal such as Mo or Pb or a metal alloy film such as a metal silicide by sputtering.
A conductive film 80 'having a film thickness of about the same is formed. If the thickness is about 50 nm, there is almost no possibility of penetrating when the second contact hole 8b is opened later. The conductive film 8
On 0 ′, an antireflection film such as a polysilicon film may be formed to reduce surface reflection. Also, the conductive film 80 '
For relaxation of stress, a doped polysilicon film or the like may be used. At this time, the doped polysilicon film (conductive polysilicon film) is used as the lower layer and the metal film is used as the upper layer.
You may form the conductive film 80 'laminated | stacked by more layers. Further, a metal film may be sandwiched between two layers of polysilicon film to form three layers. As described above, when the conductive film 80 'and the high-concentration drain region 1e are electrically connected, if they are formed of the same polysilicon film, the contact resistance can be significantly reduced.

Next, as shown in step (16) of FIG. 6, a resist mask corresponding to the pattern of the barrier layer 80 (see FIG. 2) is formed on the formed conductive film 80 'by photolithography, and the resist mask is formed. Conductive film 8 through the resist mask
By etching 0 ', the barrier layer 80 including the third storage capacitor electrode is formed.

Next, as shown in the step (17), NS is applied so as to cover the first interlayer insulating film 81 and the barrier layer 80 by using, for example, a normal pressure or low pressure CVD method or TEOS gas.
A second interlayer insulating film 4 made of a silicate glass film such as G, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm. If the film thickness of the second interlayer insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a does not become a problem or a problem.

Next, in step (18), heat treatment at about 1000 ° C. is performed for about 20 minutes to activate the high concentration source region 1d and the high concentration drain region 1e, and then the contact hole 5 for the data line 6a is formed. To open a hole. Also,
Contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings (not shown) in the peripheral region of the TFT array substrate 10 can also be formed in the second interlayer insulating film 4 by the same process as the contact holes 5.

Next, as shown in step (19), a low-resistance metal such as Al having a light-shielding property, metal silicide, or the like is formed as a metal film 6 on the second interlayer insulating film 4 by sputtering or the like for about 100. ~ 500 nm thick, preferably about 300
nm.

Next, as shown in step (20), the data line 6 is formed by a photolithography process, an etching process and the like.
a is formed.

Next, as shown in step (21) of FIG. 7, for example, normal pressure or reduced pressure CV is provided so as to cover the data line 6a.
NSG, PSG, BS using D method or TEOS gas
A third interlayer insulating film 7 made of a silicate glass film such as G or BPSG, a silicon nitride film or a silicon oxide film is formed. The thickness of the third interlayer insulating film 7 is about 500 to 1500.
nm is preferred.

Next, as shown in step (22), the contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. Form. Alternatively, wet etching may be used to form a taper shape.

Next, as shown in step (23), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm, Further, as shown in step (24), the pixel electrode 9a is formed by a photolithography step, an etching step, and the like. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Then, after applying a coating liquid of a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3) is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and the second light-shielding film 23 and the third light-shielding film as a frame to be described later are sputtered with, for example, metallic chromium, and then the photomask is formed. It is formed through a lithography process and an etching process. The second and third light-shielding films are made of a metal material such as Cr, Ni, Al,
It may be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist. If the light-shielding region is defined on the TFT array substrate 10 by the data line 6a, the barrier layer 80, the first light-shielding film 11a, etc., the second light-shielding film 23 and the third light-shielding film on the counter substrate 20 can be omitted. it can.

Thereafter, a transparent conductive thin film of ITO or the like is formed on the entire surface of the counter substrate 20 by sputtering or the like in an amount of about 50 to 50.
By depositing to a thickness of 200 nm, the counter electrode 21
To form. Furthermore, after applying a coating liquid of a polyimide-based alignment film on the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

Finally, the T on which each layer was formed as described above.
The FT array substrate 10 and the counter substrate 20 are bonded together by a sealing material described later so that the alignment films 16 and 22 face each other, and by vacuum suction or the like, for example, a plurality of types of nematic liquid crystals are mixed in the space between the substrates. The liquid crystal thus formed is sucked to form a liquid crystal layer 50 having a predetermined thickness.

(Second Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. 8 and 9. Figure 8
T on which data lines, scanning lines, pixel electrodes, light-shielding films, etc. are formed
FIG. 9 is a plan view of a plurality of pixel groups adjacent to each other on the FT array substrate, and FIG. 9 is a cross-sectional view taken along the line BB ′ of FIG. 8. In addition, in the second embodiment shown in FIGS. 8 and 9, the same components as those in the first embodiment shown in FIGS. 2 and 3 are designated by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 9, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

8 and 9, unlike the first embodiment, in the second embodiment, the first light-shielding film 11b covers the scanning lines 3a, the capacitance lines 3b, and the data lines 6a when viewed from the TFT array substrate 10 side. That is, it is provided over the entire non-aperture area in the form of a lattice surrounding each pixel. Furthermore, the base insulating film 1
2 is provided with a contact hole 15 that electrically connects the capacitance line 3b and the first light shielding film 11b. The capacitance line 3b and the first light shielding film 11b are
It is connected to constant potential wiring. Other configurations are similar to those of the first embodiment.

Therefore, according to the second embodiment, the first light-shielding film 11b not only has the function of defining the pixel opening region and the function of the constant potential wiring or the redundant wiring of the capacitance line 3b, but also the capacitance line itself. It is possible to reduce the resistance and improve the image quality. According to this structure, it is possible to define the pixel opening region by the first light shielding film 11b alone. Further, the potentials of the capacitance line 3b and the first light-shielding film 11b can be set to the same constant potential, and the adverse effect on the image signal and the TFT 30 due to the potential fluctuation in the capacitance line 3b and the first light-shielding film 11b can be reduced. In addition, the first light shielding film 11b and the semiconductor layer 1a
It is possible to add a storage capacitor by using the base insulating film 12 interposed between the layers as a dielectric film.

If the first light-shielding film 11b is used as a capacitance line, the capacitance line 3 formed in the same step as the scanning line 3a is formed.
b may be provided in an island shape as a storage capacitor electrode for each pixel unit. With this configuration, it is possible to improve the pixel aperture ratio.

Incidentally, such a first light-shielding film 11b has a first
It can be formed by changing the pattern of the resist mask in the step (2) during the manufacturing process in the embodiment. Further, the contact hole 15 is formed by performing dry etching such as reactive ion etching or reactive ion beam etching or wet etching between step (8) and step (9) during the manufacturing process in the first embodiment. Open a hole.

(Third Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 10 shows the second
It is sectional drawing of 3rd Embodiment corresponding to BB 'cross section of the top view of FIG. 8 in embodiment. In the third embodiment shown in FIG. 10, the same components as those of the second embodiment shown in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 10, in order to make each layer and each member recognizable in the drawing, the scale is different for each layer and each member.

In FIG. 10, the third embodiment is different from the second embodiment in that the upper surface of the third interlayer insulating film 7'is formed flat. As a result, the third interlayer insulating film 7 '
The pixel electrode 9a and the alignment film 16 having the underlayer as a base film are also flattened. Other configurations are similar to those of the second embodiment.

Therefore, according to the third embodiment, the step difference between the region where the scanning line 3a, the TFT 30, the capacitance line 3b and the like are formed overlapping the data line 6a is reduced.
Since the pixel electrode 9a is flattened in this way,
The occurrence of disclination of the liquid crystal layer 50 can be reduced according to the degree of flattening. As a result, according to the third embodiment, it is possible to display a higher quality image and also to expand the pixel opening area.

The flattening of the third interlayer insulating film 7'as described above is performed by, for example, CMP (Chemical Mechanical Polish) at the step (21) in the manufacturing process of the first embodiment.
ing) treatment, spin coating treatment, reflow method or the like, or using organic SOG (Spin On Glass), inorganic SOG, polyimide film or the like. Since the barrier layer 80 is formed of a film having a high selection ratio even if the film thickness of the third interlayer insulating film 7'becomes thick for flattening as described above, it does not penetrate through the film during etching.

Fourth Embodiment of Electro-Optical Device A structure of a liquid crystal device which is a fourth embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 11 shows the second
It is sectional drawing of 4th Embodiment corresponding to BB 'cross section of the top view of FIG. 8 in embodiment. In the fourth embodiment shown in FIG. 10, the same components as those of the second embodiment shown in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 11, in order to make each layer or each member recognizable in the drawing, the scale is different for each layer or each member.

In FIG. 11, unlike the second embodiment, in the fourth embodiment, the upper surface of the TFT array substrate 10 ′ has a concave shape in the portion facing the data lines 6 a, the scanning lines 3 a and the capacitance lines 3 b. It is formed as a depression. As a result, the pixel electrode 9a and the alignment film 16 formed on the TFT array substrate 10 'via these wirings and the interlayer insulating film are also flattened. Other configurations are similar to those of the second embodiment.

Therefore, according to the fourth embodiment, the step difference between the region where the scanning line 3a, the TFT 30, the capacitance line 3b and the like are formed and the region where the scanning line 3a, the TFT 30, and the like are not formed is reduced. In this way, the pixel electrode 9a is substantially flattened only by filling at least a part of the non-opening area of the pixel, and the occurrence of disclination of the liquid crystal layer 50 can be reduced depending on the degree of flattening. As a result, according to the fourth embodiment, it is possible to display a higher quality image and also to expand the pixel opening area.

Incidentally, such a TFT array substrate 10 '
For example, before the step (1) in the manufacturing process of the first embodiment, etching may be performed on the region where the concave recess is to be formed.

As described above, in the third embodiment, the upper surface of the third interlayer insulating film is flattened, and in the fourth embodiment, the wiring and the element portion are formed by finally forming the groove on the substrate in a concave shape. Although the pixel electrode is flattened, the same flattening effect can be obtained by forming the second interlayer insulating film 4 or the base insulating film 12 in a concave shape. In this case, as a method of forming each interlayer insulating film in a concave shape, each interlayer insulating film has a two-layer structure, a thin portion consisting of only one layer is a concave depression portion, and a two-layer thick portion is a concave bank portion. Thus, thin film formation and etching may be performed. Alternatively, each interlayer insulating film may have a single-layer structure, and the concave recess may be opened by etching. In these cases, the use of dry etching such as reactive ion etching or reactive ion beam etching has the advantage that the recessed portion can be formed according to the design dimension. On the other hand, when at least at least wet etching is used alone or in combination with dry etching, the side wall surface of the concave depression can be formed in a tapered shape.
Since it is possible to reduce the residue of the polysilicon film, the resist and the like formed in the recesses in the recesses around the sidewalls in the subsequent step, it is possible to obtain the advantage that the yield is not reduced.

(Fifth Embodiment of Electro-Optical Device) A liquid crystal device as a fifth embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 12 shows a fifth embodiment corresponding to the AA ′ sectional view of FIG. 2 in the first embodiment.
It is sectional drawing of embodiment. Note that, in the fifth embodiment shown in FIG. 12, the same components as those in the first embodiment are designated by the same reference numerals, the description thereof will be omitted, and only the points different from the first embodiment will be described.

In the fifth embodiment, the second contact hole 8b for electrically connecting the barrier layer 80 and the pixel electrode 9a is formed on the capacitance line 3b. By thus forming the second contact hole 8b on the capacitance line 3b, the area under the region of the second contact hole 8b can also function as a capacitance, and the capacitance can be increased accordingly.

(Overall Configuration of Electro-Optical Device) The overall configuration of a liquid crystal device, which is an example of the electro-optical device in each of the above-described embodiments, will be described with reference to FIGS. 13 and 14. 13 is a plan view of the TFT array substrate 10 together with the constituent elements formed thereon as seen from the side of the counter substrate 20, and FIG. 14 is a sectional view taken along line HH 'of FIG.

In FIG. 13, the sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel with the inside thereof, for example, is made of the same or different material as the second light shielding film 23. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. In the area outside the sealing material 52, the data line drive circuit 101 and the external circuit connection terminal 1 for driving the data line 6a by supplying the image signal to the data line 6a at a predetermined timing.
02 is provided along one side of the TFT array substrate 10, and the scanning line driving circuit 10 drives the scanning line 3a by supplying the scanning signal to the scanning line 3a at a predetermined timing.
4 are provided along two sides adjacent to this one side. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line 3a does not matter. In addition, the data line drive circuit 10
1s may be arranged on both sides along the side of the image display area.
For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines 6a extend along the opposite side of the image display area. The image signal may be supplied from the data line driving circuit arranged as described above. By thus driving the data lines 6a in a comb shape, the occupied area of the data line driving circuit can be expanded, and a complicated circuit can be configured. Furthermore, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the image display area are provided. In addition, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20. Then, as shown in FIG.
Counter substrate 2 having substantially the same contour as the sealing material 52 shown in FIG.
0 is fixed to the TFT array substrate 10 by the sealing material 52. On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of data lines. 6
Even if a precharge circuit for supplying a precharge signal of a predetermined voltage level to a is supplied respectively to the image signal a, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or shipping, Good. According to the present embodiment,
The second light-shielding film 23 on the counter substrate 20 is the TFT array substrate 1
It may be formed smaller than the light-shielding region of 0. Further, the second light shielding film 23 can be easily removed depending on the application of the liquid crystal device.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding). The drive LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Further, for example, TN (Twisted) is provided on the side on which the projection light of the counter substrate 20 is incident and on the side on which the emission light of the TFT array substrate 10 is emitted.
Nematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction according to an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

The electro-optical device in each of the embodiments described above is applied to a color display projector or the like, and therefore three electro-optical devices are used as light valves for R (red) G (green) B (blue). The light of each color, which is respectively used and is separated through the dichroic mirror for RGB color separation, is incident on each light valve as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, the second
An RGB color filter may be formed on the counter substrate 20 together with its protective film in a predetermined region facing the pixel electrode 9a where the light shielding film 23 is not formed. Or TF
It is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the T array substrate 10. With this configuration, the electro-optical device according to each embodiment can be applied to a direct-view type or reflective type color liquid crystal television other than the projector. Further, the counter substrate 20
A microlens may be formed so that one pixel corresponds to one pixel. By doing so, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that creates RGB colors may be formed by utilizing interference of light by depositing a number of interference layers having different refractive indexes on the counter substrate 20. With this counter substrate with a dichroic filter, a brighter color electro-optical device can be realized.

In the electro-optical device according to each of the embodiments described above, the incident light is incident from the counter substrate 20 side as in the conventional case, but since the first light shielding film 11a is provided, the TFT array substrate 10 is provided. Incident light from the side of
The light may be emitted from the counter substrate 20 side. That is, even when the electro-optical device is attached to the liquid crystal projector as described above, it is possible to prevent light from entering the channel region 1a ′, the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a. It is possible to display the image of. Here, conventionally, the TFT array substrate 1
In order to prevent reflection on the back side of 0,
Although it was necessary to separately dispose a polarizing plate coated with R (Anti Reflection) or to attach an AR film, in each embodiment, the surface of the TFT array substrate 10 and the semiconductor layer 1a are formed.
Of the first light-shielding film 11 between at least the channel region 1a ′, the low-concentration source region 1b, and the low-concentration drain region 1c.
Since a is formed, such an AR-coated polarizing plate or AR film is used, or the TFT array substrate 10 is used.
It is not necessary to use a substrate whose AR is processed. Therefore, according to each of the embodiments, the material cost can be reduced, and when the polarizing plate is attached, the yield is not lowered due to dust or scratches, which is very advantageous. Further, since the light resistance is excellent, even if the light utilization efficiency is improved by using a bright light source or polarization conversion by the polarization beam splitter, image deterioration such as crosstalk due to light does not occur.

Although the switching element provided in each pixel is described as a positive stagger type or coplanar type polysilicon TFT, it is an inverse stagger type TFT.
The respective embodiments are also effective for other types of TFTs such as and amorphous silicon TFTs.

(Electronic Device) Next, an embodiment of an electronic device including the electro-optical device 100 described in detail above will be described with reference to FIGS.

First, FIG. 15 shows the electro-optical device 1 thus constructed.
1 shows a schematic configuration of an electronic device including 00.

In FIG. 15, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, electro-optical device 100, clock generation circuit 100
8 and a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Memory).
y), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like, and displays an image signal in a predetermined format based on the clock signal from the clock generation circuit 1008. The information is output to the display information processing circuit 1002. The display information processing circuit 1002 includes an amplification / polarity inversion circuit, a serial-
It is configured to include various well-known processing circuits such as a parallel conversion circuit, rotation circuit, gamma correction circuit, and clamp circuit. It sequentially generates digital signals from the display information input based on the clock signal, and along with the clock signal CLK. It outputs to the drive circuit 1004. Drive circuit 1004
Drives the electro-optical device 100. Power supply circuit 1010
Supplies a predetermined power to each of the above circuits. The driving circuit 1004 may be mounted on the TFT array substrate that constitutes the electro-optical device 100, and in addition to this, the display information processing circuit 1002 may be mounted.

Next, FIG. 16 to FIG. 17 show specific examples of the electronic apparatus configured as described above.

In FIG. 16, in the projector 1100 which is an example of an electronic device, the above-mentioned drive circuit 1004 is TF.
Three light valves including the electro-optical device 100 mounted on the T-array substrate are prepared, and the light valves 100R, 100G, and 100B for RGB are used as projectors. In the projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, the three mirrors 1
106 and two dichroic mirrors 1108 divide the light components R, G, and B corresponding to the three primary colors of RGB into the light valves 100R and 100G corresponding to the respective colors.
And 100B respectively. At this time, in particular, the B light is incident on the incident lens 1122, in order to prevent light loss due to a long optical path.
It is guided through a relay lens system 1121 including a relay lens 1123 and an emission lens 1124. Then, the light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.

In FIG. 17, a laptop personal computer (PC) 1200 compatible with multimedia, which is another example of an electronic apparatus, is the electro-optical device 10 described above.
0 is provided in the top cover case, and CP
A keyboard 12 for accommodating U, memory, modem, etc.
The main body 1204 in which 02 is incorporated is provided.

In addition to the electronic devices described with reference to FIGS. 16 to 17, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, an engineering A workstation (EWS), a mobile phone, a videophone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices equipped with the electro-optical device having high manufacturing efficiency and capable of displaying high-quality images.

The invention of this embodiment will be described below.

In the first electro-optical device of the present invention, a plurality of scanning lines and a plurality of data lines, a thin film transistor connected to the scanning line and the data line, a pixel electrode connected to the thin film transistor, and An electro-optical device having a storage capacitor, comprising: a first interlayer insulating film formed above one electrode of the scanning line and the storage capacitor; and a conductive layer formed above the first interlayer insulating film. And a second interlayer insulating film formed above the conductive layer, and the data line is formed on the second interlayer insulating film.

According to the first electro-optical device of the present invention, one electrode of the scanning line and the storage capacitor, the first interlayer insulating film, the conductive layer, the second interlayer insulating film, and the data line are formed in this order on the substrate. ing. Therefore, the conductive layer interposed as a layer between the scan line and the data line can be used for various purposes. For example, first, by electrically connecting the conductive layer and the semiconductor layer through the first contact hole and electrically connecting the conductive layer and the pixel electrode through the second contact hole, the conductive layer is connected through the conductive layer. It is possible to electrically connect the semiconductor layer and the pixel electrode. Alternatively, a storage capacitor is provided to the pixel electrode by using a part of the conductive layer as another storage capacitor electrode facing a part of the semiconductor layer or one electrode of the storage capacitor via the dielectric film. Configuration is also possible. Alternatively, by forming the conductive layer from a light-shielding film, a structure in which at least a part of the opening region of the pixel is defined by the conductive layer is also possible. Furthermore, a structure in which a data line, a scanning line, or another wiring other than the capacitance line for forming one electrode of the storage capacitor is formed from the conductive layer, and the data line, the scanning line, and the capacitance line are redundant from the conductive layer. A configuration in which wiring is formed is also possible.

According to one aspect of the first electro-optical device of the present invention, the substrate is further provided with a third interlayer insulating film formed above the data line, and the pixel electrode is The conductive layer is electrically connected to the conductive layer through a contact hole formed on the third interlayer insulating film and formed in the second and third interlayer insulating films, and the conductive layer is connected to the semiconductor layer. It is electrically connected.

According to this structure, the pixel electrode is formed above the data line via the third interlayer insulating film,
The pixel electrode is electrically connected to the conductive layer through a contact hole formed in the second and third interlayer insulating films,
The conductive layer is connected to the semiconductor layer. Therefore, a structure in which the semiconductor layer and the pixel electrode are electrically connected via the conductive layer can be obtained.

In a second electro-optical device according to the present invention, a plurality of scanning lines and a plurality of data lines, a thin film transistor connected to each scanning line and each data line, and a pixel connected to the thin film transistor are provided on a substrate. An electrode, a semiconductor layer forming a source region and a drain region of the thin film transistor, and a first storage capacitor electrode, an insulating thin film formed on the semiconductor layer, and the scanning line formed on the insulating thin film A gate electrode of the thin film transistor, which is a part of the first thin film transistor, a second storage capacitor electrode of the storage capacitor formed on the insulating thin film, and a first electrode formed above the scanning line and the second storage capacitor electrode. The data line includes an interlayer insulating film, a conductive layer formed above the first interlayer insulating film, and a second interlayer insulating film formed above the conductive layer. Through the insulating film and contact holes formed in the first and second interlayer insulating films while being formed on the second interlayer insulating film, and is electrically connected to the source region of the semiconductor layer.

According to the second electro-optical device of the present invention, the scanning line and the second storage capacitor electrode, the first interlayer insulating film,
The conductive layer, the second interlayer insulating film, and the data line are formed in this order, and the pixel electrode is further formed thereabove. The data line is electrically connected to the source region of the semiconductor layer via the contact hole formed in the first and second interlayer insulating films. In addition to these, a source region and a drain region are formed from a part of the semiconductor layer,
A gate insulating film of a thin film transistor is formed from a part of the insulating thin film, and a gate electrode of the thin film transistor including a part of a scanning line is formed on the insulating thin film. On the other hand, part of the semiconductor layer constitutes the first storage capacitor electrode, part of the insulating thin film constitutes the dielectric film of the storage capacitor, and further part of the capacitance line is formed on the insulating thin film. The second storage capacitor electrode is formed. Therefore, the thin film transistor is arranged below the scan line, and the thin film transistor is arranged next to the second line.
A structure in which the storage capacitor is arranged below the storage capacitor electrode is obtained. Therefore, in the structure in which such a storage capacitor is provided in parallel with the thin film transistor, the conductive layer interposed as a layer between the scanning line and the data line can be used for various purposes. For example, first, a part of the conductive layer is
By forming the third storage capacitor electrode which faces the storage capacitor electrode via the first interlayer insulating film, that is, the first interlayer insulating film serves as a dielectric film of the storage capacitor at this portion and a part of the conductive layer and the second layer. By arranging the storage capacitor electrodes so as to face each other, it is possible to provide a structure in which a storage capacitor is additionally provided (in addition to the storage capacitor composed of the first storage capacitor electrode and the second storage capacitor electrode) to the pixel electrode. Alternatively, the first aspect of the present invention described above.
Similar to the case of the electro-optical device, a configuration in which the semiconductor layer and the pixel electrode are electrically connected via the conductive layer, a configuration in which at least a part of the opening region of the pixel is defined by the conductive layer, and the data line from the conductive layer It is also possible to form a scan line, another wiring except the capacitance line for forming the second storage capacitor, or a redundant wiring thereof.

According to one aspect of the second electro-optical device of the present invention, the conductive layer is formed in the drain region of the semiconductor layer through a contact hole formed in the first interlayer insulating film and the insulating thin film. It is electrically connected.

According to this structure, the data line is electrically connected to the source region of the semiconductor layer through the contact hole formed in the insulating thin film and the first and second interlayer insulating films, and the data line is electrically conductive. The layer is electrically connected to the drain region of the semiconductor layer through a contact hole formed in the first interlayer insulating film and the insulating thin film. Therefore, it is possible to easily use the conductive layer as an electrode of the storage capacitor connected to the pixel electrode, and at the same time, to easily connect the pixel electrode and the drain region via the conductive layer. It becomes possible.

According to another aspect of the second electro-optical device of the present invention, the substrate is further provided with a third interlayer insulating film formed above the data lines, and the pixel electrodes are It is formed on the third interlayer insulating film and is electrically connected to the conductive layer through the contact holes formed in the second and third interlayer insulating films.

According to this structure, the pixel electrode is formed above the data line via the third interlayer insulating film,
The pixel electrode is electrically connected to the conductive layer through a contact hole formed in the second and third interlayer insulating films. Therefore, a configuration in which the pixel electrode and the drain region are electrically connected via the conductive layer can be easily made possible.

In the third electro-optical device of the present invention, a plurality of pixel electrodes and thin film transistors arranged in a matrix on the substrate, and scanning which is connected to the thin film transistors and three-dimensionally intersects with each other through the interlayer insulating film. Line and data line, interposed between the semiconductor layer forming the thin film transistor and the pixel electrode, electrically connected to the drain region of the semiconductor layer through the first contact hole, and connected to the pixel electrode and the second electrode. Between a conductive layer electrically connected through a contact hole, a first storage capacitor electrode made of the same film as the semiconductor layer portion, and a second storage capacitor electrode arranged on the first storage capacitor electrode. An intervening first dielectric film,
A third electrode composed of the second storage capacitor electrode and a part of the conductive layer;
A second dielectric film interposed between the storage capacitor electrode and the storage capacitor electrode.

According to the third electro-optical device of the present invention, the plurality of scanning lines and the plurality of data lines are three-dimensionally intersected with each other through the interlayer insulating film on the substrate, and the storage capacitors are stored in the plurality of pixel electrodes. A second storage capacitor electrode for adding each of these is separately provided. The conductive layer is interposed between the semiconductor layer and the pixel electrode, is electrically connected to the drain region of the semiconductor layer through the first contact hole, and is electrically connected to the pixel electrode on the other hand. It is electrically connected through two contact holes. Therefore, the diameter of the contact hole can be reduced as compared with the case where one contact hole is opened from the pixel electrode to the drain region. In other words, the deeper the contact hole is, the lower the etching accuracy becomes. Therefore, in order to prevent punch-through in a thin semiconductor layer, the dry etching that can reduce the diameter of the contact hole is stopped halfway, and finally the semiconductor is wet etched. The process must be arranged to open up to the layers. For this reason, the diameter of the contact hole cannot but be widened by wet etching having no directivity. On the other hand, in the present invention, since the pixel electrode and the drain region of the semiconductor layer may be connected by two series of first and second contact holes, it is possible to open each contact hole by dry etching. Or, at least it becomes possible to shorten the distance of opening by wet etching. As a result, the diameters of the first and second contact holes can be made smaller, and the depressions and irregularities formed on the surface of the conductive layer in the first contact holes can be made smaller, so that the pixel electrode portion located thereabove can be flattened. Is promoted. Furthermore, since the depressions and irregularities formed on the surface of the pixel electrode in the second contact hole can be small, planarization in this pixel electrode portion is promoted. As a result, defects such as disclination in the electro-optical material such as liquid crystal due to the depressions and irregularities on the surface of the pixel electrode are reduced.

Further, a first storage capacitor electrode in which the first dielectric film is made of the same film as the semiconductor layer portion forming the drain region of the semiconductor layer, and a second storage capacitor electrode arranged on the first storage capacitor electrode. The first storage capacitor is added to the pixel electrode electrically connected to the drain region of the semiconductor layer by these three elements. In addition to this, since the second dielectric film is interposed between the second storage capacitor electrode and the third storage capacitor electrode formed of a part of the conductive layer, the third storage capacitor causes the second storage capacitor to act as a pixel electrode. Is added. Therefore, the first and second layers connected in parallel above and below the conductive layer as the center.
Storage capacity is formed. In this way, it is possible to construct a three-dimensional storage capacitor in the limited area on the substrate. Here, in particular, each of the first and second dielectric films is made of a dielectric film in a layer different from the second interlayer insulating film interposed between the scanning line and the data line that three-dimensionally intersect each other. Therefore, in order to suppress the parasitic capacitance between the scanning line and the data line which causes the voltage drop of the image signal which causes flicker and the like, a constant thickness is required regardless of the thickness of the second interlayer insulating film. It is possible to make the first and second dielectric films as thin as the technical limit. If the barrier layer (corresponding to the conductive layer in the present invention) is composed of the same conductive layer as the data line, the barrier layer is used as one electrode of the storage capacitor to scan the data line and the scanning line. Assuming that an interlayer insulating film between lines is used as a dielectric film, this dielectric film needs to have a thickness of about 800 nm so that the parasitic capacitance between the data line and the scanning line does not become a problem. Therefore, it is fundamentally difficult to construct a large-capacity storage capacitor using the barrier layer. On the other hand, according to the present invention, by using a dielectric film that can be made thin, it is possible to extremely efficiently increase the capacitance value of the storage capacitor that is inversely proportional to the thickness of the dielectric film.

Furthermore, since the diameter of the first contact hole can be further reduced by forming the dielectric film thin as described above, the depressions and irregularities of the conductive layer in the first contact hole can be further reduced. The planarization of the pixel electrode located thereabove is further promoted. Therefore, the defects of the electro-optical material due to the depressions and irregularities in the pixel electrode are reduced, and finally, it becomes possible to display a higher quality image.

In the structure of the present invention, instead of or in addition to the function of adding the storage capacitance in the conductive layer, the light shielding function in the conductive layer, the layout of the contact holes, etc. are emphasized, and the conductive layer and the second dielectric film are formed. When forming up to the scanning line, the second dielectric film may be formed thick enough to cause no problem with the parasitic capacitance between the conductive layer and the scanning line. Therefore, in this case, it is difficult to increase the storage capacity by making the second dielectric film as thin as the technical limit as described above. However, if a sufficient storage capacity can be added according to the device specifications, it is not necessary to make the second dielectric film thinner, so that other additional functions such as the light-shielding function of the conductive layer are promoted accordingly. It is advantageous for the electro-optical device as a whole to be configured as described above. In short, in consideration of the specific device specifications, the conductive layer is used so that the original relay function, the function of adding the necessary storage capacity, and other additional functions such as the light-shielding function can be sufficiently exerted. The plane layout of the conductive layer, the thickness of the second dielectric film, etc. may be set.

In one aspect of the third electro-optical device of the present invention, at least a part of the first storage capacitor electrode and the second storage capacitor electrode overlap each other with the first dielectric film interposed therebetween in plan view, At least a part of the second storage capacitor electrode and the third storage capacitor electrode may overlap with each other with the second dielectric film interposed therebetween.

According to this structure, the first and third storage capacitor electrodes are formed in parallel above and below the second storage capacitor electrode with the center as the center. In this way, it is possible to construct a three-dimensional storage capacitor in the limited area on the substrate.

In one aspect of the third electro-optical device of the present invention, the first dielectric film and the insulating thin film are made of the same film, and the scanning line and the second storage capacitor electrode are made of the same film. The second interlayer insulating film is formed on the scan line and the conductive layer.

According to this structure, since the first dielectric film and the insulating thin film of the thin film transistor are made of the same film, these insulating films can be formed in the same process, and the scanning line and the second storage capacitor electrode are made of the same film. Therefore, these conductive films can be formed in the same step. The second interlayer insulating film is formed on the scanning line and the conductive layer, and the data line is further formed thereon. Therefore, the first and second dielectric films can be formed thin to increase the storage capacitance, and at the same time, the second interlayer insulating film can be formed thick to reduce the parasitic capacitance between the scan line and the data line. As a result, it is possible to display a high-quality image using a relatively simple structure.

In another aspect of the third electro-optical device of the present invention, the first interlayer insulating film and the second dielectric film are the same film.

With this structure, it is possible to form the first interlayer insulating film and the second dielectric film in the same step,
It is advantageous without increasing the number of steps.

In another aspect of the first, second or third electro-optical device of the present invention, the conductive layer is made of a conductive light shielding film.

According to this structure, each pixel opening region can be defined at least partially by the conductive layer formed of the conductive light-shielding film. Thus, not the light-shielding film formed on the other substrate (usually the counter substrate), but a part or all of the built-in light-shielding film (that is, the conductive layer formed of the light-shielding film) on the substrate (usually the TFT array substrate). The configuration provided is extremely advantageous in that the pixel aperture ratio does not decrease due to the positional deviation between the substrate and the counter substrate in the manufacturing process.

In a mode in which the conductive layer is a light-shielding film, the conductive layer extends along the scanning line between the data lines whose planar shapes on the substrate are adjacent to each other, and is formed in an island shape for each pixel electrode. It may have been done.

By thus forming the conductive layer in an island shape, not only the influence of the stress of the film forming the conductive layer can be reduced, but also a part or all of the side along the scanning line of the pixel opening region is formed into the conductive layer. It becomes possible to specify by. In particular, when the parasitic capacitance between the scan line and the conductive layer becomes a problem depending on the specific circuit design, without providing a conductive layer on the scan line,
It is preferable that the side of the pixel opening region along the scanning line on the side where the capacitance line and the pixel electrode are adjacent to each other be defined by the conductive layer.

In the aspect in which the island-shaped light-shielding film is provided as a conductive layer, the adjacent data lines and the conductive layer may be configured to at least partially overlap each other when seen in a plan view.

According to this structure, there is no need to form a light-transmitting gap between the end of the island-shaped conductive layer in plan view and the edge of the data line. That is, if the edge portion of the data line and the end portion of the conductive layer are coincident with or slightly overlap with each other, it is possible to prevent display defects such as light leakage in this portion.

In the mode in which the above-mentioned conductive layer is made of a light shielding film,
The conductive layer may be formed so as to overlap the scanning line when seen in a plan view.

According to this structure, the side of the pixel opening region along the scanning line can be defined by the conductive layer formed of the light shielding film that at least partially covers both the scanning line and the capacitance line. .

In the mode in which the conductive layer is composed of the light shielding film,
The conductive layer may include a refractory metal.

According to this structure, it is possible to prevent the conductive layer from being destroyed or melted by the high temperature treatment performed after the step of forming the conductive layer made of the light shielding film. For example, the light-shielding film is an opaque refractory metal such as Ti, Cr (chrome), W (tungsten), Ta (tantalum), and Mo.
It is composed of a simple metal, an alloy, a metal silicide or the like containing at least one of (molybdenum) and Pb (lead).

In another aspect of the first, second or third electro-optical device of the present invention, the conductive layer is composed of a conductive polysilicon film.

According to this structure, the conductive layer made of a conductive polysilicon film does not function as a light-shielding film, but can sufficiently function as a storage capacitor and a relay function. In this case, stress due to heat or the like is unlikely to occur between the conductive film and the interlayer insulating film, which helps prevent cracks in the conductive layer and its periphery.

In another aspect of the first, second or third electro-optical device of the present invention, the conductive layer is composed of a laminated film of two or more layers of a conductive polysilicon film and a refractory metal. There is.

According to this structure, the conductive layer made of a conductive polysilicon film does not function as a light-shielding film, but can sufficiently function as a storage capacitor and a relay function. If the same polysilicon film is used to electrically connect the semiconductor layer and the conductive polysilicon film, the contact resistance can be significantly reduced.
Further, when a refractory metal is laminated on such a conductive polysilicon film, the function as a light-shielding film can be exerted and the resistance can be further reduced.

In another aspect of the first, second or third electro-optical device of the present invention, it is provided on the substrate at a position that respectively covers at least the channel region of the semiconductor layer when viewed from the substrate side. A light shielding film is further provided.

According to this structure, due to the light shielding film provided on the side closer to the substrate than the thin film transistor, that is, on the lower side of the thin film transistor, the return light from the substrate side is reflected in the channel region of the thin film transistor and LDD (Lightly Doped Drain).
It is possible to prevent the incident on the region, and it is possible to prevent the characteristics of the thin film transistor from being changed or deteriorated due to the generation of photocurrent due to the incident current. Then, it is possible to define a part or the whole of the pixel opening region by this light shielding film.

In the aspect including the light shielding film, at least the light shielding film may be extended below the scanning line and connected to the constant potential source.

According to this structure, it is possible to prevent the potential of the light-shielding film from fluctuating and the characteristics of the thin film transistor provided above the light-shielding film via the base insulating film from changing or deteriorating.

Alternatively, in the aspect including the light-shielding film, the light-shielding film is provided with the second storage capacitor through a contact hole formed in the base insulating film interposed between the light-shielding film and the semiconductor layer. It may be electrically connected to the electrodes.

According to this structure, the potentials of the second storage capacitor electrode and the light shielding film can be made the same, and if one of the second storage capacitor electrode and the light shielding film is set to a predetermined potential,
The other potential can also be a predetermined potential. At that time, if the light-shielding film is a capacitance line, the second storage capacitance electrode is connected to the capacitance line, and a constant potential can be applied to the second storage capacitance electrode. As a result, it is possible to reduce adverse effects due to potential fluctuations in the second storage capacitor electrode and the light shielding film.

In another aspect of the third electro-optical device of the present invention, the second storage capacitor electrode is extended and is a capacitor line.

According to this structure, the potential of the capacitance line can be made constant and the potential of the second storage capacitance electrode can be stabilized. At that time, the capacitance line and the scanning line can be formed of the same film.

In another aspect of the third electro-optical device of the present invention, the capacitance line is electrically connected to the light shielding film through the base insulating film.

According to this structure, the potentials of the capacitance line and the light-shielding film can be made the same, and if one of the capacitance line and the light-shielding film is set to the predetermined potential, the other potential can also be set to the predetermined potential. As a result, it is possible to reduce adverse effects due to potential fluctuations in the capacitance line and the light shielding film. Further, the wiring formed of the light shielding film and the capacitance line can function as a redundant wiring mutually.

In another aspect of the third electro-optical device of the present invention, the conductive layer and the light-shielding film may be overlapped at least partially in a plan view.

According to this structure, since the conductive layer and the light-shielding film are formed so as to sandwich the channel region of the semiconductor layer, it is possible to prevent light from entering the channel region from the substrate side and light from the other side. Can be prevented. As a result, it is possible to prevent the characteristics of the thin film transistor from changing or deteriorating, and it is possible to prevent the occurrence of crosstalk, the decrease of the contrast ratio, and the deterioration of the flicker level.

In another aspect of the first, second or third electro-optical device of the present invention, a base insulating film is provided between the substrate and the thin film transistor, and above the data line and below the pixel electrode. At least one of the substrate, the base insulating film, the second interlayer insulating film, and the third interlayer insulating film, the thin film transistor, the scanning line, and the data line. , And at least a part of the region corresponding to the storage capacitor is concavely formed, so that the underlying surface of the pixel electrode is substantially flattened.

According to this structure, at least one of the substrate and the plurality of interlayer insulating films is a thin film transistor,
Since at least a part of the scan line, the data line, and the region corresponding to the storage capacitor is formed to be recessed in a concave shape, a region where the thin film transistor, the scan line, the storage capacitor, and the like are formed over the data line and another region The steps are reduced. Since the lower surface of the pixel electrode is substantially flattened in this manner, the pixel electrode can be further flattened, and the disclination or the like in the electro-optical material such as liquid crystal caused by the depressions and irregularities on the pixel electrode surface can be achieved. Defects are reduced, and finally high-quality image display becomes possible.

In another aspect of the third electro-optical device of the present invention, the first contact hole and the second contact hole are opened at different plane positions on the substrate.

Since the conductive layer in the plane position where the first contact hole is opened has some depressions and protrusions,
If the second contact hole is opened directly above this, the unevenness is amplified, and it becomes difficult to establish good electrical connection. Therefore, if the two plane positions are slightly displaced as in this aspect, good electrical connection can be expected.

In another aspect of the first, second or third electro-optical device of the present invention, the conductive layer has a thickness of 50 nm or more and 5 or more.
It is not more than 00 nm.

According to this structure, the thickness of the conductive layer is
Since the thickness is 50 nm or more and 500 nm or less, there is little or no adverse effect due to the step on the surface of the pixel electrode due to the presence of the conductive layer (for example, liquid crystal misalignment) or an interlayer insulating film or the like located above the conductive layer. By the flattening process in step 2, it is possible to remove the influence of such a step. In addition, it is possible to obtain various benefits by the conductive layer as described above, while reducing the harmful effects of the conductive layer.

In another aspect of the second electro-optical device of the present invention, the film thickness of the first interlayer insulating film is 10 nm or more and 200 n or more.
m or less.

According to this structure, the thickness of the first interlayer insulating film is 10 nm or more and 200 nm or less, which is a relatively thin insulating film. Therefore, using this first interlayer insulating film as a dielectric film, as described above, an additional storage capacitor is formed by arranging the second storage capacitor electrode and the conductive layer so as to face each other with the first interlayer insulating film interposed therebetween. By constructing, a large storage capacity can be obtained according to this thinness.

In another aspect of the third electro-optical device of the present invention, the film thickness of the second dielectric film is 10 nm or more and 200 n or more.
m or less.

According to this structure, the thickness of the second dielectric film is 10 nm or more and 200 nm or less, which is a relatively thin insulating film. Therefore, the storage capacitance formed by disposing the second storage capacitance electrode and the third storage capacitance electrode facing each other with the second dielectric film interposed therebetween becomes large according to the thinness.

In the aspect in which the conductive layer of the present invention is a light-shielding film, the conductive layer may define at least a part of the opening region of the pixel.

According to this structure, it is possible to define the opening area of the pixel by the conductive layer alone or with the data line or the light shielding film formed on the other substrate. In particular, if the opening region is defined without forming a light-shielding film on the other substrate, it is possible to reduce the number of steps in the manufacturing process, and also to prevent the pixel aperture ratio from decreasing or varying due to misalignment between the pair of substrates. It is possible and advantageous.

In order to solve the above-mentioned problems, the method of manufacturing an electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, a thin film transistor connected to the scanning line and the data line, and a thin film transistor connected to the thin film transistor. In the method of manufacturing an electro-optical device having a pixel electrode and a storage capacitor, a semiconductor layer serving as a source region, a channel region and a drain region of the thin film transistor and a first storage capacitor electrode of the storage capacitor is formed on a substrate. A step of forming an insulating thin film on the semiconductor layer, a step of forming the scanning line and a second storage capacitor electrode of the storage capacitor on the insulating thin film, and a step of forming a second storage capacitor electrode on the second storage capacitor electrode. Forming a first interlayer insulating film; forming a first contact hole in the gate insulating film and the first interlayer insulating film; Forming a conductive layer on the first interlayer insulating film so as to be electrically connected to the semiconductor layer through a hole; forming a second interlayer insulating film on the conductive layer; 2 forming the data line on the interlayer insulating film, forming the third interlayer insulating film on the data line, and forming the second contact hole in the second and third interlayer insulating films. And a step of forming a pixel electrode so as to be electrically connected to the conductive layer through the second contact hole.

According to the method of manufacturing an electro-optical device of the present invention, it can be manufactured by using relatively simple steps.

In one aspect of the method of manufacturing an electro-optical device of the present invention, a step of forming a light shielding film in a region of the substrate facing the channel region, and a step of forming a base insulating film on the light shielding film. And further, in the step of forming the semiconductor layer, the semiconductor layer is formed on the base insulating film.

According to this structure, the electro-optical device having the light-shielding film provided on the lower side of the thin film transistor can be manufactured with a relatively small number of steps and relatively simple steps.

In one aspect of the method of manufacturing an electro-optical device of the present invention, at least one of the substrate, the base insulating film, the second interlayer insulating film and the third interlayer insulating film is the thin film transistor and the scanning line. , The data line and at least a part of the region corresponding to the storage capacitor are depressed.

According to this aspect, the lower surface of the pixel electrode can be flattened by forming a part of the region corresponding to the thin film transistor, the scanning line, the data line, and the storage capacitor in a concave shape. It is possible to reduce defects such as a liner.

[0179]

As described above, according to the electro-optical device of the present invention, the storage capacity can be increased by using a relatively simple structure even if the pixel pitch is made fine.

[Brief description of drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, etc. provided in a plurality of pixels in a matrix forming an image display region in a liquid crystal device which is a first embodiment of an electro-optical device.

FIG. 2 is a data line in the liquid crystal device of the first embodiment,
FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which scanning lines, pixel electrodes, light-shielding films, etc. are formed.

FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 4 is a process chart (1) sequentially showing a manufacturing process of the liquid crystal device of the first embodiment.

FIG. 5 is a process chart (No. 2) sequentially showing the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 6 is a process chart (No. 3) sequentially showing the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 7 is a process chart (No. 4) sequentially showing the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 8 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light-shielding film, and the like are formed in a liquid crystal device which is a second embodiment of the electro-optical device.

9 is a cross-sectional view taken along the line B-B ′ of FIG.

FIG. 10 is a cross-sectional view of a liquid crystal device that is a third embodiment of the electro-optical device.

FIG. 11 is a cross-sectional view of a liquid crystal device that is a fourth embodiment of the electro-optical device.

FIG. 12 is a cross-sectional view of a liquid crystal device that is a fifth embodiment of the electro-optical device.

FIG. 13 is a plan view of the TFT array substrate in the liquid crystal device according to each embodiment as viewed from the counter substrate side together with the constituent elements formed thereon.

14 is a cross-sectional view taken along the line H-H ′ of FIG.

FIG. 15 is a block diagram showing a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 16 is a cross-sectional view showing a projector as an example of an electronic device.

FIG. 17 is a front view showing a personal computer as another example of the electronic apparatus.

[Explanation of symbols]

1a ... semiconductor layer 1a '... Channel region 1b ... Low concentration source region 1c ... low concentration drain region 1d ... High-concentration source region 1e ... high-concentration drain region 1f ... First storage capacitor electrode 2 ... Insulating thin film (first dielectric film) 3a ... scanning line 3b ... Capacity line 4 ... Second interlayer insulating film 5 ... Contact hole 6a ... Data line 7 ... Third interlayer insulating film 8a ... first contact hole 8b ... second contact hole 9a ... Pixel electrode 10 ... TFT array substrate 11a, 11b ... First light-shielding film 12 ... Base insulating film 15 ... Contact hole 16 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 23 ... Second light-shielding film 30 ... TFT 50 ... Liquid crystal layer 52 ... Sealing material 53 ... Third light-shielding film 70 ... Storage capacity 70a ... first storage capacity 70b ... Second storage capacity 80 ... Barrier layer 81 ... First interlayer insulating film (second dielectric film) 101 ... Data line drive circuit 104 ... Scan line drive circuit

Continued front page    F term (reference) 2H092 HA04 JA25 JA46 JB54 JB57                       JB63 JB65 KA04 KA17 KB22                       KB24 KB25 MA05 MA08 MA13                       NA25 PA01 RA05                 5C094 AA02 AA05 AA07 AA45 BA03                       BA43 CA19 DA13 DB04 EA04                       EA10 ED15 FA02 FB02 FB14                       FB15 FB16 HA02 HA06 HA07                       HA08 HA10 JA08                 5F110 AA30 BB02 CC02 DD02 DD03                       DD12 DD13 DD14 EE09 EE28                       EE45 FF02 FF03 FF09 FF23                       GG02 GG13 GG25 GG47 HJ01                       HJ04 HJ13 HL02 HL03 HL04                       HL08 HL11 HL23 HM03 HM15                       NN03 NN22 NN23 NN24 NN25                       NN26 NN34 NN35 NN42 NN44                       NN46 NN54 NN72 NN73 PP02                       PP03 PP10 PP33 QQ05 QQ11

Claims (3)

[Claims] 1. An electro-optical device having a pixel electrode provided corresponding to a thin film transistor, and a storage capacitor connected to the pixel electrode, the electro-optical device being formed on a drain region side of a semiconductor layer of the thin film transistor. A first storage capacitor electrode, a second storage capacitor electrode formed in the same layer as the gate electrode of the thin film transistor and facing the first storage capacitor electrode, and an insulating layer above the second storage capacitor electrode A conductive film formed via a film and electrically connected to the drain region of the semiconductor layer, and formed via an insulating film above the conductive film,
An electro-optical device having a pixel electrode electrically connected to the conductive film, wherein the insulating film under the pixel electrode is a flattening film. 2. The electro-optical device according to claim 1, wherein the conductive film is a third storage capacitor electrode formed so as to face the second storage capacitor electrode. 3. An electronic apparatus comprising the electro-optical device according to claim 1. Description: