JP2003023104A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having the constitution of high insulating withstand pressure for preventing a gate insulating film from being made into silicide when a gate electrode is made into silicide in terms of self-matching and having a TAT DRAM cell, and to provide the manufacturing method. SOLUTION: The transistor part 40 of the semiconductor device has constitution similar to conventional one except for a gate electrode. The SiN sidewall 42 having a film thickness of 20 nm is arranged on the gate insulating film 16 along both groove walls of a groove 14. The gate electrode 44 is constituted of a multilayer film having a phosphorus doped polysilicon gate electrode main body 44a buried from the lower ends of both SiN sidewalls to a groove base, a phosphorus doped polysilicon layer 44b formed between the SiN sidewalls on the gate electrode main body and silicide 44c obtained by making the polysilicon layer into silicide in terms of self-matching. Since the polysilicon layer between the SiN sidewalls is made into silicide, the gate insulating film is prevented from being damaged and the insulating withstand pressure defect of the gate electrode is prevented like a conventional case when the electrode is made into silicide.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a TAT / DRAM.
More specifically, the present invention relates to a semiconductor device having a structure in which a gate electrode of a TAT / DRAM cell has a good withstand voltage, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a semiconductor device for processing a large amount of information at high speed, a large capacity DRAM and an Emb (Embeded) DRAM in which a high speed logic integrated circuit is embedded in one chip have been put into practical use. However, in response to the ever-increasing demand for miniaturization of semiconductor devices, various problems as described below have become apparent in EmbDRAMs.

(1) In order to maintain the high performance of the transistor against the reduction of the size of the DRAM memory cell, the substrate concentration of the semiconductor substrate forming the semiconductor device is becoming higher and higher. The concentration change in the area is also becoming sharp. For this reason, the electric field applied to the junction becomes stronger and stronger, and it is difficult to suppress the leakage of the junction to the ppm order in the megabit class DRAM. As a result, the data retention characteristics of DRAMs (generally Ta
It is difficult to maintain the il characteristic) as in the past. Then, as it is, there is no effective measure other than increasing the capacitance of each generation.

(2) As the size of the DRAM cell is reduced, the contact area between the extraction contact (extraction electrode) of the diffusion layer and the diffusion layer is narrowed, and the contact resistance is increasing about twice with each generation. . In the generations after 0.1 μm, the contact resistance is expected to reach several kilohms, which is expected to reach a resistance value comparable to the on resistance of the memory cell transistor. When the contact resistance becomes large, the variation of the contact resistance greatly affects not only the memory cell / transistor but also the operation of the DRAM, especially the high-speed operation. Therefore, in the manufacturing process of the DRAM, higher positioning accuracy of the contact and the diffusion layer is required. Required.
In particular, in DRAMs that require high-speed operation, improving the positioning accuracy is a problem in ensuring the performance.

(3) Also, with the reduction in size of DRAM cells, the interlayer insulation distance between the word line and the diffusion layer extraction contact formed beside the word line is decreasing year by year.
For example, in order to secure the dielectric strength between the word line and the diffusion layer extraction contact, a megabit class DRAM is used.
Then, the interlayer insulation distance between the word line and the diffusion layer take-out contact is said to be 20 to 30 nm as a limit distance, but if the trend of the area reduction of the DRAM cell continues as it is, in the generation after 0.1 μm, the word The interlayer insulation distance between the line and the diffusion layer lead-out contact becomes equal to or less than the limit distance of 20 to 30 nm.

(4) Conventionally, the WSi / doped polysilicon polycide structure has been adopted for the word line of the DRAM to alleviate the problem of signal delay.
With the miniaturization, the aspect ratio of the word line becomes large, and it becomes difficult to make the wiring structure of the word line sufficiently low resistance in order to suppress the signal delay of the word line. In particular, in the case of an Emb / DRAM that requires high-speed operation, this word line delay is a serious problem that affects the access time of the DRAM. Therefore, in order to reduce the resistance of the gate electrode (word line), a wiring having a salicide structure has been put into practical use. However, when the salicide structure is applied to the gate electrode (word line) of the DRAM cell,
Since the offset SiO ₂ cannot be used, it becomes an obstacle to downsizing of the DRAM cell. Further, in order to maintain the data retention characteristic, there is a problem that a process for forming salicide is not required in the diffusion layer of the DRAM,
At present, it is difficult to adopt a salicide structure for the gate electrode.

(5) Further, as the DRAM size is reduced, D
When forming a storage node contact of a RAM, it is indispensable to provide an opening with no margin, and the distance between the contact opening and the word line is close to the withstand voltage limit, like the diffusion layer contact. As a result, the contact diameter becomes smaller, and thus a technique for efficiently suppressing an increase in resistance with a small contact diameter is needed.

(6) On the other hand, the transistor performance of the logic portion has been remarkably improved, and in particular, a P ⁺ gate electrode into which boron ions have been ion-implanted has come to be generally used in order to suppress the off leak of the P-channel transistor. . By the way, the P ⁺ gate electrode, P by the heat treatment ⁺
When activating the gate electrode, there is a problem of so-called “penetration” in which boron as an impurity diffuses to the substrate side. This causes serious problems such as variations in characteristics of P-channel transistors, depletion of gate electrodes, and deterioration of gate insulation. In addition, doped polysilicon, which is widely used for the diffusion layer contact of DRAM, is a material that must be activated by heat treatment.
Attention must be paid to the consistency in mixed loading.

[0009]

In the future 0.1 μm generation or later, further thinning of the gate oxide film is required, and as described above, the technology which is manageable in the current 0.18 μm generation is manageable. May not be applicable. Therefore, it is expected that the Emb / DRAM structure itself needs to be drastically improved in order to maintain the trend of improving the chip performance.

Therefore, Emb / DRA of 0.1 μm or later
As a device structure that can solve all of the above-mentioned six problems that are expected to be manifested in M and can maintain the trend of improving chip performance, the word line of the DRAM part is embedded in the "groove" formed in the substrate. Trench Access Transist
An or (TAT) DRAM cell has been proposed.

Now, with reference to FIG. 7, the structure of a semiconductor device which is an Emb / DRAM in which a DRAM memory unit and a logic unit are mounted together and in which the DRAM memory unit is composed of TAT / DRAM cells will be described. . Figure 7 shows TAT
It is a cross-sectional view showing the configuration of the transistor portion of the DRAM cell. Since the logic part of the semiconductor device has no direct relation to the present invention, the illustration and description of FIG. 7 are omitted. The transistor portion 10 of the TAT / DRAM cell is N
A channel transistor, as shown in FIG.
A gate electrode 18 embedded in a groove 14 formed in the i-substrate 12 via a gate insulating film 16, a diffusion layer 20 formed on a substrate upper side of the groove 14, and a diffusion layer connected to the diffusion layer 20. And an electrode 22.

Further, referring to FIG. 7, TAT / DRAM
The structure of the transistor portion 10 of the cell will be described. As shown in FIG. 7, the element isolation region 24 is formed in the Si substrate 12 by, for example, the STI (Shallow Trench Isolation) technique to a depth of, for example, about 0.1 μm to 0.2 μm. In the Si substrate 12 and the element isolation region 24,
The groove 14 is formed with a depth of, for example, about 50 nm to 100 nm, and a word line (gate electrode) 18 is formed in the groove 14 via a gate insulating film 16.

A P well 26 is provided in a region between the two element isolation regions 24, that is, a transistor forming region, and a region of the Si substrate 12 between the P well 26 and the trench 14 has a high concentration. For example, 1.0 × 10 ¹⁸ / cm ^{3 to} 1.0
A channel diffusion layer 28 of × 10 ¹⁹ / cm ³ is formed. On the other hand, the semiconductor substrate regions on both sides and above the groove 14 are
Most of the substrate concentration is extremely low, for example 1.0.
× 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁸ / cm ³ . A silicon oxide film formed by thermal oxidation of silicon can be applied to the gate insulating film 16, and a silicon oxide film having a thickness of, for example, about 2 nm to 4 nm is formed as the gate insulating film 16.

The word line (gate electrode) 18 is formed such that the upper surface thereof is located at a position below the surface of the Si substrate 12 by a distance of at least 30 nm to 50 nm, preferably 40 nm to 50 nm. As a result, a breakdown voltage with respect to the diffusion layer extraction electrode 20 described later is secured. In order to suppress the signal delay, the word line (gate electrode) 18 has a heat-resistant salicide gate structure made of cobalt silicide / polysilicon instead of the conventional polycide structure made of WSi ₂ / polysilicon. Therefore, problems such as boron penetration and segregation at the tungsten silicide interface do not occur. Figure 7
Inside, 18a shows cobalt silicide / polysilicon.

Further, in the upper substrate portion on the side of the groove 14, 1
A source / drain diffusion layer 20 having a concentration of about × 10 ¹⁸ cm ^{-3 to} 3 × 10 ¹⁸ cm ^-3 is formed. Si substrate 12
Since it is desirable to relax the electric field strength of the semiconductor layer and the diffusion layer 20, the semiconductor substrate region at the junction with the diffusion layer 20 is set to a low concentration to form a low electric field strength junction.

Since the Si substrate 12 under the diffusion layer 20 is a region where almost no ions are implanted, it is 1 × 10 ¹⁶ cm ^{−3 to} 5 ×.
It has a very thin concentration of about 10 ¹⁷ cm ^-3 . As a result, the NP junction of this example is a super graded junction.
ction. This super-graded junction relaxes the electric field at the time of reverse bias, and as a result, megabit-class DRAM
It is possible to suppress a junction leak that occurs in a defective bit of only ppm order and is worse by two digits than usual. The data retention characteristic of this defective bit is DRA
It controls the chip performance of M and is an important technology for maintaining the data retention characteristics in future DRAMs. If the substrate concentration is about 5 × 10 ¹⁶ cm ³ , 500 msec at 85 ° C
The above data retention characteristics can be expected. This is 4
The ~ 5th generation has performance comparable to the data retention characteristics of the previous DRAM.

As described above, the gate electrode 18 is embedded in the Si substrate 12 via the gate insulating film 16, and the diffusion layer 2 is formed.
Since 0 is formed in the upper layer of the Si substrate 12,
The channel is formed so as to surround the substrate region on the bottom side of the groove 14 in which the gate electrode 18 is formed. As a result, in the transistor portion of the DRAM, a channel can be formed by rounding the groove 14 to secure a long effective channel length. It is also possible to stabilize the transistor characteristics of the cell.

On the Si substrate 12 including the diffusion layer 20, except for the inside of the groove 14, a C film having a film thickness of 20 nm to 40 nm is formed.
A VD / SiO ₂ film 30 is formed. The SiO ₂ film 30 (1) plays a role of a buffer film when performing ion implantation for forming the P well, and (2) D performed later.
At the time of ion implantation for adjusting the substrate concentration of the transistor of the RAM cell, it works as a stopper for the ion implantation,
A low substrate concentration in the junction portion of the DRAM is realized, and when the salicide is formed on the surface of the word line buried in the groove 14 in the step (3), salicide is formed in the diffusion layer of the DRAM portion. It plays a role to prevent being abused.

A SiN cap layer 32 having a thickness of 10 nm is provided on the gate electrode 18, along the gate insulating film 16 on the groove wall of the groove 14, and on the SiO ₂ film 30. The first interlayer insulating film 3 is formed on the SiN cap layer 32.
4 is deposited and the surface is flattened. First interlayer insulating film 34, SiN cap layer 32, and CVD / SiO
_{2 A} diffusion layer lead-out electrode 22 which penetrates the film 30 and reaches the diffusion layer 20 is formed of phosphorus-doped polysilicon in a plug shape. The lead-out electrode 22 contacts the entire surface of the diffusion layer 20 and has a plug diameter as large as possible so that the contact resistance is reduced. The extraction electrodes 22 are connected to a capacitor and a bit line (not shown) depending on the design.

By the way, in manufacturing the above-mentioned TAT / DRAM cell, when siliciding the gate electrode surface of the DRAM in a self-aligning manner, that is, when forming salicide, the silicidation reaction proceeds too much, and cobalt is generated. There is a problem that it also reacts with the gate insulating film, damages the gate insulating film, and causes a breakdown voltage failure.

Therefore, an object of the present invention is to prevent the silicidation of the gate insulating film when siliciding the gate electrode in a self-aligned manner, and to provide a TAT having a high withstand voltage.
-To provide a semiconductor device having a DRAM cell and a manufacturing method thereof.

[0022]

In order to achieve the above object, a semiconductor device according to the present invention is buried in a groove formed in a semiconductor substrate via a gate insulating film, and is silicided in a self-aligned manner. In a semiconductor device having a TAT / DRAM cell provided with a gate electrode having an upper layer, an insulating film sidewall is provided on the gate insulating film along both opposing groove walls at the upper part of the groove, and the gate electrode is provided on both sides. A multilayer film having a gate electrode body made of silicon provided in the lower part of the groove from the lower end of the insulating film sidewall to the groove bottom, and a silicide formed in a self-aligned manner between the insulating film sidewalls on the gate electrode body. It is characterized by being configured.

The semiconductor device according to the present invention is a semiconductor device that has an Emb (Embe
ded) Not limited to DRAM, it is applicable as long as it is a semiconductor device having a TAT / DRAM cell.
3.) It does not have to be DRAM. Preferably, a silicon layer is provided between the gate electrode body and the silicide, and the silicon layer is silicidized, whereby the silicidation can be more easily performed in a self-aligned manner. Also, preferably,
The insulating film sidewall is formed so that its film thickness is thicker than that of the gate insulating film. As a result, the withstand voltage of the gate electrode can be improved.

A method of manufacturing a semiconductor device according to the present invention is
A method of manufacturing a semiconductor device having an AT / DRAM cell, wherein a gate electrode body made of silicon is formed below a groove when a gate electrode is buried in a groove formed in a semiconductor substrate via a gate insulating film. And a step of providing an insulating film sidewall on the gate insulating film along both opposing groove walls on the gate electrode body in the groove, a silicon layer is provided between the insulating film sidewalls, and then the silicon layer upper part is self-assembled. And a step of forming a silicide in a consistent manner. Preferably, an insulating film sidewall whose thickness is larger than that of the gate insulating film is formed.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, examples of embodiments will be given and attached.
Embodiments of the present invention will be described in detail with reference to the drawings.
Explained. In addition, the film forming method shown in the following embodiment example
The composition and thickness of the edge layer, conductive layer, etc., process conditions, etc.
One example for facilitating the understanding of the invention,
The invention is not limited to this example. Example of embodiment of semiconductor device The example of the present embodiment is an embodiment of the semiconductor device according to the present invention.
FIG. 1 shows an example of the TA of the semiconductor device of this embodiment.
FIG. 2 is a cross-sectional view of the structure of the T / DRAM cell part, and FIG.
FIG. T of the semiconductor device of the present embodiment example
The transistor portion 40 of the AT / DRAM cell is shown in FIG.
As described above, except that the structure of the gate electrode is different.
Transistor of TAT / DRAM cell shown in FIG.
It has the same configuration as the unit 10.

In the present embodiment, as shown in FIG. 2, SiN sidewalls 42 having a film thickness of 20 nm are provided on the gate insulating film 16 having a film thickness of 4 nm along both opposing groove walls above the groove 14. Has been. Then, the gate electrode 44 is
A gate electrode body 44a made of phosphorus-doped polysilicon provided under the groove from the lower ends of both SiN sidewalls 42 to the groove bottom, and SiN on the gate electrode body 44a.
The multilayer film includes a phosphorus-doped polysilicon layer 44b formed between the sidewalls 42 and a silicide 44c formed by siliciding the polysilicon layer 44b in a self-aligned manner.

In this embodiment, the polysilicon layer 44b between the SiN sidewalls 42 is silicidized,
Since the silicide 44c is provided, the gate insulating film 16 is damaged during silicidation as in the conventional case.
The dielectric strength failure of the gate electrode 44 does not occur. Further, by providing the SiN sidewall 42, the dielectric strength of the gate electrode 44 is improved.

Example of Embodiment of Method for Manufacturing Semiconductor Device This example of the embodiment is an example of an embodiment in which the method for manufacturing a semiconductor device according to the present invention is applied to manufacture of the transistor portion 40 of the TAT / DRAM cell of the semiconductor device. Is. Figure 3
6 to FIG. 6 respectively show TA by the method of this embodiment.
FIG. 6 is a cross-sectional view of each step when manufacturing the transistor portion 40 of the T.DRAM cell. In the method of this embodiment, first, as shown in FIG. 3A, the element isolation region 24 is formed on the Si substrate 12 by shallow trench isolation (STI), and the CVD / SiO ₂ film 30 is deposited on the substrate surface. To do. Then, ions are implanted into the DRAM formation region to form Si.
A P well 26 is formed in the lower layer of the substrate 12. If necessary, punch through stop ion implantation is performed. At this stage, ion implantation for adjusting the substrate concentration of the RAM cell, that is, channel doping is not performed yet.

Next, a photoresist film is formed on the CVD / SiO ₂ film 30, and subsequently, as shown in FIG. 3B, a resist mask 45 having a pattern covering a region other than the word lines is formed. To do. Next, as shown in FIG. 3C, the SiO ₂ film 30 is etched using the resist mask 45, and then the Si substrate 12 is continuously etched to form a groove depth in the Si substrate 12 in the field region. Saga 10
The groove 14 having a size of 0 to 150 nm is formed. Incidentally, the groove 14
Is shown in FIG. 3 (c) in order to prevent the electric field concentration of the transistor.
It is desirable to make the bottom rounded, as shown in. Since the width of the groove 14 becomes the channel length of the transistor, it is desirable to process the groove 14 as vertically as possible.

The resist mask 45 is removed, and FIG.
, The sacrificial oxide film 4 having a film thickness of 10 nm to 20 nm is formed.
6 is deposited. Then, ion implantation is performed to
As shown in (d), the transistor portion 40 is formed under the groove 14.
The channel diffusion layer 28 of is formed. Transistor part 40
The region of high concentration as the channel diffusion layer 28 of
It is almost unnecessary to perform ion implantation for adjusting the substrate concentration in the Si substrate 12 on the side of the groove 14 and in the upper layer portion of the Si substrate 12 in the substrate region below 4. CVD
Since the SiO ₂ film 30 plays the role of a stopper for ion implantation, effective ion implantation can be performed only in the substrate region below the groove 14 without a mask. In addition, since ion implantation is not performed in the upper layer portion of the substrate, it is possible to form an extremely low concentration region.

Then, as shown in FIG. 4E, the sacrificial oxide film 46 is removed, and SiO ₂ or SiON having a film thickness of 4 nm is formed.
A gate oxide film 16 made of is formed, and a phosphorus-doped polysilicon layer 48 is deposited on the entire surface of the gate oxide film 16.
Next, the phosphorus-doped polysilicon layer 48 is etched back to form a gate electrode body 44a made of the phosphorus-doped polysilicon layer in the trench 14 as shown in FIG. 4 (f). At this time, the upper surface of the polysilicon layer 48 is the Si substrate 1
The gate electrode body 44a is formed so as to come to a position lower than the surface of No. 2 by about 100 to 150 nm. In the fabrication of the transistor portion 10 of the TAT / DRAM cell shown in FIG. 7, the upper surface of the polysilicon layer 48 is located at a position lower than the surface of the Si substrate 12 by about 50 to 100 nm. Then, as will be described later, since the polysilicon layer is stacked on the gate electrode body 44a, the polysilicon layer 48 is etched back deeper by that amount.

Transistor part 4 of TAT / DRAM cell
Reference numeral 0 is an Nch transistor, and since the polysilicon layer is used only for the word line of the DRAM part, phosphorus-doped polysilicon which is an N ⁺ gate material can be applied. The thickness of the gate electrode body 44a is 50
It is about 150 nm, and the film thickness optimized only for forming the "groove" word line can be set.

Next, as shown in FIG. 5G, phosphorus ions are ion-implanted to form the diffusion layer 20 in the source / drain regions. The ion implantation is performed only on the upper portion of the diffusion layer 20 with a profile as sharp as possible. Since it suffices to penetrate the CVD / SiO ₂ film 30 provided in advance, the implantation energy is set to 20 to 50 KeV.
The concentration is set to about x10 ^{18 to} 3x10 ¹⁸ cm ^-3 . Since the Si substrate region under the diffusion layer 20 is a region in which almost no ion implantation is performed, and the concentration can be made extremely low at about 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ , this NP junction is super-graded. Become a junction.

Subsequently, as shown in FIGS. 5 (h) and 5 (i), the SiN sidewalls 42 made of a SiN film having a film thickness of 20 nm are formed on the gate walls of the groove 14 above the gate electrode body 44a. It is formed along the insulating film 16. Figure 5
(I) is an enlarged view of the gate electrode portion of FIG. Although not shown when forming the SiN sidewall 42, first, for example, DCS (dichlorosilane) and N are used.
Hot wall type LP-C using H ₃ gas as raw material gas
Using a VD device, the film thickness is 1
A 0 nm SiN film is formed. Then, using, for example, a parallel plate type RIE device, CHF ₃ , C as an etching gas under the conditions of the upper electrode 1000 W and the lower electrode 500 W.
The SiN film 42 is etched back by using a mixed gas of O and CO ₂ to form the SiN sidewall 42.

Next, as shown in FIG. 6L, a phosphorus-doped polysilicon layer 50 is formed on the entire surface of the substrate to form the groove 14
6M, followed by etching back to form a polysilicon layer 44b forming a part of the gate electrode 44 on the gate electrode body 44a in the groove 14 as shown in FIG. 6 (m). Next, as shown in FIG. 6 (n), the upper layer portion of the polysilicon layer 44b is silicided in a self-aligned manner to form a silicide 44c.

Thereafter, as in the conventional method, as shown in FIGS. 1 and 2, the SiN cap layer 32 is further formed on the entire surface of the substrate, and then the first interlayer insulating film 34 is formed. Next, a connection hole (not shown) which penetrates the first interlayer insulating film 34, the SiN cap layer 32, and the CVD / SiO ₂ film 30 and reaches the diffusion layer 20 is provided, and the connection hole is filled with polysilicon, As shown in FIG. 1, a plug-shaped diffusion layer extraction electrode 22 is formed.

As a result, as shown in FIGS. 1 and 2,
The transistor portion 40 of the TAT / DRAM cell in which the silicide 44c and the Si substrate 12 are insulated by the thick SiN sidewall 42 can be manufactured.

[0038]

According to the present invention, since the silicon layer between the insulating film sidewalls is silicidized and the silicide is provided, the silicidation is performed as in the conventional case.
The gate insulating film will not be damaged and the dielectric strength of the gate electrode will not be defective. Further, by providing the insulating film sidewall, the withstand voltage of the gate electrode is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of the configuration of a TAT / DRAM cell portion of a semiconductor device according to an exemplary embodiment.

FIG. 2 is an enlarged cross-sectional view of a gate electrode portion of a TAT / DRAM cell portion of a semiconductor device according to an exemplary embodiment.

FIG. 3A to FIG. 3C are cross-sectional views of respective steps when a TAT / DRAM cell portion is manufactured by the method of the embodiment.

4 (d) to (f) are respectively FIG.
Following (c), TAT / DR is performed by the method of the embodiment.
It is sectional drawing for every process at the time of producing an AM cell part.

5 (g) to (i) are respectively FIG.
Following (f), TAT / DR is performed by the method of the embodiment.
It is sectional drawing for every process at the time of producing an AM cell part.

6 (l) to 6 (n) are respectively shown in FIG.
Following (i), the TAT DR
It is sectional drawing for every process at the time of producing an AM cell part.

FIG. 7 is a cross-sectional view showing a configuration of a TAT / DRAM cell portion of a conventional semiconductor device.

[Explanation of symbols]

10 ... Transistor part of TAT / DRAM cell, 12
...... Si substrate, 14 ...... groove, 16 ...... gate insulating film, 1
8 ... Gate electrode, 18a ... Silicide, 20 ... Diffusion layer, 22 ... Diffusion layer extraction electrode, 24 ... Element isolation region, 26 ... P well, 28 ... Channel diffusion layer, 3
0 ... CVD / SiO ₂ film, 32 ... SiN cap layer, 34 ... First interlayer insulating film, 40 ... Transistor portion of TAT / DRAM cell of semiconductor device of embodiment example,
42 ... SiN sidewall, 44 ... Gate electrode,
44a ... gate electrode body, 44b ... polysilicon layer, 44c ... silicide, 45 ... resist mask,
46 ... Sacrificial oxide film, 48 ... Polysilicon film, 50 ...
... polysilicon film.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 H01L 21/265 HRF term (reference) 4M104 BB01 BB40 CC05 DD02 DD04 DD08 DD15 DD16 DD63 DD65 DD91 EE03 EE09 EE14 EE16 EE17 FF06 FF14 FF27 GG09 GG16 HH00 5F083 AD04 GA30 JA02 JA05 JA32 JA35 JA53 MA03 MA06 MA16 MA17 MA20 NA01 NA08 PR21 PR33 PR36 PR39 5F140 AA19 AC32. BG26 BG27 BG34 BG36 BG52 BG53 BH49 BJ01 BJ04 BJ23 BJ27 BJ29 BK13 BK25 CA04 CB04 CB08 CC01

Claims (5)

[Claims] 1. A TAT / DR provided with a gate electrode having an upper layer which is buried in a groove formed in a semiconductor substrate via a gate insulating film and is silicided in a self-aligned manner.
In a semiconductor device having an AM cell, insulating film sidewalls are provided on a gate insulating film along both groove walls facing each other at an upper part of the groove, and the gate electrode is provided from a lower end of both insulating film sidewalls to a groove bottom. A multi-layer film having a gate electrode body made of silicon provided in the lower part of the groove and a silicide formed in a self-aligned manner between the insulating film sidewalls on the gate electrode body. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a silicon layer is provided between the gate electrode body and the silicide. 3. The semiconductor device according to claim 1, wherein the insulating film sidewall is thicker than the gate insulating film. 4. A method of manufacturing a semiconductor device having a TAT / DRAM cell, wherein a gate electrode made of silicon is formed below a groove when a gate electrode is buried in the groove formed in a semiconductor substrate via a gate insulating film. Forming a body, providing an insulating film sidewall on the gate insulating film along both opposing groove walls on the gate electrode body in the groove, and providing a silicon layer between the insulating film sidewalls And a step of subsequently silicidizing the upper portion of the silicon layer in a self-aligned manner. 5. The semiconductor device according to claim 4, wherein an insulating film sidewall having a film thickness larger than that of the gate insulating film is formed.