JP2003152086A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an element structure which can secure necessary capacitance without lowering an aperture rate. SOLUTION: A substrate is provided with a groove or trench recessed part, and a capacitor element is manufacture in the groove. As the substrate is provided with more and more grooves, the capacitance is larger and larger. The capacitance increases with the depth of the grooves. Namely, the capacitance can be adjusted by adjusting the number of the grooves and further adjusted by adjusting the depth of the grooves. This capacitor element is provided below a semiconductor film, so it serves as a shading film which prevents light from being incident on the semiconductor film from below.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device represented by a liquid crystal display panel and an electronic device in which the electro-optical device is mounted as a component.

[0002] In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. The present invention relates to a semiconductor device having a thin film transistor (hereinafter referred to as TFT), and more particularly to the structure of a storage capacitor element in the semiconductor device.

[0003]

2. Description of the Related Art A TFT drive type liquid crystal display device is known as one of semiconductor devices. This TFT drive type liquid crystal display device has a clear image because it controls the voltage applied to the liquid crystal for each pixel by a TFT formed on a transparent substrate such as glass, and is widely used in OA devices, TVs and the like. Has been. Further, in order to display characters and graphics more clearly, it is required to reduce the size of one pixel to increase the number of pixels per unit area, that is, to increase the so-called definition.

FIG. 17 shows an equivalent circuit diagram of one pixel in a TFT drive type liquid crystal display device. A TFT 1002 is arranged at the intersection of the gate signal line 1000 and the source signal line 1001, and the liquid crystal capacitor 10 serves as a load of the TFT 1002.
A storage capacitor 1004 is connected in parallel with 03. Therefore, according to the signal of the gate signal line 1000, the TFT 10
When 02 is turned on, the potential of the source signal line 1001 is written in the pixel electrode portion 1005, and the liquid crystal capacitor 1003
Electric charges are accumulated in the storage capacitor 1004 and the storage capacitor 1004. Also, TF
When T1002 is in the OFF state, the electric charge accumulated in the liquid crystal capacitor 1003 is retained, but the retention characteristic can be improved by arranging the retention capacitors 1004 in parallel.

The storage capacitor 1004 is a TFT 100.
2 has the effect of suppressing the shift of the display electrode voltage that occurs during operation. That is, in the overlapping portion of the gate signal line 1000 and the source signal line 1001, the TFT 1002
The parasitic capacitance 1007 changes according to the ON / OFF state of. Also, while the TFT 1002 is OFF, the TFT 10
Due to the leak current of 02, the charge stored in the liquid crystal capacitor 1003 is lost. Therefore, by arranging the storage capacitors 1004 in parallel and increasing the total capacitance, the influence of the DC component due to the parasitic capacitance 1007 on the potential of the pixel electrode portion 1005 is mitigated.

Due to these advantages, the storage capacitor 1004 is an indispensable circuit element for a pixel of a TFT drive type liquid crystal display device.

However, the storage capacitor has a required value per pixel determined by the ratio of the channel width and the channel length of the TFT serving as a switching element, the parasitic capacitance and the OFF leakage current, and the capacitance value per unit area of the dielectric material. From this, the area of the capacitive element is determined. Therefore, the required capacitance value is substantially satisfied by controlling the area of the dielectric according to the required capacitance value.

In the prior art, the storage capacitor is usually a pixel TFT.
It was formed outside the area, that is, in the display area. Therefore, the area occupied by the capacitive element is increased in the pixel portion in order to secure a sufficient capacitance value, which causes a reduction in the aperture ratio of the pixel, a reduction in the light transmittance and a reduction in the contrast, making it impossible to display a clear screen. There was a problem. In particular, this drawback becomes remarkable when an attempt is made to realize a high-definition display device.

In addition, the channel formation region of the TFT element and the LD
When light enters the D region, a current due to photoexcitation flows. Since such a current causes an increase in off-leakage current, the incidence of light on the TFT element deteriorates the retention characteristic of the TFT element. In recent years, especially in the case of a transmissive liquid crystal element structure used for a projector, it has become essential to provide light shielding films above and below the TFT element. This is because the brightness of the lamp is remarkably improved, and not only the light directly entering the TFT element from the lamp, but also the light reflected and returned after passing through the liquid crystal element structure has a non-negligible intensity. For the above reasons, measures to shield the incident light from the upper and lower parts of the TFT element are as important as securing a sufficient storage capacitor.

In order to overcome these problems, the present inventor has invented that a capacitor element is formed below a TFT element in Japanese Patent Laid-Open No. 2001-249362. Further, this capacitive element has a feature that deterioration of the retention characteristics due to the incidence of light on the active layer (semiconductor film) can be reduced by using a material having a light shielding property.

[0011]

However, Japanese Patent Laid-Open No. 2001-2001
In the structure of Japanese Patent No. 249362, the electrodes of the capacitance element are parallel plate type, and the electrode surface is parallel to the semiconductor film above the capacitance element. Therefore, when the electrode area is increased, the aperture ratio is reduced. Therefore, there was a limit in securing the necessary capacitance value without lowering the aperture ratio.

[0012]

In order to solve the above-mentioned problems, it is important to make at least a part of the electrode surface of the capacitor element have a vertical structure with the semiconductor film formed on the capacitor element. Further, since this capacitive element is provided below the semiconductor film, it also serves as a light-shielding film that prevents light from entering the semiconductor film from below.

Specifically, a groove or a trench recess is provided in the substrate, and a capacitive element is manufactured in the groove. The more grooves provided on the substrate, the larger the capacitance value. The capacitance value also increases depending on the depth of the groove. That is, the capacitance value can be adjusted by adjusting the number of grooves, and the capacitance value can also be adjusted by adjusting the depth of the groove.

By providing a groove or trench recess in the substrate and forming a capacitor element in the groove or trench recess, the required capacitance can be secured without increasing the aperture ratio. Further, as described above, the capacitive element of the present invention also plays the role of the light shielding film. Therefore, with the minimum area required for shading,
It has a great effect that a sufficient capacity can be secured and the aperture ratio does not decrease.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION 1. Configuration of Semiconductor Device FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of the present invention. In FIG. 1, 101 is a substrate, 102 is a groove or trench recess, 103 is a first conductive film, and 104 is a first conductive film.
Insulating film, 105 is a second conductive film, 106 is a third conductive film, 107 is a second insulating film, 108 is a semiconductor film, and 108 is a semiconductor film.
a is a channel formation region, 108b is a source region or a drain region, 108c is an LDD region, 109 is a gate insulating film, 110 is a gate electrode, 111 and 112 are source electrodes and drain electrodes, and 113 is a third insulating film. Third
The conductive film 106 and the LDD region 108c are not essential constituent elements but can be provided as needed.

The first conductive film 103 and the first insulating film 10 are formed in the groove or trench recess 102 formed in the substrate 101.
4, a capacitive element formed by the second conductive film 105 and the third conductive film 106 is provided. With this structure, the capacity can be increased without lowering the aperture ratio. In addition, the first conductive film 103 and the second conductive film 10
By forming any one of 5 and the third conductive film 106 with a material having a light shielding property, the capacitor element also serves as a light shielding film.

Although two grooves or trench recesses are provided in FIG. 1, the number is not limited to two. 1 depending on the ratio between the channel width and the channel length of the TFT that serves as a switching element, the parasitic capacitance, the OFF leakage current, etc.
The value of the storage capacitor required for each pixel is determined, and the required number is determined accordingly.

Further, as shown in FIGS. 11A to 11C, the groove or trench recesses 1101, 1103, 1105 are
It may be formed in a single row type, a grid shape, a well shape or a cross shape. In addition, the semiconductor film 11 provided over the capacitor element
02, 1104 can be provided in the parallel direction (FIG. 11A) or the vertical direction (FIG. 11B) with respect to the channel length directions 1107, 1108. Further, they may be provided in a direction parallel to and a direction perpendicular to the channel length direction 1109 (FIG. 11C). By doing so, increasing the capacitance value of the capacitor without reducing the aperture ratio can improve the light blocking effect on the semiconductor films 1102, 1104, 1106.

FIG. 12 is a top view showing an example of the embodiment of the present invention. In FIG. 12, some of the electrode lines and the light-shielding film provided on the semiconductor film are omitted for ease of explanation. The capacitor 1201 is provided in a direction 1208 parallel to the channel length direction of the semiconductor film 1203. By providing the capacitor element 1201 below the TFT in the pixel portion in this manner, it is possible to obtain a necessary storage capacitor and a light blocking effect for incident light from the lower portion without lowering the aperture ratio. However, in this form, the shielding of the incident light 1204 from below onto the semiconductor film is insufficient. The incident light 1204 from the lower portion is the light reflected by the projection lens or the like and returned, and is not necessarily parallel to the normal direction of the substrate. With the recent improvement in the brightness of lamps, it is necessary to consider blocking light that is incident from below at a shallow angle such that the incident path extends over several pixels.

FIG. 13 is a top view showing an example of the embodiment of the present invention. In FIG. 13, some of the electrode lines and the light-shielding film provided on the semiconductor film are omitted for ease of explanation. In order to solve the above problem, the capacitor 1301
Is a direction parallel to the channel length direction of the semiconductor film 1303.
08 and 1309 in the vertical direction. That is, as shown in FIG. 13, the capacitive element 1301 has an independent L
It may be formed in a letter pattern. Further, it may be formed in a shape divided at the corners of the L-shape. Further, in FIG. 13, the dotted line ○
The portion indicated by the mark, that is, the L-shaped corner portion 1310 does not form a groove, and the first conductive film, the first insulating film, the second conductive film, and the third conductive film are formed in parallel with the semiconductor film. A parallel plate type capacitive element may be formed by forming a film. By forming the capacitive element in this way, it is possible to obtain a sufficient capacitance value without lowering the aperture ratio. Further, it becomes possible to block incident light from various angles to the lower portion of the semiconductor film. That is, the incident light 1 from the bottom to the semiconductor film shown in FIG.
304 is shielded from light by the capacitive element 1301. By providing the storage capacitor element in an L shape and appropriately setting the depth of the groove or the trench recess, the incident path of the incident light from the lower part can be limited, and the light shielding effect can be improved.

2. Components of Semiconductor Device (1) Substrate In the present invention, a semiconductor substrate such as a silicon wafer, a glass substrate, a quartz substrate, a metal substrate, a stainless substrate or a flexible substrate such as a film substrate can be used. Film substrate is PET (polyethylene terephthalate), PC (polycarbonate), PES (polyether sulfone), PAR (polyarylate), PEC
A film of N (polyether nitrile), stainless steel or the like can be used. In the case of a film substrate, an inorganic layer or an organic layer is provided on the surface as a gas barrier layer. In addition, when a projection is generated on the film substrate due to dust or the like when the film substrate is manufactured, the film substrate may be polished by CMP or the like and planarized before use.

(2) Groove, Trench Recess When a glass substrate or quartz substrate is used, the groove may be provided directly. Alternatively, an insulating film may be formed and a groove may be provided in the insulating film. As a manufacturing method, a mask can be formed with a photoresist and anisotropic etching can be performed. Of course, an isotropic etching process may be used depending on the design dimensions of the groove. The anisotropic etching process is typically RIE,
It can be performed by a method such as ICP. The value of the storage capacitance required for each pixel is determined by the ratio of the channel width and the channel length of the TFT serving as a switching element, the parasitic capacitance, the OFF leakage current, and the like. The number of grooves and the depth of the groove can be determined.

It is preferable that the width of the groove is designed so as to be filled by forming a conductive film and an insulating film (dielectric) forming the capacitive element in terms of flatness after filling the groove.

When a film substrate, a metal substrate or a stainless steel substrate is used, a substrate having an insulating film formed on the surface thereof is used as a substrate and a groove is formed in the insulating film.
As the insulating film, SiO ₂ film, SiN _x film, SiON film, S
An iNO film or a laminated film of these can be used.
As a film forming method, a CVD method, a sputtering method, or the like can be used. The film thickness may be about 100 nm to 2000 nm.

(3) Conductive film forming capacitive element The conductive film forming the capacitive element is made of WSi ₂ , MoSi ₂ , and T.
Silicide film such as iSi ₂ , p-type or n-type impurity-added silicon film, Al, Ta, W, Cu, Mo
Conductive materials such as and nitride films thereof, Al-Si,
An Al alloy film such as Al—Cu, a Cu alloy film such as Cu—Ag—Pd, or a laminated film thereof can be used. As a film forming method, a CVD method or a sputtering method can be used. However, the first conductive film in contact with the groove must be a film having excellent step coverage (good step coverage). Further, it is necessary to fill the groove with the second conductive film, and further, the second conductive film or the third conductive film is required to have surface flatness. Accordingly, it may be necessary to adjust film forming conditions (temperature, pressure, gas flow rate, etc.). Of course, after the second conductive film or the third conductive film is formed, the surface may be chemically and mechanically polished (typically, CMP technique) to improve the flatness. Further, the conductive film needs to be patterned by etching in order to form an independent capacitor element for each pixel.

(4) Insulating Film (Dielectric) Constituting Capacitance Element The insulating film constituting the capacitative element is a SiO ₂ film, a SiN _x film,
SiON film, SiNO film, Ta ₂ O ₅ film, BaSrTiO 3
A film or a laminated film of these can be used. As a film forming method, a CVD method, a sputtering method, or the like can be used. However, the insulating film must be a film having excellent step coverage (good step coverage) as with the conductive film. Accordingly, it may be necessary to adjust film forming conditions (temperature, pressure, gas flow rate, etc.). Further, the insulating film forming the capacitive element needs to be provided at least in the capacitive element portion.

(5) Insulating Film (Insulating Film Between Capacitance Element and TFT) The insulating film used in the present invention is a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiNO film, SiON film, etc.) or These laminated films can be used. As a film forming method, a CVD method, a sputtering method, or the like can be used.

(6) Semiconductor Film The semiconductor film used in the present invention is a single semiconductor film such as Si film and Ge film, compound semiconductor film such as GaAs film and GaN film or SiC film, SiGe film, Al _x Ga ₁ film. _-x As
A mixed crystal semiconductor film such as a film can be used. As the semiconductor film, a single crystal semiconductor film or a crystalline semiconductor film can be used. In the case of a crystalline semiconductor film, crystal growth is performed so that the carrier movement direction in the TFT channel formation region is parallel to the crystal growth direction or the crystal grain boundary occurs in parallel to the carrier movement direction in the TFT channel formation region. It is preferable. In this case, the carrier movement direction is the channel length direction (source-drain region direction).
Thus, the crystal growth direction and the channel length direction are parallel.

The single crystal semiconductor film and the crystalline semiconductor film are formed by forming an amorphous semiconductor film by a CVD method, a sputtering method or the like, and then irradiating it with laser light to crystallize it or a method of thermal crystallization. Can be considered. Alternatively, a metal element that promotes crystallization may be added to the amorphous semiconductor film, thermal crystallization may be performed, and then laser light may be irradiated to perform recrystallization.

As the laser, a continuous wave or pulsed gas laser or solid laser is used. Gas lasers include excimer lasers, Ar lasers, and Kr lasers, and solid-state lasers include YAG lasers, YVO ₄ lasers, YLF lasers, YAlO ₃ lasers, glass lasers, ruby lasers, alexandrite lasers, and Ti: sapphire lasers. Can be mentioned.

As the solid-state laser, Cr, Nd, E
A laser using crystals of YAG, YVO ₄ , YLF, YAlO ₃ or the like doped with r, Ho, Ce, Co, Ti or Tm is applied. The fundamental wave of the laser differs depending on the material to be doped, and laser light having a fundamental wave of about 1 μm can be obtained. The harmonic wave with respect to the fundamental wave can be obtained by using a non-linear optical element.

In crystallizing the amorphous semiconductor film, in the present invention, it is preferable to use a solid-state laser capable of continuous oscillation and to apply the second to fourth harmonics of the fundamental wave.
Typically, an Nd: YVO ₄ laser (fundamental wave 1064n
m) second harmonic (532 nm) or third harmonic (355
nm) is applied.

Laser light emitted from a continuous oscillation YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal and a non-linear optical element are put in a resonator to emit a higher harmonic wave. Then, it is preferably shaped into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and the object to be processed is irradiated. Energy density at this time is 0.01-100 MW
/ Cm ² (preferably 0.1 to 10 MW / cm ² ) is required. Then, the semiconductor film, that is, the substrate provided with the semiconductor film is moved and irradiated relative to the laser light at a speed of about 10 to 2000 cm / s. In addition,
The thickness of the semiconductor film may be about 30 to 300 nm.

At least a channel forming region, a source region and a drain region must be provided in the semiconductor film. An LDD region and an offset region may be provided as needed. If necessary, the LDD region and the offset region may be provided so that a part or all of the region overlaps the gate electrode with the gate insulating film interposed therebetween.

(7) Gate Insulating Film The gate insulating film used in the present invention can be a thermal oxide film of a semiconductor film, a SiO ₂ film, a SiN _x film, a SiON film, or a SiNO film. Alternatively, a laminated film of these films may be used. As a film forming method, a CVD method, a sputtering method, or the like can be used. The thickness of the gate insulating film is 30 to
It may be about 300 nm.

(8) Gate Electrode, Source Electrode, Drain Electrode The gate electrode, the source electrode, and the drain electrode used in the present invention include a silicide film such as WSi ₂ , MoSi ₂ , and TiSi ₂ , a p-type or n-type impurity. Conductive materials such as added silicon film, Al, Ta, W, Cu, Mo and their nitride films, Al such as Al-Si, Al-Cu
An alloy film, a Cu alloy film such as Cu-Ag-Pd, or a laminated film of these is used.

(9) Interlayer Insulating Film The interlayer insulating film used in the present invention is a SiO ₂ film or SiN _x film.
Film, SiON film, SiNO film, SOG (spin-on)
-Glass) film, an organic resin film such as acryl, or a laminated film thereof can be used. The film can be formed by heating after the CVD method, the sputtering method, or the spin coating method. The thickness of the second insulating layer is 300 to 3000.
It may be about nm.

[0038]

EXAMPLES The present invention will be specifically described below with reference to examples. However, the invention is not limited to only these examples.

[Embodiment 1] In the following, the steps of forming the groove or trench recess and the fabrication process of the capacitor according to this embodiment will be briefly described. In this embodiment, the number of grooves is three, but it is not limited to three.

Here, a glass substrate was used as the substrate 300. In addition to the glass substrate, a quartz substrate, a semiconductor substrate such as a silicon wafer, a metal substrate, or a stainless steel substrate having an insulating film formed on its surface can be used as the substrate. When using a glass substrate, it is 1 above the glass strain point.
You may heat-process in advance at a low temperature of 0-20 degreeC.

A photoresist film is applied to the surface of the glass substrate 300, exposed and developed to form a mask 301 made of resist, and then anisotropic etching is performed.
The groove 302 was formed (FIG. 2A). Groove 302 of course
Depending on the design size of the above, only isotropic etching may be used.
ICP (Inductively Co) is used for etching.
It is preferable to use an up plasma (inductively coupled plasma) etching method. Using ICP etching method,
Etching conditions (electric power applied to the coil type electrode,
The film could be etched into a desired shape by appropriately adjusting the amount of electric power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, and the like. It is also possible to etch in a taper shape. As the etching gas,
A chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like, or a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ or the like, and O ₂ can be appropriately added.

Further, a groove 1401 was formed as shown in FIG. Here, the manufactured capacitive element was formed to have an L-shaped pattern. 1402 is a semiconductor film formed thereafter. Here, no groove was formed in the corner 1403 of the L-shaped pattern indicated by the dotted circle mark. In FIG.
For simplification, the number and width of the grooves are emphasized in the description. Note that in reality the number of grooves is even greater and the width is smaller.

Further, here, the grooves are arranged as shown in FIG. 11 (A), but of course the invention is not limited to this,
Grooves may be arranged as shown in FIGS. 11B and 11C.

The ratio of the channel width and the channel length of the TFT serving as a switching element, the parasitic capacitance, the OFF leakage current, and the like determine the value of the storage capacitance required per pixel, and the capacitance is calculated from the capacitance value per unit area of the dielectric. The area of the device is determined. Therefore, the depth and the number of the grooves 302 may be determined so that the required capacitance value can be secured and the light shielding effect can be secured. It is desirable to narrow the partition between the grooves to the limit of fine processing. This is because the capacity can be increased. In addition, the width of the groove is determined by the first conductive film, the first insulating film, and the second conductive film which are formed later.
It is desirable for the purpose of flattening that the film is designed to be embedded by forming the conductive film. Specifically, the first
Assuming that the conductive film, the first insulating film, and the second conductive film have a conformal shape, the first conductive film (thickness is t1), the first insulating film (film) The width may be twice the total thickness (t1 + t2 + t3) of the thickness of the second conductive film (t3) and the thickness of the second conductive film (t3).

Next, the first conductive film 303 is formed. First
The conductive film 303 serves as a capacitor wiring having the same potential as the drain electrode. Here, pol with phosphorus (P) added
A y-Si film was formed to a thickness of 0.2 μm by the LPCVD method. A gas mixture of silane (SiH ₄ ) gas and phosphine (PH ₃ ) was used as a source gas, and the film forming temperature was 600 ° C. The impurity element to be added is not limited to phosphorus, but boron (B) or arsenic (As) may be used. When boron is added, diborane (B ₂ H ₆ ) is mixed with silane, and when arsenic is added, arsine (AsH ₃ ) is mixed with silane to form a raw material gas.

Here, poly-Si doped with impurities is used.
Although a membrane is used, it is not limited to this. For example, a tungsten (W) film or a TiN film may be formed by the CVD method.

As the first conductive film 303, it is necessary to form a film having excellent step coverage (step coverage) and a film having a conformal shape. here,
Since the first conductive film was formed by the LPCVD method, it was possible to easily obtain a film having excellent step coverage. The first conductive film 303 may be formed by a sputtering method or a plasma CVD method. In some cases, it may be necessary to adjust the film forming conditions (temperature, pressure, gas flow rate, etc.) in order to obtain a film having excellent step coverage.

Next, the first conductive film 303 was patterned and etched to form an independent capacitive element for each pixel. Here, the capacitive element is configured to form an L-shaped pattern.

Next, the first insulating film 304 is formed. First
The insulating film serves as a dielectric. Here, a SiO ₂ film of 0.1 μm is formed by LPCVD using tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ ) and oxygen (O ₂ ).
m was formed into a film. The film may be formed by the plasma CVD method. In this case as well, it is necessary to form a film having excellent step coverage (step coverage) and a film having a conformal shape, like the first conductive film 303. In this embodiment, the SiO ₂ film is formed, but the SiN _x film, the SiON film,
An inorganic film such as a SiNO film or a laminated film of these may be used.

A second conductive film 305 is formed. The second conductive film serves as a grounded capacitance wiring.
Here, a poly-Si film added with phosphorus (P) is used as an LP.
A film was formed by the CVD method and the groove 302 was embedded.
A gas mixture of silane (SiH ₄ ) gas and phosphine (PH ₃ ) was used as a source gas, and the film forming temperature was 600 ° C. The impurity element to be added is not limited to phosphorus, but boron (B) or arsenic (As) may be used. When boron is added, diborane (B ₂ H ₆ ) is mixed with silane, and when arsenic is added, arsine (AsH ₃ ) is mixed with silane to form a raw material gas.

Here, poly-Si doped with impurities is used.
Although a membrane is used, it is not limited to this. For example, W film,
Tungsten silicide (WSi ₂ ) film, molybdenum silicide (MoSi ₂ ) film, titanium silicide (TiS
i ₂ ) a silicide film such as a film, Al, Ta, W, Cu,
A conductive material such as Mo may be formed.

A third conductive film 3 is formed on the second conductive film 305.
As W06, a WSi ₂ film was formed by a sputtering method. Third
The conductive film 306 plays a role as a light-blocking film, but when the light-blocking conductive film (eg, W film) is formed as the first conductive film or the second conductive film 305, it is sufficient as a light-blocking film. Since it can be used, it is not necessary to form the third conductive film 306. The third conductive film 306 can be provided as needed. When the third conductive film 306 is formed,
The second conductive film 305 and the third conductive film 306 serve as a capacitor wiring. The third conductive film 306 is WSi
_In addition to the _two films, a silicide film such as MoSi ₂ or TiSi ₂ , a silicon film, a conductive material such as Al, Ta, W, Cu or Mo, or a laminated film thereof can be used.

Then, the second conductive film 305 and the third conductive film 306 are patterned and etched in order not to reduce the aperture ratio and to block the incidence of light on the TFTs formed thereafter. Part of it was removed. Since these are used as the grounded capacitance wiring 1503, they are not divided for each pixel (FIG. 15). At this time, needless to say, a region where a contact hole is formed is secured so that the first conductive film and the drain electrode can contact each other.

Then, the second insulating film 307 is formed to a film thickness of 100.
The thickness is about 1000 nm (FIG. 2B). Here C
A laminated film of a SiON film and a SiNO film was used by the VD method.

After forming the second insulating film 307,
The surface of the insulating film may be planarized by a process of chemically and mechanically polishing (typically, a CMP technique or the like). For example,
The maximum height (Rmax) of the insulating film surface is 0.5 μm or less,
It is preferably 0.3 μm or less. As a result, a structure having a capacitive element in the groove can be obtained (FIG. 2B).

[Embodiment 2] This embodiment shows an example in which the substrate 400 of Embodiment 1 is used as a film substrate.

PET commercially available as the film substrate 400
(Polyethylene terephthalate) was used. Of course P
A transparent film substrate such as ES (polyether sulfone), PC (polycarbonate), PAR (polyarylate), PECN (polyether nitrile), PI (polyimide) can also be used. Chemically and mechanically polishing the film substrate surface (typically CMP technology)
And the like). In addition, 10 on the film substrate
You may heat-process at about 0-130 degreeC. On the film substrate, a SiO ₂ film, Si
N _x film, AlO film, AlON film, AlN film, carbon film, D
An LC (diamond-like carbon) film and a laminated film of these were provided. A sputtering method was used as a film forming method. If the film forming temperature is lower than the heat resistant temperature of the substrate, plasma CVD method,
It may be formed by a normal pressure CVD method or an LPCVD method.

Next, the first insulating film 402 is formed to a film thickness of 100.
nm to 2000 nm (FIG. 3A). Here, a laminated film of a SiON film and a SiNO film was formed by using the sputtering method. If the film forming temperature is lower than the heat resistant temperature of the substrate, the plasma CVD method, the atmospheric pressure CVD method, or the LPCVD method may be used.

A photoresist film is applied to the surface of the first insulating film 402, exposed and developed to form a mask 403 made of a resist, and then anisotropically etched to form a groove 404 (see FIG. 3 (A)). ICP (Inductively Coupled) is used for etching.
Plasma: Inductively coupled plasma) etching method may be used. A film is formed into a desired shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) using the ICP etching method. It was able to be etched. It is also possible to etch in a taper shape. As the etching gas, Cl ₂ , BC is used.
A chlorine-based gas typified by l ₃ , SiCl ₄ , CCl ₄ or the like, or a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ or the like, and O ₂ can be appropriately added. Further, in this embodiment, the groove 1601 is formed as shown in FIG. FIG.
, The number and width of the grooves are emphasized for simplification. Note that in reality the number of grooves is even greater and the width is smaller.

Although the grooves are arranged as shown in FIG. 11 (B) here, of course, the invention is not limited to this, and
Grooves may be arranged as shown in FIGS. 11 (A) and 11 (C).

The ratio of the channel width and the channel length of the TFT serving as a switching element, the parasitic capacitance, the OFF leakage current, and the like determine the value of the storage capacitance required per pixel, and the capacitance value is calculated from the capacitance value per unit area of the dielectric. The area of the device is determined. Therefore, the depth and the number of the grooves 402 may be determined so that the required capacitance value can be secured and the light shielding effect can be secured. It is desirable to narrow the partition between the grooves to the limit of fine processing. This is because the capacity can be increased. The widths of the grooves are the same as those of the first conductive film, the second insulating film and the second conductive film to be formed thereafter.
It is desirable for the purpose of flattening that the film is designed to be embedded by forming the conductive film. Specifically, the first
Assuming that the conductive film, the second insulating film, and the second conductive film have a conformal shape, the first conductive film (thickness is t1), the second insulating film (film) The width may be twice the total thickness (t1 + t2 + t3) of the thickness of the second conductive film (t3) and the thickness of the second conductive film (t3).

Next, a first conductive film 405 is formed. First
The conductive film 405 plays a role of a capacitor wiring having the same potential as the drain electrode. Here, a tungsten (W) film is formed by a sputtering method. The TiN film may be formed by sputtering. If the film forming temperature is lower than the heat resistant temperature of the substrate, the plasma CVD method, the atmospheric pressure CVD method, or the LPCVD method may be used.

As the first conductive film 405, it is necessary to form a film having excellent step coverage (step coverage) and a film having a conformal shape. In order to obtain a film having excellent step coverage, film forming conditions (temperature, pressure, gas flow rate, etc.) can be adjusted to obtain a desired shape.

Next, the first conductive film 405 was patterned and etched to form an independent capacitive element for each pixel.

Next, a second insulating film 406 is formed. Second
The insulating film 406 serves as a dielectric. Here, a SiO ₂ film is formed to a thickness of 0.1 μm by a sputtering method. If the film forming temperature is lower than the heat resistant temperature of the substrate, the plasma CVD method, the atmospheric pressure CVD method, or the LPCVD method may be used. Here as well, it is necessary to form a film having excellent step coverage (step coverage) or a film having a conformal shape, like the first conductive film 405. In this embodiment, the SiO ₂ film is formed, but the SiN _x film and the SiON film are formed.
A film, an inorganic film such as a SiNO film, or a laminated film thereof may be used.

A second conductive film 407 is formed. The second conductive film 407 serves as a grounded capacitor wiring. Here, the W film is formed by the sputtering method. Other than the W film, a conductive material such as Al, Ta, W, Cu or Mo may be formed. Here, the groove 30 is formed by the second conductive film.
2 embedded.

The third conductive film 4 is formed on the second conductive film 407.
No. 08, a WSi ₂ film was formed by the sputtering method. Third
The conductive film 408 plays a role of a light-shielding film, but when the first conductive film or the second conductive film 407 is a conductive film having a light-shielding property (for example, a W film), it functions as a light-shielding film. Since the third conductive film 408 can be sufficiently used, it is not necessary to form the third conductive film 408. The third conductive film 408 can be provided as needed. When the third conductive film 408 is formed, the second conductive film 407 and the third conductive film 408 serve as a capacitor wiring. The third conductive film 408 is W
In addition to the Si ₂ film, a silicide film such as MoSi ₂ or TiSi ₂ , a silicon film, a conductive material such as Al, Ta, W, Cu or Mo, or a laminated film thereof can be used.

Next, as in Example 1, the second conductive film 407 and the third conductive film 408 were patterned and etched to remove a part thereof in order not to reduce the aperture ratio. By doing so, the aperture ratio does not decrease, and it is possible to block the incidence of light on the TFT that is subsequently formed.

Then, a third insulating film 409 is formed to a film thickness of 100.
It is formed with a thickness of up to 1000 nm (FIG. 3B). Here, a laminated film of a SiON film and a SiNO film was formed by using the sputtering method. If the film forming temperature is lower than the heat resistant temperature of the substrate or the capacitive element, the plasma CVD method, the atmospheric pressure CVD method, or the LPCVD method may be used.

After forming the third insulating film 409,
The surface of the insulating film may be planarized by a process of chemically and mechanically polishing (typically a CMP technique). For example, the maximum height (Rmax) of the surface of the insulating film is 0.5 μm or less, preferably 0.3 μm or less. Thus, a structure having a capacitor element in the groove can be obtained (FIG. 3B).

[Embodiment 3] In this embodiment, a method of manufacturing an active matrix substrate using the substrate having the capacitive element structure manufactured in Embodiment 1 will be described with reference to FIGS. In this specification, a substrate in which a pixel portion including a driver circuit portion, a pixel TFT, and a storage capacitor is formed over one substrate is referred to as an active matrix substrate for convenience. The same reference numerals are used for the reference numerals. Note that, in FIGS. 4 to 8, for simplification, the left side of the center chain line is the drive circuit section and the right side of the center chain line is the pixel section.

Semiconductor films 308 to 308 are formed on the second insulating film 307.
Form 310. The semiconductor films 308 to 310 are formed by known means (sputtering method, LPCVD method, or plasma CV method).
25 to 80 nm (preferably 30 to 60) by D method etc.
nm) to form a semiconductor film, and a known crystallization method (laser crystallization method, thermal crystallization method using RTA or furnace annealing, thermal crystallization using a metal element that promotes crystallization). Method) to crystallize. Then, the obtained crystalline semiconductor film is patterned into a desired shape to form the semiconductor film 3
08 to 310 are formed. Examples of the semiconductor film include an amorphous semiconductor film, a microcrystalline semiconductor film, and a crystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment, a plasma CVD method is used to form an amorphous silicon film having a thickness of 55 nm. Then, a solution containing nickel is held on the amorphous silicon film, and this amorphous silicon film is dehydrogenated (500 ° C., 1 ° C.).
Time) and then thermal crystallization (550 ° C., 4 hours) to form a crystalline silicon film. Then, the semiconductor films 308 to 310 are formed by a patterning process using a photolithography method.

When a crystalline semiconductor film is produced by the laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby is used. A laser, a Ti: sapphire laser, or the like can be used. When these lasers are used, it is preferable to use a method in which a laser beam emitted from a laser oscillator is linearly condensed by an optical system and is applied to a semiconductor film. The crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 7
00 mJ / cm ² (typically 200-300 mJ / cm
² ) When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density is set to 300 to 1000 mJ /
cm ² (typically 350 to 500 mJ / cm ² ) is preferable. And a width of 100 to 1000 μm, for example 400 μm
It is also possible to irradiate a laser beam linearly condensed with m over the entire surface of the substrate and set the overlapping ratio (overlap ratio) of the linear beams at this time to 50 to 99%.

However, in this embodiment, since the amorphous silicon film is crystallized using the metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, 50 to 100 nm is formed on the crystalline silicon film.
Of the amorphous silicon film, and heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed to diffuse the metal element into the amorphous silicon film. Is removed by etching after the heat treatment.
By doing so, the content of the metal element in the crystalline silicon film can be reduced or removed.

After forming the semiconductor films 308 to 310, a slight amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

Next, a gate insulating film 311 which covers the semiconductor films 308 to 310 is formed. The gate insulating film 311 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
It is formed of an insulating film containing silicon with a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio Si = 32%, O = 59%, N =) having a thickness of 110 nm is formed by the plasma CVD method.
7%, H = 2%). Of course, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orl) is formed by plasma CVD.
Thosilicate) and mixed with O _2, and reaction pressure 40 Pa, a substrate temperature of 300 to 400 ° C., a high frequency (1
It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can be provided with excellent characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, a film having a thickness of 20 is formed on the gate insulating film 311.
A fourth conductive film 312 having a thickness of 100 nm and a thickness of 100 to 4
A fifth conductive film 313 having a thickness of 00 nm is formed by stacking. In this embodiment, a fourth conductive film 312 made of a TaN film having a film thickness of 30 nm and a fifth conductive film 313 made of a W film having a film thickness of 370 nm are stacked. The TaN film was formed by a sputtering method and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by the sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and the resistivity of the W film is 20 μΩc.
It is desirable to be m or less. Although the resistivity of the W film can be lowered by enlarging the crystal grains, when the W film contains many impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in the present embodiment, the W film is formed by the sputtering method using a high-purity W (purity 99.9999%) target, and with careful consideration that impurities are not mixed from the gas phase during film formation. By forming, a resistivity of 9
˜20 μΩcm could be realized.

In this embodiment, the fourth conductive film 312 is used.
Is TaN and the fifth conductive film 313 is W, but is not particularly limited and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr or Nd, or an alloy material or a compound material containing the above element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, AgP
You may use dCu alloy. In addition, the fourth conductive film is formed of a tantalum (Ta) film, the fourth conductive film is formed of a W film, the fourth conductive film is formed of a titanium nitride (TiN) film, and the fifth conductive film is formed. Is a W film, the fourth conductive film is a tantalum nitride (TaN) film, the fifth conductive film is an Al film, and the fourth conductive film is a tantalum nitride (TaN) film. The fifth conductive film may be a combination of Cu films.

Next, masks 314 to 317 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
The first etching process is performed under the first and second etching conditions. (FIG. 5A) In this embodiment, as the first etching condition, ICP (Inductive C) is used.
open plasma (inductively coupled plasma) etching method, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the gas flow ratio of each gas is 25: 25: 1.
At 0 (sccm), RF (13.56 MHz) power of 500 W was applied to the coil-shaped electrode at a pressure of 1 Pa to generate plasma for etching. RF (13.56 MHz) power of 150 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage.
The W film is etched under the first etching condition so that the end portion of the fourth conductive film is tapered.

Thereafter, the mask 314 made of resist is used.
Without removing 317, the second etching condition was changed, CF ₄ and Cl ₂ were used as etching gases, and the respective gas flow rate ratios were set to 30:30 (sccm) to form a coil-type electrode at a pressure of 1 Pa. RF of 500W (13.56MHz)
Power was applied to generate plasma and etching was performed for about 30 seconds. An RF (13.56 MHz) electric power of 20 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is adjusted to
The ends of the fourth conductive film and the fifth conductive film are tapered due to the effect of the bias voltage applied to the substrate side. The angle of this tapered portion is 15 to 45 °. Thus, the first shape conductive films 318 to 321 (the fourth conductive films 318a to 321a and the fifth conductive films 318b to 32) including the fourth conductive film and the fifth conductive film are formed by the first etching treatment.
1b) is formed. 322 is a gate insulating film,
The area not covered with the conductive films 318 to 321 having the shape
A thinned region is formed by etching about 50 nm.

The second mask is formed without removing the resist mask.
The etching process is performed. (Fig. 5 (B)) Here,
CF ₄ , Cl _2, and O ₂ are used as an etching gas, and the W film is selectively etched. At this time, the fifth conductive layers 323b to 326b are formed by the second etching treatment.
On the other hand, the fourth conductive films 323a to 326a are hardly etched, and the second conductive films 323 to 326 are formed.

Then, the first doping process is performed without removing the resist mask, and the impurity element 327 imparting n-type conductivity is added to the semiconductor layer at a low concentration. The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10.
^{13 to} 5 × 10 ¹⁴ / cm ² and accelerating voltage of 40 to 80 k
Perform as eV. In this embodiment, the dose amount is 1.5 × 1
0 ¹³ / cm ² and accelerating voltage of 60 keV. An element belonging to Group 15 is used as the impurity element imparting n-type, typically phosphorus (P) or arsenic (As), but phosphorus (P) is used here. In this case, the conductive layer 3
23 to 326 serve as masks for the impurity element imparting n-type, and impurity regions 328 to 330 are formed in a self-aligned manner. 1 × 10 ¹⁸ to the impurity regions 328 to 330
An impurity element imparting n-type conductivity is added within a concentration range of 1 × 10 ²⁰ / cm ³ (FIG. 6A).

After the mask made of resist is removed, new masks 332a to 332c made of resist are formed, and an impurity element imparting n-type is added by the second doping process at an acceleration voltage higher than that of the first doping process. Added. The condition of the ion doping method is that the dose amount is 1 × 10 ¹³ to
1 × 10 ¹⁵ / cm ² and accelerating voltage of 60 to 120 ke
Perform as V. The doping process is performed on the fifth conductive film 32.
Using 3b to 326b as a mask for the impurity element, doping is performed so that the impurity element is added to the semiconductor layer below the fourth conductive film. Subsequently, the accelerating voltage is lowered from the second doping process and the third doping process is performed, and an impurity element imparting n-type is added to obtain the state of FIG. 6B. The condition of the ion doping method is that the dose amount is 1 × 1.
0 ¹⁵ to 1 × 10 ¹⁷ / cm ² and an acceleration voltage of 50 to 10
Perform as 0 keV. 1 × 10 is formed in the low-concentration impurity region (third impurity region) 334 overlapping with the fourth conductive layer by the second doping treatment and the third doping treatment.
An impurity element imparting n-type conductivity is added in the concentration range of ^{18 to} 5 × 10 ¹⁹ / cm ³ , and 1 × 10 ¹⁹ is added to the high concentration impurity regions (second impurity regions) 333, 335, 336, 337.
An impurity element imparting n-type is added within a concentration range of up to 5 × 10 ²¹ / cm ³ .

Of course, by setting an appropriate acceleration voltage,
The second doping process and the third doping process are 1
It is possible to form the low-concentration impurity region and the high-concentration impurity region by performing the doping process once.

Next, after removing the resist masks, new resist masks 338a and 338 are formed.
b is formed and a fourth doping process is performed. This 4th
By the doping process of, the fourth impurity region 340 and the fifth impurity region 341 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer to be the active layer of the p-channel TFT are formed. Form. In this embodiment,
Fourth impurity region 340 and fifth impurity region 341
Is formed by an ion doping method using diborane (B ₂ H ₆ ) (FIG. 7A).

In the fourth impurity region 340, 1 × 10 ²⁰ to
An impurity element imparting p-type conductivity is added within a concentration range of 1 × 10 ²¹ / cm ³ . The fourth impurity region 3
40 is a region to which phosphorus (P) was added in the previous step, but the concentration of the impurity element imparting p-type is 1.5 to 3
The conductivity type is p-type due to the double addition.

The fifth impurity region 341 is formed in a region overlapping the tapered portion of the fourth conductive film 324a, and has a p concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. An impurity element that imparts a mold is added.

Through the above steps, the impurity regions are formed in the respective semiconductor films.

Masks 338a and 338 made of resist
b is removed and a first interlayer insulating film 342 is formed. The first interlayer insulating film 342 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film having a thickness of 150 nm is formed by a plasma CVD method. Of course, the first interlayer insulating film 342 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

Then, heat treatment is performed to recover the crystallinity of the semiconductor film and activate the impurity element added to each semiconductor film. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method has an oxygen concentration of 1 ppm or less, preferably 0.1 p
The temperature may be 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere of pm or less, and 550 in this embodiment.
The activation treatment was performed by heat treatment at 4 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Further, heat treatment may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak against heat, activation is performed after forming an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) to protect the wiring and the like as in this embodiment. It is preferable to carry out a chemical treatment.

Then, heat treatment (1 at 300 to 550 ° C.)
Hydrogenation can be performed by performing a heat treatment for 12 hours. This step is a step of terminating the dangling bond of the semiconductor layer with hydrogen contained in the first interlayer insulating film 342. As other means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) or 3-1
300-450 ° C in an atmosphere containing 00% hydrogen
The heat treatment may be performed for 1 to 12 hours.

A second interlayer insulating film 34 made of an inorganic insulating film material or an organic insulating material is formed on the first interlayer insulating film 342.
3 is formed. In this example, an acrylic resin film having a thickness of 1.6 μm was formed.

After that, the first conductive film 303 and the pixel TFT
Through holes reaching the source region and the drain region are formed, and a source wiring 344 and a drain wiring 345 are formed. In addition, wirings 346 to 349 electrically connected to the respective impurity regions of the TFT of the driving circuit portion are formed (FIG. 7).
(B)). In this embodiment, the drain wiring 345 and the first conductive film 303 are formed as wiring for electrical connection, but the structure is not limited to this. Note that these wirings are formed by patterning a laminated film of a Ti film having a film thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a film thickness of 500 nm. Of course, the structure is not limited to the two-layer structure, and may be a single-layer structure or a laminated structure of three or more layers. The material of the wiring is not limited to Al and Ti. For example, T
Wiring may be formed by forming Al or Cu on the aN film and then patterning the laminated film on which the Ti film is formed.

Next, a third interlayer insulating film 350 is formed of an acrylic resin film (FIG. 8). After forming the third interlayer insulating film, the surface may be chemically and mechanically polished (typically, CMP technique) to improve the flatness. A light shielding film 351 is formed on the third interlayer insulating film. The light shielding film 351 is made of Cr
A film, a CrO ₃ film, a Ti film, a Ni film, a resin film in which a black dye or pigment is dispersed, or a laminated film of these can be used.
The light shielding film 351 prevents light from entering the semiconductor film 310 from above. Although the light-shielding film is provided on the third interlayer insulating film in this embodiment, it is not limited to this and may be provided on the counter substrate.

A fourth interlayer insulating film 352 is provided. Of course, the flatness may be improved by chemically and mechanically polishing the surface after forming the fourth interlayer insulating film (typically, CMP technique). After that, in the pixel portion, the pixel electrode 353,
A gate wiring (not shown) and a connection electrode (not shown) are formed. The source electrode 344 is electrically connected to the pixel TFT by the connection electrode. The gate wiring is electrically connected to the gate electrode of the pixel TFT. In addition, the pixel electrode 353 is electrically connected to the drain region 335 of the pixel TFT, and is further electrically connected to one electrode forming a storage capacitor, that is, the first conductive film 303. Further, it is desirable to use a transparent conductive film such as an ITO film as the pixel electrode 353 (FIG. 8).

Further, also in the drive circuit portion 355, after forming the fourth interlayer insulating film 353, contact holes are formed to connect the wirings 346 to 349 to the source lines and the gate lines (not shown).

As described above, the n-channel TFT 36
0 and p-channel TFT 361 drive circuit section 36
2 and the pixel TFT 363 and the storage capacitor 364 can be formed on the same substrate. Thus
The active matrix substrate is completed.

[Embodiment 4] In this embodiment, a process of manufacturing a liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below.

After obtaining the active matrix substrate in the state of FIG. 8, an alignment film 354 is formed on the active matrix substrate of FIG. 8 and at least on the pixel electrode 353, and a rubbing process is performed. An insulating film may be formed over the pixel electrode 353 and the alignment film 354 may be formed thereover. As the alignment film 354, an organic film such as a polyimide film can be used. Also D
An inorganic film such as an LC (diamond-like carbon) film may be used. Further, the alignment film is not limited to the rubbing treatment, and the alignment film may be provided with an alignment function by irradiating with an electron beam. When the oblique vapor deposition film is used as the alignment film, the alignment treatment may be unnecessary.

Next, the counter substrate 358 is prepared. Next, a colored layer (not shown) is formed over the counter substrate 358. In this embodiment, the light shielding film 351 is formed on the substrate on which the pixel TFT is provided, but it goes without saying that the light shielding film may be formed on the counter substrate 358.

Next, a counter electrode 357 made of a transparent conductive film was formed on at least a pixel portion on a flattening film (not shown), an alignment film 356 was formed on the entire surface of the counter substrate, and rubbing treatment was performed. The same film as that provided over the active matrix substrate can be used for the alignment film 356. Further, the alignment film is not limited to the rubbing treatment, and the alignment film may have an alignment function by irradiating with an electron beam. An oblique deposition film may be used. After forming the flattening film, the surface may be chemically and mechanically polished (typically, CMP technique) to improve the flatness. Of course, an insulating film may be formed on the flattening film and the alignment film 356 may be formed thereon.

Then, the active matrix substrate on which the pixel portion and the drive circuit are formed and the counter substrate are bonded together by a known cell assembling process via a sealant and a spacer (both not shown). After that, the liquid crystal material 3 is placed between both substrates.
55 is injected and completely sealed by a sealant (not shown). As the liquid crystal material 355, nematic liquid crystal, cholesteric liquid crystal, ferroelectric liquid crystal, or antiferroelectric liquid crystal can be used. A polymer liquid crystal may be used. Further, a mixture of these liquid crystals with a resin and a mixture of dyes may be used. In this way, the liquid crystal display device shown in FIG. 9 is completed. In FIG. 9, only the TFT and the storage capacitor of the pixel portion having the features of the present invention are shown. T for drive circuit
It goes without saying that the FT is separately provided. Then, if necessary, the active matrix substrate or the counter substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, the FPC was attached using a known technique.

The liquid crystal display device manufactured as described above can be used as a display portion of various electronic devices.

[Embodiment 5] In this embodiment, a TFT when the active matrix substrate shown in Embodiment 3 is manufactured.
An example in which a light-emitting device is manufactured by using the manufacturing method of will be described. In the present specification, a light emitting device is a generic term for a display panel in which a light emitting element formed on a substrate is enclosed between the substrate and a cover material, and a display module including a TFT on the display panel. is there. Note that the light emitting element emits luminescence (El) generated by applying an electric field.
It has a layer (light emitting layer) containing an organic compound capable of obtaining electro luminescence, an anode layer, and a cathode layer. In addition, for luminescence in organic compounds,
Light emission when returning from singlet excited state to ground state (fluorescence) and light emission when returning from triplet excited state to ground state (phosphorescence)
And includes light emission of either or both of them.

In the present specification, all the layers formed between the anode and the cathode in the light emitting device are defined as the organic light emitting layer. The organic light emitting layer specifically includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, a light emitting device has a structure in which an anode layer, a light emitting layer, and a cathode layer are sequentially stacked. In addition to this structure, an anode layer, a hole injection layer, a light emitting layer, a cathode layer, and an anode layer are provided. It may have a structure in which a hole injecting layer, a light emitting layer, an electron transporting layer, a cathode layer and the like are laminated in this order.

FIG. 10 is a sectional view of the light emitting device of this embodiment. In FIG. 10, the switching TFT 500 provided on the substrate 502 is the n-channel TFT 35 of FIG.
3 is used. Therefore, the description of the structure may be referred to the description of the pixel TFT 353 of the third embodiment.

Although the double gate structure in which two channel forming regions are formed is used in this embodiment, a single gate structure in which one channel forming region is formed or a triple gate structure in which three channel forming regions are formed is also possible. good.

Although only the switching TFT and the storage capacitor are shown in FIG. 10, it goes without saying that a TFT for a drive circuit is provided on the substrate 502. The structure is described in the n-channel TFT 35 of the third embodiment.
0 and the description of the p-channel TFT 351 may be referred to. Although the third embodiment has a single gate structure, it may have a double gate structure or a triple gate structure. Further, according to the manufacturing process of the present embodiment, in addition, a signal dividing circuit, a D / A converter, an operational amplifier,
Logic circuits such as a γ correction circuit can be formed on the same insulator, and a memory and a microprocessor can also be formed.

Further, in the present embodiment, the current control TFT
Is provided (not shown). The current control TFT is formed by using a p-channel type TFT. The description of the structure may be referred to the description of the p-channel TFT 351 of the third embodiment. Although the third embodiment has a single gate structure, it may have a double gate structure or a triple gate structure.

Reference numeral 504 is a pixel electrode (anode of a light emitting element) made of a transparent conductive film. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide or indium oxide can be used. Moreover, you may use what added gallium to the said transparent conductive film. Pixel electrode 50
4 is a flat interlayer insulating film 503 before forming the wiring.
Form on top. In this embodiment, it is very important to flatten the step due to the TFT by using the flattening film 503 made of resin. Since the light emitting layer that is formed later is very thin, the light emitting failure may occur due to the existence of the step. Therefore, it is desirable to flatten the light emitting layer before forming the pixel electrode so that the light emitting layer can be formed as flat as possible.

After forming the wiring (not shown), a bank 505 is formed as shown in FIG. Bank 505 is 10
It may be formed by patterning an insulating film containing 0 to 400 nm of silicon or an organic resin film.

Since the bank 505 is an insulating film,
Attention must be paid to the electrostatic breakdown of the device during film formation.
In this embodiment, carbon particles or metal particles are added to the insulating film that is the material of the bank 505 to lower the resistivity and suppress the generation of static electricity. At this time, the resistivity is 1 × 10 ⁶ to 1 × 1.
The addition amount of carbon particles or metal particles may be adjusted so as to be 0 ¹² Ωm (preferably 1 × 10 ⁸ to 1 × 10 ¹⁰ Ωm).

A light emitting layer 506 is formed on the pixel electrode 504. Although only one pixel is shown in FIG. 11, the light emitting layers corresponding to the respective colors of R (red), G (green), and B (blue) are separately formed in this embodiment. Further, in this embodiment, the low molecular weight organic light emitting material is formed by the vapor deposition method.
Specifically, a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 7-nm light emitting layer is formed thereon.
It has a laminated structure in which a 0 nm thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided. The emission color can be controlled by adding a fluorescent dye such as quinacridone, perylene or DCM1 to Alq ₃ .

However, the above example is an example of an organic light emitting material that can be used as a light emitting layer, and it is not necessary to limit to this. The light emitting layer (charge transporting layer or charge injecting layer) may be freely combined to form a light emitting layer (a layer for emitting light and for moving carriers therefor). For example, in this embodiment, an example in which a low molecular weight organic light emitting material is used as the light emitting layer is shown, but a medium molecular weight organic light emitting material or a high molecular weight organic light emitting material may be used. In the present specification, an organic light-emitting material having no sublimability and having a number of molecules of 20 or less or a chain of molecules having a length of 10 μm or less is referred to as a medium molecule organic light-emitting material. In addition, as an example of using a polymer organic light emitting material, the hole injection layer has a thickness of 20 nm.
Alternatively, a polythiophene (PEDOT) film may be provided by a spin coating method, and a para-phenylene vinylene (PPV) film having a thickness of about 100 nm may be provided on the polythiophene (PEDOT) film as a laminated structure. By using a PPV π-conjugated polymer, the emission wavelength can be selected from red to blue. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic light emitting materials and inorganic materials.

Next, a cathode 507 made of a conductive film is provided on the light emitting layer 506. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film. Of course, a well-known MgAg film (an alloy film of magnesium and silver)
May be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

A light emitting element is completed when the cathode 507 is formed. Note that the light-emitting element here refers to a diode formed by the pixel electrode (anode) 504, the light-emitting layer 506, and the cathode 507.

It is effective to provide the passivation film 508 so as to completely cover the light emitting element. As the passivation film 508, an insulating film including a carbon film, a silicon nitride film, or a silicon nitride oxide film is used, and the insulating films are used as a single layer or a stacked layer in which they are combined. At this time, it is preferable to use a film having good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC (diamond-like carbon) film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C. or lower, it can be easily formed over the light-emitting layer 506 having low heat resistance. Further, the DLC film has a high blocking effect on oxygen and can suppress oxidation of the light emitting layer 506. Therefore, it is possible to prevent the problem that the light emitting layer 506 is oxidized during the subsequent sealing step.

Further, a sealing material 509 is provided on the passivation film 508, and a cover material 510 is attached. An ultraviolet curable resin may be used as the sealing material 509, and it is effective to provide a substance having a hygroscopic effect or a substance having an antioxidant effect inside. In addition, in this embodiment, the cover material 510 is a glass substrate, a quartz substrate, or a plastic substrate (including a plastic film) on which carbon films (preferably diamond-like carbon films) are formed.

Thus, the light emitting device having the structure shown in FIG. 10 is completed. Note that it is effective to continuously perform the steps from the formation of the bank 505 to the formation of the passivation film 508 by using a multi-chamber system (or in-line system) film formation apparatus without exposing to the atmosphere. . Further, it is also possible to further develop and continuously process up to the step of attaching the cover material 510 without exposing to the atmosphere.

[Embodiment 6] The TFT formed by implementing the present invention can be applied to various modules (active matrix type liquid crystal module, active matrix type EL module) such as a driving circuit and switching. All electronic devices incorporating them can be completed. Examples of electronic devices include video cameras, digital cameras, head-mounted displays (goggles type displays), car navigations, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), and the like. Examples of those are shown in FIGS.
Shown in.

FIG. 18A shows a personal computer, which has a main body 3001, an image input section 3002, and a display section 30.
03, keyboard 3004 and the like.

FIG. 18B shows a video camera, which includes a main body 3101, a display portion 3102, a voice input portion 3103, operation switches 3104, a battery 3105, and an image receiving portion 310.
Including 6 etc.

FIG. 18C shows a mobile computer (mobile computer), which includes a main body 3201, a camera portion 3202, an image receiving portion 3203, operation switches 3204, a display portion 3205, and the like.

FIG. 18D shows a goggle type display, which includes a main body 3301, a display section 3302 and an arm section 330.
Including 3 etc.

FIG. 18E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) in which a program is recorded.
3, a recording medium 3404, operation switches 3405 and the like. This player uses a DVD (D
optical Versatile Disc), CD
It is possible to play music, watch movies, play games, and use the internet.

FIG. 18F shows a digital camera, which includes a main body 3501, a display portion 3502, an eyepiece portion 3503, operation switches 3504, an image receiving portion (not shown) and the like.

FIG. 19A shows a front type projector including a projection device 3601, a screen 3602 and the like.

FIG. 19B shows a rear type projector, which includes a main body 3701, a projection device 3702, and a mirror 370.
3, screen 3704 and the like.

Note that FIG. 19C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 19A and 19B. Projection devices 3601, 37
02 is a light source optical system 3801, mirrors 3802, 380
4 to 3806, dichroic mirror 3803, prism 3807, liquid crystal module 3808, retardation plate 380.
9, a projection optical system 3810. Projection optical system 38
Reference numeral 10 is composed of an optical system including a projection lens. Although the present embodiment shows an example of a three-plate type, it is not particularly limited and may be, for example, a single-plate type. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG. 19C. Good.

Further, FIG. 19D is a diagram showing an example of the structure of the light source optical system 3801 in FIG. 19C. In this embodiment, the light source optical system 3801 includes the reflector 3811, the light source 3812, the lens arrays 3813, and 3.
814, a polarization conversion element 3815, and a condenser lens 3816. The light source optical system shown in FIG. 19D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, the projector shown in FIG. 19 shows a case where a transmissive electro-optical device is used, and an application example of a reflective electro-optical device is not shown.

FIG. 20A shows a mobile phone, which is a main body 39.
01, voice output unit 3902, voice input unit 3903, display unit 3904, operation switch 3905, antenna 390
6. Image input unit (CCD, image sensor, etc.) 3907
Including etc.

FIG. 20B shows a portable book (electronic book) including a main body 4001, display portions 4002 and 4003, a storage medium 4004, operation switches 4005, an antenna 4006.
Including etc.

FIG. 20C shows a display, which includes a main body 4101, a support base 4102, a display portion 4103 and the like.

By the way, the display shown in FIG. 20 (C) is a medium-sized or large-sized display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate whose one side is 1 m and perform multi-chambering for mass production.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to the manufacturing methods of electronic devices in all fields. In addition, the electronic device of the present embodiment is
It can be realized by using any configuration of 6 combinations.

[0140]

According to the present invention, it is possible to obtain a capacitive element which can secure a sufficient capacitance value without lowering the aperture ratio. Further, since the capacitive element is provided below the TFT, it has an excellent effect that it also functions as a light shielding film.

[Brief description of drawings]

FIG. 1 is a diagram showing the present invention.

FIG. 2 is a diagram showing a manufacturing process of the present invention (Example 1).

FIG. 3 is a diagram showing a manufacturing process of the present invention (Example 2).

FIG. 4 is a diagram showing a manufacturing process of the present invention (Example 3).

FIG. 5 is a diagram showing a manufacturing process of the present invention (Example 3).

FIG. 6 is a diagram showing a manufacturing process of the present invention (Example 3).

FIG. 7 is a diagram showing a manufacturing process of the present invention (Example 3).

FIG. 8 is a diagram showing a manufacturing process of the present invention (Example 3).

FIG. 9 is a diagram showing a manufacturing process of the present invention (Example 4).

FIG. 10 is a diagram showing a manufacturing process of the present invention (Example 5).

FIG. 11 is a diagram showing the present invention.

FIG. 12 is a diagram showing the present invention.

FIG. 13 is a diagram showing the present invention.

FIG. 14 is a diagram showing a manufacturing process of the present invention (Example 1).

FIG. 15 is a diagram showing a manufacturing process of the present invention (Example 1).

FIG. 16 is a view showing a manufacturing process of the present invention (Example 2).

FIG. 17 is a diagram showing an equivalent circuit of one pixel of a liquid crystal display device.

FIG. 18 illustrates examples of electronic devices. (Example 6)

FIG. 19 illustrates an example of an electronic device. (Example 6)

FIG. 20 illustrates an example of an electronic device. (Example 6)

[Explanation of symbols]

101 substrate 102 groove or trench structure 103 first conductive film 104 First insulating film (dielectric) 105 second conductive film 106 third conductive film 107 second insulating film 108 semiconductor film 108a Channel formation region 108b Source region or drain region 108c LDD region 109 gate insulating film 110 gate electrode 111, 112 Source or drain electrode 113 Third Insulating Film (Interlayer Insulating Film) 300 substrates 301 mask 302 Groove or trench structure 303 First conductive film 304 First insulating film (dielectric) 305 Second conductive film 306 Third conductive film 307 Second insulating film 308 to 310 semiconductor film 311 Gate insulating film 312 Third conductive film 313 Fourth conductive film 314-317 mask 318-326 Conductive film 318a to 326a Third conductive film 318b to 326b Fourth conductive film 322 Gate insulating film 327 Impurity element 328 to 330 First impurity region 331 Impurity element 332a, 332b, 332c mask 333, 335, 336, 337 Second impurity region 334 Third Impurity Region 338a, 338b mask 340 Fourth Impurity Region 341 Fifth Impurity Region 342 First interlayer insulating film 343 Second interlayer insulating film 344 to 349 source electrode, drain electrode 350 Third interlayer insulating film 351 light-shielding film 352 Fourth interlayer insulating film 353 transparent electrode 354 Alignment film 355 liquid crystal material 356 Alignment film 357 transparent electrode 358 substrate 360 n-channel TFT 361 p-channel TFT 362 drive circuit section 363 pixel TFT (switching TFT) 364 holding capacity 400 substrates 401 Base film 402 first insulating film 403 mask 404 groove 405 First conductive film 406 Second insulating film (dielectric) 407 second conductive film 408 Third conductive film 409 Third insulating film 500 pixel TFT (switching TFT) 501 holding capacity 502 substrate 503 Interlayer insulation film 504 pixel electrode 505 bank 506 light emitting layer 507 cathode 508 passivation film 509 sealing material 510 cover material 1001 Gate signal line 1002 Source signal line 1003 Liquid crystal capacity 1004 holding capacity 1005 Pixel electrode part 1006 Common electrode signal line 1007 parasitic capacitance

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8234 H01L 27/06 102A 27/04 29/78 612Z 27/06 626C 27/08 331 619B 29 / 786 F term (reference) 2H090 HA04 HD05 JA06 LA01 LA04 2H092 GA17 GA21 JA24 JA28 JB04 JB62 NA25 PA01 5F038 AC04 AC05 AC10 AC15 AC16 AC17 AC18 AC19 EZ06 EZ20 5F048 AC10 BA16 BC06 5F110 AA21 AA30 BB02 DD12 DD02 CC02 BB02 BB02 BB04 BB04 DD14 DD15 DD17 DD21 DD25 DD30 EE01 EE02 EE03 EE04 EE05 EE06 EE09 EE14 EE23 EE28 EE44 EE45 FF02 FF03 FF04 HL06 HL04 HL04 HL03 GG04 GG04 GG04 GG04 HL12 HM14 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN34 NN35 NN36 NN42 NN44 NN45 NN46 NN47 NN48 NN54 NN55 NN73 PP01 PP0 2 PP03 PP04 PP05 PP06 PP10 PP24 PP29 PP34 PP35 QQ04 QQ11 QQ19 QQ23 QQ24 QQ25 QQ28

Claims (13)

[Claims] 1. A semiconductor device having a thin film transistor and a storage capacitor connected to the thin film transistor, wherein the storage capacitor is at least partially formed in a groove provided in a substrate. Characteristic semiconductor device. 2. A semiconductor device having a thin film transistor and a storage capacitor connected to the thin film transistor, wherein the storage capacitor is at least partly formed in a groove provided in a first insulating film on a substrate. A semiconductor device characterized in that it is formed in. 3. A semiconductor device having a thin film transistor and a storage capacitor connected to the thin film transistor, wherein the thin film transistor is provided on the storage capacitor through an insulating film, and the storage capacitor is A semiconductor device, wherein at least a part thereof is formed in a groove provided in the substrate. 4. A semiconductor device having a thin film transistor and a storage capacitor connected to the thin film transistor, wherein the storage capacitor is at least partly inside a groove provided in a first insulating film on a substrate. And the thin film transistor is provided over the storage capacitor element with a second insulating film interposed therebetween. 5. The thin film transistor according to claim 1, wherein the thin film transistor has a semiconductor film provided with a source region, a drain region, and a channel formation region, and the groove has a channel length of the semiconductor film. A semiconductor device provided in a direction parallel to the direction. 6. The thin film transistor according to claim 1, wherein the thin film transistor has a semiconductor film provided with a source region, a drain region, and a channel formation region, and the groove has a channel length of the semiconductor film. A semiconductor device provided in a direction perpendicular to the direction. 7. The thin film transistor according to claim 1, wherein the thin film transistor has a semiconductor film provided with a source region, a drain region, and a channel formation region, and the groove has a channel length of the semiconductor film. A semiconductor device provided in a direction parallel to the direction and a direction perpendicular to the direction. 8. The semiconductor device according to claim 5, wherein the semiconductor device is provided with a pixel electrode, a gate line and a source line, and the storage capacitor element is provided around the pixel electrode. A semiconductor device, wherein at least one of capacitive wirings forming the storage capacitive element forms an independent L-shaped pattern for each pixel. 9. The semiconductor device according to claim 8, wherein no groove is provided at a corner of the L-shaped pattern. 10. The semiconductor device according to claim 1, wherein the storage capacitor element is a lower light-shielding film of the semiconductor film. 11. The storage capacitor according to claim 1, wherein the storage capacitor element includes a first conductive film, a second conductive film and a dielectric, and the groove is the first conductive film. A semiconductor device, wherein the semiconductor device is embedded by the second conductive film and the dielectric. 12. An active matrix type liquid crystal display comprising the semiconductor device according to any one of claims 1 to 11. 13. An active matrix EL display comprising the semiconductor device according to any one of claims 1 to 11.