JP2003016774A - Storage circuit block and data write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that because a current is required to make to flow for each bit line when data are written simultaneously in a plurality of data bits belonging to the same column address, a current required for write-in is enlarged. SOLUTION: This device comprises a plurality of pairs of bit line comprising a first bit line and a second bit line, a plurality of storage cells storing information in accordance with the direction of a current flowing in the pair of bit line, at least one current driving source connected to at least one of pairs of bit line and making to flow a current in the first bit line and the second bit line of which the directions of current are reverse each other, at least one switch circuit connecting pairs of bit line and pairs of bit line, and a control circuit controlling a connection state of the switch circuit in accordance with information stored in the storage cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit block and a memory method for writing data by current driving. In particular, the present invention relates to a storage circuit block and a storage method that share one current path for writing data in a plurality of storage cells by connecting bit lines to which the storage cells to which data is to be written are connected.

[0002]

2. Description of the Related Art A magnetic random access storage device,
FIG. 7 shows a side view of a conventional memory cell.

FIG. 7 shows a 1 Kbit MRAM chip and 5
Traditional 1 used for 12-bit MRAM chips
T (1 Transistor) 1 MTJ (1 Magnetic Tunnel Jun
ction magnetic junction device type memory cell 700 is shown.

The MTJ element 728 has a pinned magnetic layer 726, which is a ferromagnetic layer whose magnetization direction is fixed, and a tunnel barrier 724, which is an insulating layer through which a tunnel current passes.
A non-volatile data storage element composed of at least three thin films, including a free ferromagnetic layer 722, which is a ferromagnetic layer whose magnetization direction changes according to the direction of magnetization from the outside (however, free ferromagnetic Layer 722 and pinned magnetic layer 7
The position of 26 may be reversed).

Bit line 744 electrically connected to MTJ element 728 is used as a line for read and write operations. MX, V2, M in the figure
First wiring structure 7 composed of 2, V1, M1, and CA
17 through the MTJ element 728 and MOSFET 718
Is connected to the diffusion region n of the drain (D). In addition, MX, M1 and M2 are metal wire layers, and V1, V2
And CA are holes (via holes) formed in the insulating layer and the body is embedded in the holes. The gate of MOSFET 718 is the read word line 720,
A voltage is applied to this read word line 720 during a read operation to turn on MOSFET 718. This forms a current path from bit line 744 to ground 731 via MTJ element 728.

The resistance of the MTJ element 728 is determined by the fixed magnetic layer 7
The read current value flowing through the resistance of the MTJ element 728, which is determined by the magnetization direction of the free ferromagnetic layer 722 with respect to the magnetization direction of No. 26, or the voltage value determined by the resistance and current, is stored in the MTJ element 728. Data is read. For example, if the magnetization direction of the free ferromagnetic layer 722 is the same as the magnetization direction of the fixed magnetic layer 726, it is “0”, and if it is opposite, it is “1”.

In contrast to such a typical 1T1MTJ type cell, a cell called a twin cell is known.

FIG. 8 shows a conventionally known 2T2MTJ.
FIG. 7 is a diagram showing a so-called twin cell 800, which is a (2Transistor 2Magnetic Tunnel Junction) type memory cell. This is an MRAM memory cell using two MTJ elements and two transistors. Since the principle of one memory circuit is the same as that in FIG. 7, the same components as those in FIG. The description thereof will be omitted. It should be noted that the reference numerals of the constituent elements of the adjacent memory circuits are attached with “′” to distinguish the memory circuits. A characteristic of this type of memory cell is that there is a corresponding number of bit lines for storage cells per cell.

In this type of memory cell, for example, a write current path is formed in a loop shape, and a current is passed in the opposite direction to an adjacent memory circuit in the cell to write mutually opposite data in each memory circuit. You can In addition, the magnitude of noise can be suppressed thereby. That is, it has a doubled driving capability with substantially the same current value. When reading, T bit line (true bit
line) and C bit line (complement bit line) from the respective storage circuits, the opposite data is taken out as a differential signal, so that the read signal is 1T1M.
It is twice as large as that of the TJ cell, and noise-resistant reading is possible. However, the current path does not have to be configured in a loop, and T bit line 744 and C bit line 7
If a current flows in the opposite direction to 44 ', writing can be performed.

FIG. 9 shows an MRA using this twin cell.
It is a block diagram of the memory block of M. In this write circuit, when the drive current IWL flows through the write word line 716 corresponding to the row and the current flows through both the bit lines corresponding to the columns, the magnetic field generated in the memory cell at the intersection is generated. Data is written depending on the orientation of. Here, the logical data "0" and "1" are written according to the direction of the current flowing through the bit line.

In FIG. 9, bit lines 744 and 74 connected to the write current driving circuit 910 on the right side of the drawing.
Because 4'is connected in a loop, the direction of current flow in T-bit line 744 and the direction of current flow in C-bit line 744 'are opposite to cell 800.

In this configuration, for example, as shown, T bit line 744 to C bit line 7
It is possible to write "1" when the current flows in the direction toward 44 'and write "0" in the opposite case (the left side of the drawing).

[0013]

However, in the configuration as shown in FIG. 9, for example, when data is simultaneously written in a plurality of data bits belonging to the same column address, it is necessary to supply a current for each bit line. However, there is a problem that the current required for writing becomes large.

For example, in a 1 Kbit MRAM, it is known that the current required to flow through the bit line to obtain a desired magnetic field and perform stable writing is about 10 mA.

Therefore, when a plurality of bits of data are simultaneously written, if a drive circuit is prepared according to the data of each bit as in the conventional semiconductor memory device, an n times larger current is required to write n bits of data. Will be needed.
For example, if the word length is 64 bits, the current required for writing exceeds 600 mA.

This value is quite large, and since this value is the average current value, the peak current is several times that, and the current changes over time. Furthermore, this causes the generation of noise due to the inrush current and an increase in the load on the power supply circuit.

[0017]

A memory circuit block according to the present invention includes a plurality of bit line pairs including a first bit line and a second bit line, and a current flowing through the bit line pair. A plurality of storage cells for storing information depending on the direction, and at least one of which is connected to at least one of the bit line pairs and causes currents in opposite directions to flow in the first bit line and the second bit line. A current drive source, at least one switch circuit that connects the bit line pair and the bit line pair, and a control circuit that controls a connection state of the switch circuit according to information stored in a memory cell. There is.

In the memory circuit block according to the present invention, the bit line pairs may be connected in series, and the bit line current path may be formed in a loop.

In the memory circuit block according to the present invention, a current path connecting the ends of the first bit line and the second bit line in the bit line pair may be connected in series as a unit.

The memory circuit block according to the present invention is
Information may be stored in an MTJ (Magnetic Tunnel Junction) element.

Further, the memory cell may have a so-called twin cell structure including two MTJs per bit.

According to the storage method of the present invention, the first bit
A plurality of bits including a line and a second bit line
At least one current drive source connected to at least one of the pair of lines, which flows currents in opposite directions to the first bit line and the second bit line, and a switch connecting the pair of bit lines. A method of storing information in a plurality of memory cells in which information is stored in accordance with the direction of a current flowing through the bit line pair by a memory circuit block including a circuit and a switch circuit control circuit that controls the switch circuit. Then, the step of selecting a memory cell, the step of controlling the connection state of the switch circuit according to the information stored in the selected memory cell, and the switch circuit connecting the bit line pair and the bit line pair. Connecting step so that the current flows in the opposite direction to the first bit line and the second bit line connected to the current driving source. Flow drive source comprises flowing a current.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A magnetic random access memory (M) that generates a magnetic field by an electric current and writes information according to the direction of the magnetic field.
Embodiments relating to a circuit and a method for reducing a drive current in a RAM) will be described.

In this embodiment, for example, the word length is 8
A circuit for reducing a write current and a method of storing in an MRAM when a memory array such as MRAM having a long multi-bit structure such as bits, 16 bits, ... 64 bits, 128 bits, etc. is configured. .

The present invention resides in sharing one current path for writing data in a plurality of storage cells by connecting bit lines to which the storage cells to write data belong to in series with each other. However, since it is necessary to write arbitrary data for each cell, the connection method is controlled by the data to be written.

FIG. 1 is a block diagram of a storage block 10 showing an embodiment of the present invention. FIG. 1 shows an example of how bit lines are connected in series and an arrangement of switches for switching the connections.

In FIG. 1, the 0th bit line pair, the (K-1) th bit line pair and the Kth bit line pair as seen from the write current drive circuit 12 are connected via the switch section 20b. The bit line pair connection section 18 connected by the above and the final stage of the (n-1) th bit line pair are described.

Since the connection state on the way is the same, but it is repeated, the switch section 2 for connecting the pair of the C bit line 14 and the T bit line 15 respectively while omitting the way.
0a and 20c are represented.

In FIG. 1, the numbers are given from the 0th. Further, in FIG. 1, only bit lines belonging to the same column address corresponding to data bits to which data is simultaneously written, a part of a memory cell, and a circuit related to writing are clearly shown.

In the memory block 10, the write current drive circuit 12 and one end of a pair of a C bit line (Complement) 14 and a T bit line (True) 15 are connected. The T-bit line 15 and the C-bit line 14 have complementary current directions.

The other end of the pair of C bit line 14 and T bit line 15 is connected to the C bit line 14 and T bit line 15 via a switch.

C bit line 1 in the (n-1) th final stage via the bit line pair connection 18
4 and T bit line 15 are connected at the ends.

The memory block 10 is configured such that the n-1th C bit line 14 and the T bit line 15 are connected at the ends so that the current is circulated between the memory block 10 and the write current drive circuit 12. Has been done.

Of course, the current source may be reinforced by providing a second current drive circuit without connecting the termination of the (n-1) th bit line pair.

The operation of the storage block 10 in FIG. 1 having the above configuration will be described. In FIG. 1, it is assumed that 1 is written in the selected memory cell when a current flows through the T bit line 15 in the downward direction of the drawing. The switch is located below the array to be stored between the even numbered bit line pairs and the numbered bit line pairs greater by one, and the odd numbered bit line pairs and It is assumed that it is arranged above the storage cell array between the bit line pair numbered by 1 more.

A circuit for driving a current for writing, that is, a write current driving circuit 12 is a bit
Outside the line pair, on the bit line with number 0, writing 0 or 1 to the selected storage cell determines the signal line that sends out the current, and draws the current from the other line. It will be.

With this arrangement, the current delivered from the write current drive circuit flows from top to bottom for even numbered bit line pairs and from bottom to top for odd numbered bit line pairs. Become. Write current drive circuit 12
The current drawn into is the opposite.

FIG. 2 shows a block diagram of the memory block 10 of FIG.
FIG. 3 is a diagram showing a bit line pair connection unit 18. K-1
The th bit line pair and the K th bit line pair are connected via the switch unit 20b. In FIG. 2, the k−1th C bit line 14 is the C bit line 14-1, and the kth C bit line 14 is the C bit line 14-1.
The bit line 14-2 and the (k-1) th T bit line 15 are coded as T bit line 15-1 and the kth T bit line 15 as T bit line 15-2. To do.

Of the word lines 26, 16, 28,
Data is written to the memory cells 22 and 24 where the current flowing in the word line 16 and the current flowing in the bit line pair intersect.

Writing a 0 to the selected storage cell 22 on the bit line having an even number k and writing a 1 to the selected storage cell 24 on the bit line having the number k-1. To do.

In this case, the bit to which the selected memory cell 20 on the bit line having an even number k belongs
Since it is necessary to pass a current downward in the C bit line 14-2 and a current upward in the T bit line 15-2 of the line pair, a write current driving circuit ( It is necessary to pass the current sent from the write current drive circuit 12) of FIG.

On the other hand, on the bit line with the number k-1, the upward current is applied to the C bit line 14-1 of the bit line pair to which the selected memory cell 22 belongs, and T bit is applied. Since it is necessary to pass current downward in line 15-1, this C bit line 14-1
Also, the current sent from the write current drive circuit 32 flows.

Therefore, the k-1th bit line pair and k
The switch 20b between the second bit line pair is C
The bit line 14-1 (BLCK-1) and the C bit line 14-2 (BLCK) are connected to each other, and the T bit line 15-1 (BLTk-1) and the T bit line 15-2 (B) are connected.
LTk) will be connected.

Since there are only four combinations of data to be written in the memory cells 22 and 24, considering the same in the other three cases, when different data are written to the memory cells 22 and 24, T It can be seen that the bit lines are connected to each other and the C bit lines are connected to each other, and when the same data is written, the T bit line and the C bit line are connected.

The above is the case of the switch between the bit line pair having an odd number and the bit line pair having a number larger by 1 than that, but the bit line pair having an even number and a number larger by 1 than that. It will be understood that the same control can be applied to the switch between the bit line pair having the line.

FIG. 3 is a block diagram of a memory circuit block 30 which is another embodiment of the present invention. In the memory block 30 shown in FIG. 3, the pair of C bit line 14 and T bit line 15 is configured with a loop connecting terminations as one unit. In FIG. 3, the 0th bit line pair, the (K-1) th bit line pair, and the Kth bit line pair as seen from the write current drive circuit 12 are connected via the switch section 36c. The bit line pair connection section 40 and the (n-1) th final stage are described. The switch section 36b or 36d for connecting the pair of the C bit line 14 and the T bit line 15 respectively is also shown while omitting the middle.

It should be noted that, also in FIG. 3, as in FIG.
Numbering from th. Further, also in FIG. 3, as in FIG. 1, only the bit lines belonging to the same column address corresponding to the data bits to which data is simultaneously written, a part of the memory cell, and a circuit related to writing are shown.

One end of the write current drive circuit 12 and the 0th C
The bit line 14 or the T bit line 15 is connected in a switchable state by the switch section 36a. Further, the other end of the write current drive circuit 12 and the (n-1) th C bit line 14 or T bit line 15 are
The switches 36e are connected in a switchable state.

With respect to the first to (n-1) th pairs of the C bit line 14 and the T bit line 15, the C bit line 14 is used as a unit with the loop connecting the terminations as one unit.
And T bit line 15 pairs are connected via switches.

Further, the bit line pair at the final stage is also connected to the switch section 36d, but the connection state in the middle is repeated, so that it is omitted as in FIG.

The operation of the storage block 30 in FIG. 3 under the above structure will be described. If current flows through the word line 16, data is written at the intersection of the word line and the bit line pair through which current flows.

Since the T side and the C side are connected at the lower end of the bit line pair, when the current flows in from the T bit line 15 and the current flows out from the C bit line 14, the selected memory cell is selected. Is written to 1 and vice versa.

Here, the switch section 36c between the bit line pair having the number k-1 and the bit line pair having the number k is referred to as a switch SWk, and the write current drive circuit and the bit line having the number 0. Switch part 3 between the pair
6a is SW0, and the switch unit 36d between the bit line pair having the number n-1 and the write current drive circuit 12 is SWn.
I will call it.

It is assumed that the write current drive circuit 12 sends out current from the lower terminal and absorbs current from the upper terminal in writing any data. Under the above settings, which of the switch parts 36a (SW0) is turned on depends on whether 0 or 1 is written in the selected memory cell on the bit line having the number 0.

The control of the switch unit 36c (SWk) is selected on the bit line having the number k-1 and the data to be written in the selected memory cell and the bit line having the number k. It depends on the data to be written in the memory cell.

Further, which of the switch units 36e (SWn) is turned on depends on whether 0 or 1 is written in the selected memory cell on the bit line having the number n. Thus, depending on the data to be written,
Each switch will be controlled.

FIG. 4 is a block diagram of the memory block 30 of FIG.
It is a figure showing the bit line pair connection part 40 which shows the connection with the (K-1) th bit line pair and the Kth bit line pair.

In FIG. 4, the k-1th C bit
The line 14 is a C bit line 14-1, and the kth C bit line 14 is a C bit line 14-2, k-1.
Th T-bit line 15 to T-bit line 15-
The first and kth T-bit lines 15 will be described as T-bit lines 15-2.

When 0 is written in the selected memory cell on the bit line having the number k and 1 is written in the selected memory cell on the bit line having the number k−1. Think

Since 0 is written in the selected memory cell on the bit line having the number k, a current flows from the C bit line 14-2 in the bit line pair having the number k, and T bit. Current must flow out of line 15-2.

Since the current flows from the bit line pair with the smallest number, the switch unit 36c (SWk) outputs C
Bit line 14-2 (BLCk) is T bit line 15-1 (BLTk-1) or C bit line 14-1
You have to connect to (BLCk-1).

On the other hand, since 1 is written in the selected memory cell on the bit line having the number k-1, the current from the bit line on the T side in the bit line pair having the number k-1. Must flow in and current must flow in the bit line on the C side.

From the above, the switch section 36c (SWk)
Connects C-bit line 14-1 (BLCk-1) and C-bit line 14-2 (BLCk) to T-bit.
Line 15-1 (BLTk-1) is T bit line 15
-2 (BLTk) and C bit line 14-2 (BL
Ck) has nothing to do with it.

FIG. 5 shows the switch section 20a in FIG.
It is an example of a specific circuit diagram of 20b and 20c. In FIG. 1, how to connect the switches depends on whether the same data or different data is written in the adjacent memory cells. Therefore, the control circuit of the switch can be configured using the coincidence circuit (EXNOR) or the anti-coincidence circuit (EXOR) which inputs adjacent data bits.

The specific circuit of the switch shown in FIG. 5 is a switch circuit control circuit 505 including an exclusive OR circuit 510 and a NOT circuit 520, and MOSFETs 530 to 530.
And a switch circuit 525 including 60.

Hereinafter, the switch of FIG. 5 is assumed to be the switch unit 20b of FIGS. 1 and 2, and the same reference numerals as those of the bit lines shown in FIG. 2 will be described.

The switch unit 20b is connected to the two-input exclusive OR circuit of the k−1th data input 500 and the kth data input 502 and the output of the exclusive OR circuit, and a NOT circuit for inverting the output. 520 and the output of the exclusive OR circuit 510 as a gate input to the C bit line 1
NMOSFET 540 connecting 4-1 and 14-2 and N connecting T bit lines 15-1 and 15-2.
The MOSFET 550 and the NMOSFET 530 connecting the C bit line 14-1 and the T bit line 15-2 with the output of the NOT circuit 520 as a gate input and the T bit line 15-1 and the C bit line 14-2 are connected. The NMOSFET 560 is configured to operate.

When the data input 500 and the data input 502 match, the output of the exclusive OR circuit is L, and the output of the NOT circuit 520 is H. Therefore, in this case, C bit line 14-1 and T bit line 1
5-2 is connected, and C bit line 14-2 and T bit line 15-1 are connected.

As a result, the C bit lines 14-1 and 14-2 in FIG. 1 have the same current direction.

In this way, the switch circuit control circuit 505
The bit line connection state can be controlled depending on the data to be written.

Since there are only four combinations of data to be written in the memory cells 22 and 24, the memory cells 22 and 24 can be similarly considered in the other three cases.
It can be seen that when writing different data to the T bit line, the T bit line and the C bit line are connected, and when writing the same data, the T bit line and the C bit line are connected.

This is the case for a switch between a bit line pair with an odd number and a bit line pair with a number one higher than that, but with a bit line pair with an even number and one more than that. Similar control may be applied to switches between bit line pairs having a large number.

In the integrated circuit, the switch is actually composed of a MOS transistor or the like. Further, the other bit line pair connecting portions are not limited to the switch circuit portion 20b, but the switch portion 20a and the switch portion 2
A circuit example for realizing 0c can be realized by the one shown in FIG.

FIG. 6 shows the switch section 36b in FIG.
It is an example of a concrete circuit diagram of 36c and 36d. In FIG. 2, the combination of data to be written to the selected memory cells belonging to the bit line pair on both sides of the switch determines the 2-bit data.

The specific circuit of the switch section shown in FIG.
NOT circuits 604, 606 and AND circuits 608 to 6
Switch circuit control circuit 603 including 14 and MOS
The switch circuit 625 includes the FETs 630 to 660.

Hereinafter, the switch of FIG. 6 is assumed to be the switch unit 36c in FIGS. 3 and 4, and the same reference numerals as those of the bit lines shown in FIG. 4 are the same.

The switch section 36c receives the k-1th data input 600 and the kth data input 602 as inputs.
NOT circuits 604 and 6 for respectively inverting these inputs
06 and the data input 600, 602 or the negation circuit 60
4 and 606, AND circuits 608 to 614 which receive any two of the input signals inverted, and C bit line 14-1 and T bit line 15 with the output of AND circuit 608 as the gate input. -2 and an NMOSFET 630 for connecting the C-bit line 14-1 and the C-bit line 14-1 with the output of the AND circuit 610 as a gate input.
An NMOSFET 640 connecting the line 14-2,
With the output of the AND circuit 612 as the gate input, T bits
An NMOSFET 650 connecting the line 15-1 and the T bit line 15-2, and an NMOSFET 660 connecting the T bit line 15-1 and the C bit line 14-2 with the output of the AND circuit 614 as a gate input. Composed of.

The switch section functions as a data decoder, and the outputs of the NOT circuits 604 and 606 are connected to decoders for other data (not shown).

The operation of the switch section 36c will be described. When both data inputs 600 and 602 are L, the output of the AND circuit 614 becomes H and the NMOSFE
When T660 is turned on and both are H, the output of the AND circuit 608 becomes H and the NMOSFET 630 is turned on.

On the other hand, when the data input 600 is H and the data input 602 is L, the AND circuit 610 is H and the NMOSFET 640 is ON, and in the opposite case, the output of the AND circuit 612 is H. Become NMOSFET 65
0 turns on. In this way, the combination of each data determines the connection of the bit line pair.

In the integrated circuit, the switch is actually composed of a MOS transistor or the like.

A circuit example for realizing each circuit of the switch units 36b and 36d, not limited to the switch unit 36c, may be that shown in FIG.

As described above, in the embodiment in which the bit line pairs are connected in series, the write current is reduced to 1 / n in the case of the memory device having the n-bit structure in which the writing is performed by the current drive. be able to.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to these specific examples. For example, even with one series connection, there may be various changes in the connection method. Also,
There may be various choices and modifications regarding how many bit line pairs are connected in series.

For example, the number of bit line pairs connected in series is the maximum current value allowed for writing in the entire memory device, the resistance value of the bit line pair and the switch, the required writing speed, and the memory cell array. It can be determined by the configuration, etc. Further, in the case of a memory device having a structure of 1 word 64 bits, a bit line for 16 bits is directly connected, and a bit line driving circuit for writing is 4
Modifications such as providing individual pieces are also possible.

In the above figures, a twin cell having MTJ as a memory element is described as an example. However, in the memory circuit block and the memory method of the present invention, such a twin cell and a plurality of memory cells are used. It is not limited to a memory cell including an element. In short, one memory cell has two or more write bit lines, and each current drive type cell can be applied as long as each current can be controlled.
Therefore, it is needless to say that the invention described in all the claims should not be limited to the twin cell in the interpretation of the claims.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a storage block 10 according to the present invention.

FIG. 2 is a diagram showing a bit line pair connection unit 18.

FIG. 3 is a configuration diagram of a storage block 30 which is another embodiment of the storage block according to the present invention.

FIG. 4 is a diagram showing a bit line pair connection unit 40.

FIG. 5 is a specific circuit diagram of a switch circuit.

FIG. 6 is a specific circuit diagram of a switch circuit.

FIG. 7 is a side view of a conventional memory cell.

FIG. 8 is a circuit configuration diagram of a conventional twin cell.

FIG. 9 is a configuration diagram of a storage block of a conventional twin cell.

[Explanation of symbols]

10 memory blocks 12 Write current drive circuit 14 and 15 bit lines 16 word line 18-bit line pair connection 20a, 20b, 20c switch section 22, 24 memory cells 26, 28 word lines 30 memory blocks 36a, 36b, 36c, 36d, 36e switch section 40-bit line pair connection 500,502 Data input Control circuit for 505 switch circuit 525 switch circuit 530-560 MOSFET switch 600,602 data input 603 Control circuit for switch circuit 625 switch circuit 630-660 MOSFET switch 700 memory cells 713 Second wiring structure 716 write word line 717 First wiring structure 718, 718 'Switching element (MOSFET) 720 read word line 722 free ferromagnetic layer 724 tunnel barrier 726 pinned magnetic layer 728, 728 'Storage element (MTJ element) 730 insulation area 744, 744 'bit lines 800 twin cells 910 write current drive circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hisadamu Miyatake             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hiroaki Noda             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Hiroshi Umezaki             1 Kirihara Town, Fujisawa City, Kanagawa Japan Eye             BM Corporation Fujisawa Office (72) Inventor Hideo Asano             1 Kirihara Town, Fujisawa City, Kanagawa Japan Eye             BM Corporation Fujisawa Office (72) Inventor Toshio Sunaga             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house (72) Inventor Tsuneji Kitamura             800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture             Japan IBM Corporation Yasu Business             In-house F term (reference) 5F083 FZ10 GA05 GA12 KA05 LA10                       LA14

Claims (17)

[Claims] 1. A plurality of bit line pairs including a first bit line and a second bit line, and a plurality of storage cells for storing information according to directions of currents flowing through the bit line pairs. And at least one current drive source connected to at least one of the pair of bit lines, for supplying currents in opposite directions to the first bit line and the second bit line, and the bit line. A memory circuit block including at least one switch circuit that connects a pair and a bit line pair, and a control circuit that controls a connection state of the switch circuit according to information stored in the memory cell. 2. The storage element included in the storage cell is a storage element including a ferromagnetic layer whose magnetization direction is determined according to the direction of a magnetic field generated by a current flowing in each bit line. The memory circuit block according to claim 1. 3. The storage element is an MTJ (Magnetic Tunnel J
The memory circuit block according to claim 2, which is a unction element. 4. The storage cell has two Ms per bit.
The memory circuit block according to claim 3, which is a twin cell including a pair of TJ elements. 5. A plurality of bit line pairs including a first bit line and a second bit line, and a plurality of storage cells for storing information according to directions of currents flowing through the bit line pairs. And at least one current drive source connected to at least one of the pair of bit lines, for supplying currents in opposite directions to the first bit line and the second bit line, and the bit line. A bit line pair and at least one switch circuit that connects the pair to the bit line pair; and a control circuit that controls the connection state of the switch circuit according to the information stored in the memory cell. A switch circuit for connecting the first bit line pair and the second bit line pair for connecting the bit line pair to each other. Either connected to or to the first bit line and a switch circuit for connecting the second bit line in series with each other, the memory circuit block. 6. A first bit line and a second bit line of a bit line pair at the final stage in which the bit line pair is connected in series by a switch circuit are connected to each other,
The memory circuit block according to claim 5, wherein the current path is configured in a loop with respect to the current drive source. 7. The storage element included in the storage cell is a storage element including a ferromagnetic layer in which a direction of magnetization is determined according to a direction of a magnetic field generated by a current flowing in each bit line. The memory circuit block according to claim 5 or 6. 8. The storage element is an MTJ (Magnetic Tunnel J).
8. The memory circuit block according to claim 7, which is a unction element. 9. The storage cell comprises two Ms per bit.
9. The memory circuit block according to claim 8, which is a twin cell including a pair of TJ elements. 10. A memory circuit block for storing information in a memory cell according to the direction of a current flowing through a bit line, wherein ends of a first bit line and a second bit line are connected to each other. A plurality of bit line pairs, a current drive source for supplying a current to the plurality of bit line pairs, and a switch circuit for connecting one bit line pair and another one bit line pair are connected. A first bit line and a second bit line in series, or a first bit line and a second bit line in series in a pair of bit lines Switch circuit, and second and third switch circuits in which both ends of a bit line pair connected in series via the switch circuit are connected to a current driving source so as to form a loop, , The connection state of the second and third switch circuits,
A memory circuit block including a control circuit that controls according to information stored in a memory cell. 11. A storage element included in the storage cell includes a ferromagnetic layer whose magnetization direction is determined according to the direction of a magnetic field generated by a current flowing through each bit line. The memory circuit block according to claim 10. 12. The storage element is an MTJ (Magnetic Tunnel).
The memory circuit block according to claim 11, which is a junction element. 13. The memory circuit block according to claim 12, wherein said memory cell is a twin cell including two pairs of MTJ elements per bit. 14. A first bit line and a second bit line.
At least one current drive source connected to at least one of a plurality of bit line pairs including a line, and supplying currents in opposite directions to the first bit line and the second bit line. A storage circuit block including a switch circuit that connects the bit line pair and a switch circuit control circuit that controls the switch circuit causes a plurality of storage cells in which information is stored according to the direction of the current flowing through the bit line pair. A method of storing information to a memory cell, the method comprising: selecting a memory cell; controlling the connection state of a switch circuit according to the information to be stored in the selected memory cell; Connecting the pair and the bit line pair, a first bit line and a second bit line connected to the current drive source
A current source causes a current to flow in the opposite direction to the bit line of, and storing information in a memory cell comprising :. 15. The storage element included in the storage cell is a storage element including a ferromagnetic layer whose magnetization direction is determined according to the direction of a magnetic field generated by a current flowing in each bit line. The method according to claim 14. 16. The storage element is an MTJ (Magnetic Tunnel).
16. The method according to claim 15, which is a junction device. 17. The method of claim 16 wherein said storage cell is a twin cell containing two MTJ element pairs per bit.