JP2003046005A - Semiconductor memory and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase in chip area and raise the value of coupling ratio, especially at erasure operation for realizing low voltage operation, without sacrificing the operating characteristics of elements, such as reduction in cell current, etc. SOLUTION: Subsidiary polysilicon gates 16 are formed on a p-type silicon semiconductor substrate 10, so as to cross over control gates 15 and extend on element isolation regions 13. Floating gates 18 are formed on drain regions 11 via a dielectric film 17, each lying on the side of the control gate 15 facing the drain and the sides of the subsidiary gate 16 connected to a side facing the drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to an electrically erasable non-volatile semiconductor memory device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Recently, as a nonvolatile semiconductor memory device,
EPROM (Erasable and Programmable Read Only Me
mory) device, EEPROM (Electrically Erasable an
d Programmable Read Only Memory) device or FeRA
M (Ferro-electric Random Access Memory) devices and the like are attracting attention.

Of these, EPROM devices or EEPROMs
The device retains (stores) data by charging / discharging the floating gate and detecting a change in threshold voltage due to the presence / absence of charge in the floating gate by the control gate.
Further, as the EEPROM device, there is a flash EEPROM device capable of erasing data on a chip-by-chip basis.

The memory cells (memory transistors) constituting the flash EEPROM device are roughly classified into a stack gate type and a split gate type.

A flash EEPROM device using a stack gate type memory cell does not have a function of selecting the cell itself for each memory cell. Therefore, when the charges are extracted from the floating gate at the time of data erasing, if the charges are excessively extracted, the memory cells from which the charges have been excessively extracted become depletion, causing a non-selected cell to leak, which is a so-called over-erase problem. .

In order to prevent this excessive erasing, it is necessary to devise the erasing procedure, and it is necessary to control the erasing procedure by the peripheral circuit of the memory device or control the erasing procedure by the external circuit of the memory device.

A split gate type memory cell was developed in order to avoid this over-erasing, and its configuration is disclosed in, for example, US Pat. No. 5,029,130.

A flash EEPROM device using a split gate type memory cell has a function of selecting the cell itself for each memory cell. Therefore, even if over-erasing occurs, the memory cell becomes conductive or non-conductive. Can be controlled so that overerasure is not a problem.

A semiconductor nonvolatile memory (flash EEPROM) device using a conventional stack gate type memory cell or split gate type memory cell will be described below with reference to the drawings.

First, as shown in FIGS. 14A and 14B, in a stack gate type memory cell, a drain region 102 and a source region 103 are formed on a semiconductor substrate 101 made of silicon. Semiconductor substrate 10
A floating gate 106 is formed on the channel region 104 sandwiched between the drain region 102 and the source region 103 in No. 1 via the first dielectric film 105. A control gate 108 is formed on the floating gate 106 via a second dielectric film 107.
Are formed.

On the other hand, the split gate type memory cell is
As shown in FIGS. 15A and 15B, the drain region 102 is formed on the semiconductor substrate 101 made of silicon.
And the source region 103 are formed, and the semiconductor substrate 1
On the channel region 104 sandwiched between the drain region 102 and the source region 103 in 01, the first dielectric film 10 made of silicon oxide having a relatively small film thickness.
The control gate 108 is formed through the line 5. On the drain region 102 side of the control gate 108, a sidewall-shaped floating gate 106 is formed via a second dielectric film 107. The floating gate 106 has a small overlap with both the drain region 102 and the floating gate 106 and has a minute gate length.

By the way, the ratio of the electrostatic capacitance Cc between the control gate 108 and the floating gate 106 and the electrostatic capacitance Cf between the floating gate 106 and the channel region 104 (or the source region 103 or the drain region 102) is increased. And in particular the floating gate 106 from the control gate 108
Increasing the value of the coupling ratio indicating the potential propagating potential to the flash EEPROM is an important factor for reducing the operating voltage of the flash EEPROM device. Here, the coupling ratio is expressed as a ratio (= Cc / (Cc + Cf)) of the electrostatic capacitance Cc between the control gate 108 and the floating gate 106 to the total electrostatic capacitance (Cc + Cf).

[0013]

However, in the EEPROM device using the conventional stack type memory cell and split gate type memory cell, in order to increase the coupling ratio, the floating gate 106 and the control gate 108 face each other. Whether to increase the area and reduce the facing area between the floating gate 106 and the channel region 104, or to change the value of the film thickness ratio between the first dielectric film 105 and the second dielectric film 107. Is required.

In the former case, for example, if the gate width W _fg of the floating gate 106 is increased in order to increase the area where the floating gate 106 and the control gate 108 _face each other, the element area is increased and the integration of the element is increased. Becomes unsuitable. In addition, the floating gate 106
In order to reduce the facing area between the channel region 104 and the channel region 104, for example, reducing the gate length L _fg of the floating gate is effective only in the split gate memory cell shown in FIGS. 15A and 15B. However, it is difficult from the viewpoint of fine processing. Further, reducing the channel width of the channel region 14 reduces the cell current, which causes a reduction in the read speed for the memory cell.

On the other hand, in the latter case, the second dielectric film 10
It is difficult to reduce the film thickness of No. 7 from the viewpoint of reliability.

The present invention solves the above-mentioned conventional problems, suppresses the increase of the chip area, and does not sacrifice the operating characteristics of the device such as the decrease of the cell current. The purpose is to make it possible to realize a low voltage by increasing the voltage.

[0017]

In order to achieve the above-mentioned object, according to the present invention, an auxiliary gate intersecting with a control gate is newly formed on an element isolation region, and a floating side surface or a lower side of the formed auxiliary gate is formed. A gate is provided.

Specifically, the first semiconductor memory device according to the present invention includes a plurality of element isolation regions formed on a semiconductor substrate and separating the semiconductor substrate into a plurality of element formation regions. A plurality of control gates are formed so as to intersect with the element formation region through the first dielectric film and to intersect with the element isolation region, and to extend over the element isolation region and intersect with each control gate. A plurality of formed auxiliary gates and a second dielectric film are formed on each element formation region and on one side surface of each control gate and on a side surface of the auxiliary gate connected to the one side surface. And a plurality of floating gates.

According to the first semiconductor memory device, the auxiliary gate is formed so as to extend over the element isolation region and intersect with each control gate, and the floating gate has one side surface of the control gate and the auxiliary gate. Since it is formed on the side surface of the auxiliary gate connected to one side surface, for example, when a control voltage equivalent to that of the control gate is applied to the auxiliary gate during the erase operation, the facing area between the floating gate and the auxiliary gate increases. The value of the coupling ratio in the control gate is increased by the amount. As a result, by providing the auxiliary gate in an empty space on the element isolation region, it is possible to suppress an increase in chip area and reduce an operating voltage of the element, for example, an erase voltage.

In the first semiconductor memory device, each auxiliary gate is preferably provided independently between the elements adjacent to each other in the direction in which the control gate extends.

In the first semiconductor memory device, each auxiliary gate is provided so as to be shared by the elements adjacent to each other in the direction in which the control gate extends, and each floating gate includes an element including the floating gate. It is preferably not provided on the side surface of the auxiliary gate in the other element formation region adjacent to the formation region.

In this case, the element forming region shares the diffusion region in the direction in which the auxiliary gate extends, and one floating gate and another floating gate sharing the diffusion region face each other with the adjacent auxiliary gates facing each other. It is preferable that they are alternately formed on only one of the side surfaces.

A second semiconductor memory device according to the present invention comprises an element isolation region formed on a semiconductor substrate and separating the semiconductor substrate into a plurality of element formation regions, and a plurality of element formation regions on the semiconductor substrate. A plurality of island-shaped floating gates formed so as to intersect with each other through the first dielectric film, and a second dielectric film formed over each floating gate and above the element isolation region A plurality of control gates formed so as to intersect with the control gate, and a plurality of auxiliary gates formed so as to extend above the element isolation region and intersect the control gate. The lower portion has a bent portion that bends in the direction in which the auxiliary gate extends.

According to the second semiconductor memory device, a plurality of auxiliary gates are formed so as to extend above the element isolation region and intersect the control gate, and the floating gate is provided in the lower portion of the auxiliary gate. Since it has a bent portion that bends in the direction in which the auxiliary gate extends,
For example, when a control voltage equivalent to that of the control gate is applied to the auxiliary gate during the erase operation, the value of the coupling ratio in the control gate increases by the amount that the facing area between the floating gate and the auxiliary gate increases. As described above, by providing the auxiliary gate in the empty space on the element isolation region, it is possible to suppress the increase in the chip area and reduce the operating voltage of the element, for example, the erase voltage.

In the second semiconductor memory device, each floating gate has a planar crank shape, and the end surface outside the corner of the bent portion is formed so that its surface direction intersects the direction in which the control gate extends. It is preferable.

In the second semiconductor memory device, each auxiliary gate is preferably provided independently between the elements adjacent to each other in the direction in which the control gate extends.

In the second semiconductor memory device, each auxiliary gate is provided so as to be shared between the elements adjacent to each other in the direction in which the control gate extends, and each floating gate includes the element including the respective floating gate. It is preferably not provided below the auxiliary gate in another element formation region adjacent to the formation region.

In this case, the element forming region shares the diffusion region in the direction in which the auxiliary gate extends, and one floating gate and the other floating gate sharing the diffusion region have their bent portions adjacent to each other. It is preferable that the auxiliary gates are alternately formed on only one side.

A method for manufacturing a semiconductor device according to the present invention comprises a step of forming an element isolation region on a semiconductor substrate and separating the semiconductor substrate into a plurality of element formation regions, and a plurality of element formation on the semiconductor substrate. Forming a plurality of control gates so as to intersect with the region through the first dielectric film and intersecting with the element isolation region, and forming a plurality of control gates extending above the element isolation region and intersecting each control gate. And a side surface of each control gate by depositing a conductor film on the semiconductor substrate so as to cover the auxiliary gate and the control gate, and etching back the deposited conductor film. A step of forming a sidewall film made of a conductor film on the side surface of the auxiliary gate connected with the second dielectric film, and a step of forming each sidewall film. 2 an area on the side of the auxiliary gate by partially removing, from each side wall film
Forming two floating gates.

According to the method of manufacturing a semiconductor memory device of the present invention, a plurality of auxiliary gates are formed so as to extend over the element isolation region and intersect with the respective control gates, and the conductive film deposited on the semiconductor substrate is formed. Etching back is performed to form a sidewall film made of a conductor film on the side surface of each control gate and the side surface of the auxiliary gate connected to the side surface via the second dielectric film. After that, by partially removing the region on the side surface of the auxiliary gate in each sidewall film, a floating gate is formed for each element from each sidewall film, so that the first semiconductor memory device of the present invention can be reliably implemented. Obtainable.

[0031]

(First Embodiment) First Embodiment of the Present Invention
Embodiments will be described with reference to the drawings.

1 (a) and 1 (b) show the first embodiment of the present invention.
1A shows a plan configuration of four cells, and FIG. 1B shows a cross section taken along line Ib-Ib of FIG. 1A. The partial structure including is shown.

As shown in FIG. 1 (a) or FIG. 1 (b),
For example, a semiconductor substrate 10 made of p-type silicon is formed with a plurality of element formation regions that are insulated and separated by an element isolation region 13 made of LOCOS isolation or shallow trench isolation (STI). Here, the element formation region is n
The drain region 11 of the n-type and the source region 12 of the n-type.

A drain region 1 is formed on the semiconductor substrate 10.
1 and the source region 12 are intersected with each other through the first dielectric film 14 serving as a gate insulating film, and the element isolation region 13 is formed.
A plurality of control gates 15 made of polysilicon intersecting with each other are formed in parallel with each other.

Further, a plurality of auxiliary gates 16 made of polysilicon are formed on the semiconductor substrate 10 so as to extend on the element isolation regions 13 and to intersect and straddle each control gate 15. Has been done.

The second dielectric film 1 is formed on each drain region 11 and on the side surface of each control gate 15 on the drain side and the side surface of the auxiliary gate 16 connected to the side surface.
A plurality of floating gates 18 are formed via 7.

Here, the second dielectric film serves as a capacitance insulating film on the side surface of the control gate 15 and the side surface of the auxiliary gate 16 and a tunnel insulating film on the drain region 11. The second dielectric film 17 is made of silicon oxide, silicon nitride, or a laminated film of these, and is made of a material having a breakdown voltage such that charges injected into the floating gate 18 are not extracted to the control gate 15. That is, the second dielectric film 17 may be optimized in consideration of its film thickness, material, process, etc. so that it has a breakdown voltage such that the charges injected into the floating gate 18 are not extracted to the control gate 15. .

The coupling ratios of the semiconductor memory device according to the first embodiment and the semiconductor memory device having the split gate type memory cell according to the conventional example will be compared below.

FIGS. 2A and 2B are schematic semiconductor memory devices for showing the dimensions of the constituent members necessary for calculating the value of the coupling ratio, and FIG. 2 is a plan view showing the configuration of the semiconductor memory device according to the first embodiment.
FIG. 15B shows a plan configuration of the conventional split gate semiconductor memory device shown in FIG. Figure 2 (a)
2B, and FIG. 1A and FIG. 15B.
The same reference numerals are given to the same constituent members as those shown in FIG.

First, in the semiconductor memory device according to the first embodiment shown in FIG. 2A, the control gate 15
On the side surface of the auxiliary gate 16 in the floating gate 18 is 0.2 μm, the width W of the drain region 11 and the source region 12 is 0.44 μm, and the gate length L _fg of the floating gate 18 is 0.1 μm. The width P _{eg of each is set} to 0.25 μm.

Further, if the film thickness and material of the first dielectric film 14 and the second dielectric film 17 shown in FIG. 1A are the same, the coupling ratio C _R1 is expressed by the following equation (1). Can be approximated by

C _R1 = Cc / (Cc + Cf) = h (W _fg + 2P _eg ) / {h (W _fg + 2P _eg ) + L _fg · W} (1) On the other hand, the conventional semiconductor memory shown in FIG. In the device, the height h of the control gate 106 is 0.2 μm, the width W of the drain region 102 and the source region 103 is 0.44 μm, and the gate length L _fg of the floating gate 106 is 0.1 μm. _fg is 0.9
2 μm.

The coupling ratio C _R0 of the conventional semiconductor memory device is the same as that of the first embodiment when the first dielectric film 105 and the second dielectric film 107 shown in FIG. When applied to a memory cell having the same area as the memory cell of, the coupling ratio _CR0 of the conventional semiconductor memory device can be approximated by the following equation (2).

C _R0 = Cc / (Cc + Cf) = _{hW fg} / ( _{hW fg} + L _fgW ) (2) Here, the above dimension values are _added to the equations (1) and (2). Substituting each, the coupling ratio C _R1 of the present embodiment
Is about 0.87, and the coupling ratio C _R0 of the conventional example is about 0.81.

As shown in the equation (1), in the semiconductor memory device according to the first embodiment, the width of the floating gate 18 is W _fg + 2P _eg = 1.42 μm, so the coupling ratio C in this case is The value of _R1 is about 1.1 times the value of the coupling ratio C _R0 of the conventional semiconductor memory device.

In the semiconductor memory device according to the first embodiment, a negative control potential is applied to the control gate 15 and the auxiliary gate 16 and a positive control potential is applied to the drain region 11 at the time of erasing. Thus, the electrons in the floating gate 18 are extracted.
On the other hand, the conventional semiconductor memory device has a configuration in which, during erasing, the control gate 108 is set to a negative potential and the drain region 102 is set to a positive potential to extract electrons in the floating gate 106.

As described above, according to the first embodiment, since the auxiliary gate 16 intersecting the control gate 15 is provided on the element isolation region 13, the control gate 15 and the auxiliary gate 16 have a predetermined potential. It can be transmitted to the floating gate 18 so that the propagation loss is smaller. As a result, the charge injection operation or the charge discharge operation to the floating gate 18 can be performed at a low voltage, so that the nonvolatile semiconductor memory device can be reliably operated even at a low voltage. Also,
By reducing the operating voltage, the area of the element isolation region 13 can be reduced and the circuit scale of the charge pump circuit can be reduced.

Further, as long as random access is possible, the EEP is not limited to flash memory devices.
It is also possible to operate it as a ROM device.

Hereinafter, a method of manufacturing the semiconductor memory device configured as described above will be described with reference to the drawings.

3A to 3C and 4A.
4B shows a partial cross-sectional structure in the order of steps of the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

First, as shown in FIG. 3A, an element isolation region 13 made of STI or the like is formed on the semiconductor substrate 10 made of p-type silicon, and the semiconductor substrate 10 is formed into a plurality of element formation regions. To separate. After that, the first dielectric film 1 made of silicon oxide is formed on the element formation region by the thermal oxidation method.
4 is formed, and then the semiconductor substrate 1 is formed by the CVD method or the like.
A control gate forming film 15A made of polysilicon is deposited on the entire surface of the 0.

Next, as shown in FIG. 3B, the control gate forming film 15A is patterned by using the lithography method and the etching method, so that the control gate forming film 15A is formed on the element forming region as a first area. A control gate 15 which intersects with the dielectric film 14 and also intersects with the element isolation region 13 is formed. continue,
An auxiliary gate formation film made of polysilicon is deposited on the entire surface including the control gate 15 on the semiconductor substrate 10 by the CVD method or the like, and the deposited auxiliary gate formation film is patterned to separate the element from the auxiliary gate formation film. A plurality of auxiliary gates 16 are formed so as to extend over the region and straddle the control gate 15.

Next, as shown in FIG. 3C, the control gate 15 and the auxiliary gate 16 are formed by a thermal oxidation method or the like.
The second dielectric film 17 is formed on each side surface of the. At this time,
The second dielectric film 17 is set to have a withstand voltage such that the charges injected into the floating gate 18 are not extracted to the control gate 15.

Next, as shown in FIG. 4A, the control gate 15 is formed on the semiconductor substrate 10 by the CVD method or the like.
Then, a polysilicon film is deposited over the entire surface including the auxiliary gate 16. Subsequently, the deposited polysilicon film is etched back to form the polysilicon film, and the control gate 15 and the auxiliary gate 1 are formed.
A floating gate forming film 18A having a sidewall shape is formed on each side surface of 6 in a self-aligned manner via the second dielectric film 17. Since the floating gate forming film 18A has a sidewall shape, the gate length L _fg as a floating gate can be reduced, so that the value of the coupling ratio C _R1 can be increased. After that, the semiconductor substrate 1 is formed using the control gate 15 and the floating gate forming film 18A as a mask.
By implanting n-type impurity ions into 0,
The drain region 11 and the source region are formed.

Next, as shown in FIG. 4B, a region on the side surface of the auxiliary gate 16 in the floating gate forming film 18A, which is a region on the side surface of the auxiliary gate 16 in the floating gate forming film 18A, is exposed by using a lithography method. A mask pattern having an opening pattern 2 to be formed is formed. Subsequently, the floating gate forming film 18A is formed using the formed mask pattern.
The exposed portion of the floating gate 1 is removed from the floating gate forming film 18A by etching.
8 is formed for each cell.

The ion implantation process for forming the drain region and the source region may be performed after the floating gate 18 is formed.

(First Modification of First Embodiment) A first modification of the first embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows a planar configuration of four cells of the semiconductor memory device according to the first modification of the first embodiment. In FIG. 5, the same components as those shown in FIG. 1A are designated by the same reference numerals and the description thereof will be omitted.

The first modification is characterized in that the auxiliary gate 16 is provided independently between adjacent cells in the direction in which the control gate 15 extends. That is,
As shown in FIG. 5, the first cell region 1A is provided with two first auxiliary gates 16A sandwiching the drain region 11 and the source region 12, and the control gate 15 of the first auxiliary gate 16A extends. Two second auxiliary gates 16B are provided in parallel with the first auxiliary gate 16A in the second cell region 1B adjacent in the direction.

With this configuration, as an example, the potential of the first auxiliary gate 16A is set to a negative potential and the potential of the drain region 11 is set to a positive potential, and the first auxiliary gate 16A is accumulated in the floating gate 18 facing the first auxiliary gate 16A. The electrons can be selectively extracted into the drain region 11. As a result, unlike the first embodiment, selective erasing for each bit line is possible, so that it can be operated as an EEPROM device.

(Second Modification of First Embodiment) A second modification of the first embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a planar configuration of four cells of the semiconductor memory device according to the second modification of the first embodiment. In FIG. 6, the same components as those shown in FIG. 1A are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 6, as in the first embodiment, each auxiliary gate 16 is shared by adjacent cells in the direction in which the control gate 15 extends, and each floating gate is provided. 18B is not provided on the side surface of the auxiliary gate 16 in the other drain region 11 and source region 12 adjacent to the drain region 11 and source region 12 including the floating gates 18B.

As a result, the size of the control gate 15 in the extending direction can be reduced, so that the cell area can be reduced. However, compared to the case of the first embodiment,
Although the value of the coupling ratio decreases, it is possible to compensate for the decrease of the coupling ratio value by enlarging the size of the upper side surface of the auxiliary gate 16 in each floating gate 18B.

(Third Modification of First Embodiment) A third modification of the first embodiment of the present invention will be described below with reference to the drawings. FIG. 7 shows a planar configuration of four cells of the semiconductor memory device according to the third modification of the first embodiment. In FIG. 7, the same components as those shown in FIG. 1A are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 7, in the third modification, of the floating gates 18B and 18C facing each other,
One end of the first floating gate 18B is provided only on the side surface of the first auxiliary gate 16C, and one end of the second floating gate 18C is a second auxiliary gate adjacent to the first auxiliary gate 16C. It is provided only on the side surface of 16D.

That is, the first floating gate 18B and the second floating gate 18C sharing the drain region 11 in the direction intersecting with the direction in which the control gate 15 extends have the side surfaces of each control gate 15 and the first floating gate 18C adjacent to each other. And the second auxiliary gate 16
It is formed alternately only on one of the opposite side surfaces of C and 16D.

In the semiconductor memory device according to the first embodiment and the first and second modifications described above, the cells sharing the drain region 11 are erased by one of the cells by the potential application method. Light erase (disturb) even if the other cell is erased or not erased
There is a risk of receiving.

However, according to the third modification, the first
Since the second floating gates 18B and 18C are alternately provided on the side surfaces of the first and second auxiliary gates 16C and 16D which are different from each other adjacent to each other, for example, during the erase operation,
It is possible to prevent erasing or disturb of a cell that is not the erasing target and that is adjacent to the erasing target cell.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 8A and FIG. 8B show the second embodiment of the present invention.
8A is a stack gate type semiconductor memory device according to the embodiment of FIG.
8B shows a partial configuration including a cross section taken along line VIIIb-VIIIb of FIG. 8A.

As shown in FIG. 8A or FIG. 8B,
For example, in a semiconductor substrate 20 made of p-type silicon, a plurality of drain regions 21 and source regions 22 are LOCO.
It is formed so as to be insulated and separated by the element isolation region 23 made of S isolation or STI.

The drain region 2 is formed on the semiconductor substrate 20.
A plurality of island-shaped floating gates 25 made of polysilicon are formed so as to intersect between 1 and the source region 22 via a first dielectric film 24 serving as a gate insulating film.

On the semiconductor substrate 20, the floating gates 25 are formed on the floating gates 25 via the second dielectric film 26 serving as a capacitance insulating film, and the element isolation regions 23 are provided on the element isolation regions 23. A plurality of control gates 27 made of polysilicon are formed so as to intersect with each other.

Further, on the semiconductor substrate 20, the control gates 2 are extended over the element isolation regions 23.
A plurality of auxiliary gates 28 are formed so as to straddle 7.

As a feature of the second embodiment, each floating gate 25 has a bent portion 25a at the lower side of the auxiliary gate 28, which is bent in the direction in which the auxiliary gate 28 extends.

The coupling ratios of the semiconductor memory device according to the second embodiment and the semiconductor memory device having the stack gate type memory cell according to the conventional example will be compared below.

9 (a) and 9 (b) are schematic semiconductor memory devices for showing the dimensions of the constituent members necessary for calculating the value of the coupling ratio, and FIG. 9 is a plan view showing the configuration of the semiconductor memory device according to the second embodiment.
14B shows a plan configuration of the conventional stack gate type semiconductor memory device shown in FIG. 14B. 9A and 9B, the same components as those shown in FIGS. 8A and 14B are designated by the same reference numerals.

First, in the semiconductor memory device according to the second embodiment shown in FIG. 9A, the width W of the drain region 21 and the source region 22 is 0.44 μm, and the floating gate 25 and the control gate 27 face each other. The overlapping width W _fg is 0.84 μm, the gate length L of the floating gate 27 is 0.5 μm, and the width W _pfg of the bent portion 25a of the floating gate 25 is 0.25.
The length P _eg of the protruding portion of the bent portion 25a in the extending direction of the auxiliary gate 28 is 0.25 μm.

Further, when the film thickness and material of the first dielectric film 24 and the second dielectric film 26 shown in FIG. 8A are the same, the coupling ratio C _R1 is expressed by the following equation (3). Can be approximated by

C _R1 = Cc / (Cc + Cf) = (L · W _fg + 2Wp _fg · P _eg ) / (L · W _fg + 2W _pfg · P _eg + L · W) (3) On the other hand, in FIG. In the illustrated conventional semiconductor memory device, the width W of the drain region 102 and the source region 103 is 0.44 μm, the gate length L of the floating gate 106 is 0.5 μm, and the floating gate 106 is
The overlap width W _fg at which the control gate 108 and the control gate 108 face each other is 0.84 μm.

The coupling ratio C _R0 of the conventional semiconductor memory device is the same as that of the first embodiment _except that the first dielectric film 105 and the second dielectric film 107 shown in FIG. When applied to a memory cell having the same area as the memory cell of, the coupling ratio C _R0 of the conventional semiconductor memory device can be approximated by the following equation (4).

[0081]   C_R0= Cc / (Cc + Cf)       = L · Wfg / (L · Wfg + L · W) (4) Here, in Equation (3) and Equation (4), the above dimension values are
Substituting each, the coupling ratio C of the present embodiment_R1
The value of is about 0.71, which is the conventional coupling ratio.
C_R0Is about 0.66. . Therefore, the second embodiment
Ratio C in a semiconductor memory device according to
_R1The value of is the coupling ratio of the conventional semiconductor memory device.
C_R0The value is about 1.1 times.

As described above, according to the second embodiment, the auxiliary gate 28 that intersects the control gate 27 and covers both ends of the floating gate 25 is provided, and the auxiliary gate 28 extends to both ends of the floating gate 25. Since the bent portion 25a that bends in the direction is provided,
The control gate 27 and the auxiliary gate 28 can transmit a predetermined potential to the floating gate 25 so that the loss during propagation can be reduced. As a result, the charge injection operation or the charge discharge operation to the floating gate 25 can be performed at a low voltage, so that the nonvolatile semiconductor memory device can be reliably operated even at a low voltage. Further, by lowering the operating voltage, the element isolation region can be reduced and the circuit scale of the charge pump circuit can be reduced.

In the stack gate type semiconductor memory device according to the present embodiment, the bent portions 25a are formed at both ends of the floating gate 25 in the conventional semiconductor memory device manufacturing process.
It can be realized by simply patterning so as to have the above structure and further adding a step of forming the auxiliary gate 28.

(First Modification of Second Embodiment) A first modification of the second embodiment of the present invention will be described below with reference to the drawings. FIG. 10 shows a planar configuration of four cells of the semiconductor memory device according to the first modification of the second embodiment. In FIG. 10, the same components as those shown in FIG. 8A are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 10, in the first modification, each floating gate 25A is patterned into a planar crank shape, and the end face outside the corner of the bent portion 25a is oriented in the direction in which the control gate 27 extends. It is characterized in that it is formed so as to intersect with.

As a result, as compared with the case of the second embodiment, the size in the extending direction of the control gate 27 and the extending direction of the auxiliary gate 28 can be reduced, so that the cell area can be reduced.

The pattern shape of the mask pattern of the floating gate 25A need only be changed, and the mask structure and manufacturing process are the same as those in the second embodiment.

(Second Modification of Second Embodiment) A second modification of the second embodiment of the present invention will be described below with reference to the drawings. FIG. 11 shows a planar configuration of four cells of the semiconductor memory device according to the second modification of the second embodiment. In FIG. 11, the same components as those shown in FIG. 8A are designated by the same reference numerals and the description thereof will be omitted.

The second modification is characterized in that the auxiliary gate 28 is provided independently between cells adjacent to each other in the direction in which the control gate 27 extends. That is,
As shown in FIG. 11, two first auxiliary gates 28A sandwiching the drain region 21 and the source region 22 are provided in the first cell region 1A, and the control gate 27 of the first auxiliary gate 28A extends in the extending direction. Two second auxiliary gates 28B are provided in parallel with the first auxiliary gate 28A in the second cell region 1B adjacent to.

With this configuration, as an example, the potential of the first auxiliary gate 28A is set to a negative potential and the potential of the drain region 21 is set to a positive potential, and the first auxiliary gate 28A is accumulated in the floating gate 25 in contact with the first auxiliary gate 28A. The electrons can be selectively extracted into the drain region 21. As a result, unlike the second embodiment, selective erasing for each bit line is possible, so that it can be operated as an EEPROM device.

(Third Modification of Second Embodiment) A third modification of the second embodiment of the present invention will be described below with reference to the drawings. FIG. 12 shows a planar configuration of four cells of the semiconductor memory device according to the third modification of the second embodiment. In FIG. 12, the same components as those shown in FIG. 8A are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 12, similarly to the second embodiment, each auxiliary gate 28 is shared by adjacent cells in the direction in which the control gate 27 extends, and each floating gate is provided. 25A is not provided on the side surface of the auxiliary gate 28 in the other regions 21 and 22 adjacent to the drain region 21 and the source region 22 including the floating gates 25A.

As a result, the size of the control gate 17 in the extending direction can be reduced, so that the cell area can be reduced. However, compared to the case of the second embodiment,
Although the value of the coupling ratio decreases, the decrease of the coupling ratio can be compensated by increasing the size of the bent portion 25a of each floating gate 25A.

(Fourth Modification of Second Embodiment) A fourth modification of the second embodiment of the present invention will be described below with reference to the drawings. FIG. 13 shows a planar configuration of four cells of the semiconductor memory device according to the fourth modification of the second embodiment. In FIG. 13, the same components as those shown in FIG. 8A are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 13, in the fourth modification, the bent portion 25a of the first floating gate 25A among the floating gates 25A and 25B facing each other.
Is provided only below the first auxiliary gate 28C, and the bent portion 25a of the second floating gate 25B is provided.
Is provided only under the second auxiliary gate 28D adjacent to the first auxiliary gate 28C.

That is, the bent portions 25a of the first floating gate 25A and the second floating gate 25B that share the drain region 21 are formed on the lower side of the adjacent first and second auxiliary gates 28C and 28D. Are alternately formed.

In the semiconductor memory device according to the second embodiment and the first to third modifications described above, cells sharing the drain region 21 may have one cell depending on the potential application method. During the erase operation, the other cell may be erased, or even if not erased, it may be disturbed.

However, according to the fourth modification, the first
Since the second floating gates 25A and 25B are alternately provided below the first and second auxiliary gates 28C and 28D which are different between adjacent ones, the erase target adjacent to the erase target cell is erased, for example, during an erase operation. It is possible to prevent erasing or disturbing a cell that is not.

[0099]

According to the semiconductor memory device of the present invention,
Since the auxiliary gate, which faces a part of the floating gate via the dielectric film, is provided on the element isolation region, the coupling ratio value in the control gate increases as the area facing the floating gate increases. The operating voltage of the device can be reduced while suppressing an increase in area.

[Brief description of drawings]

1A and 1B show a split gate type semiconductor memory device according to a first embodiment of the present invention, FIG.
(A) is a partial plan view, (b) is Ib of (a)
It is a perspective view containing the cross section in the -Ib line.

FIG. 2A is a semiconductor memory device according to the first embodiment of the present invention, and is a schematic plan view showing dimensions of constituent members necessary for calculating a coupling ratio value. . FIG. 6B is a schematic plan view of a conventional split gate semiconductor memory device for comparison.

3A to 3C are configuration cross-sectional views in order of the steps, showing a method for manufacturing the split gate type semiconductor memory device according to the first embodiment of the present invention.

FIG. 4A and FIG. 4B are cross-sectional views of a process sequence showing a method of manufacturing a split gate type semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a partial plan view showing a split gate type semiconductor memory device according to a first modification of the first embodiment of the present invention.

FIG. 6 is a partial plan view showing a split gate type semiconductor memory device according to a second modification of the first embodiment of the present invention.

FIG. 7 is a partial plan view showing a split gate type semiconductor memory device according to a third modification of the first embodiment of the present invention.

8A and 8B show a stack gate type semiconductor memory device according to a second embodiment of the present invention, and FIG.
Is a partial plan view, (b) is VIIIb-VII of (a)
It is a perspective view including the section in the Ib line.

FIG. 9A is a semiconductor memory device according to the second embodiment of the present invention, and is a schematic plan view showing dimensions of constituent members necessary for calculating a value of a coupling ratio. . FIG. 3B is a schematic plan view of a conventional stack gate type semiconductor memory device for comparison.

FIG. 10 is a partial plan view showing a stack gate type semiconductor memory device according to a first modification of the second embodiment of the present invention.

FIG. 11 is a partial plan view showing a stack gate type semiconductor memory device according to a second modification of the second embodiment of the present invention.

FIG. 12 is a partial plan view showing a stack gate type semiconductor memory device according to a third modification of the second embodiment of the present invention.

FIG. 13 is a partial plan view showing a stack gate type semiconductor memory device according to a fourth modification of the second embodiment of the present invention.

14A and 14B show a conventional stack gate type semiconductor memory device, FIG. 14A is a sectional view of the structure of one cell, and FIG. 14B is a plan view showing four cells. is there.

15A and 15B show a conventional split gate type semiconductor memory device, FIG. 15A is a sectional view showing the structure of one cell, and FIG. 15B is a plan view showing four cells. is there.

[Explanation of symbols]

10 Semiconductor substrate 11 drain region 12 Source area 13 element isolation region 14 First dielectric film 15 control gate 15A Control gate forming film 16 Auxiliary gate 17 Second dielectric film 18 floating gate 18A Floating gate formation film 18B floating gate 18C First floating gate 18D 2nd floating gate 20 Semiconductor substrate 21 drain region 22 Source area 23 Element isolation region 24 First dielectric film 25 floating gate 25a bent part 26 Second dielectric film 27 Control gate 28 Auxiliary gate 28A First auxiliary gate 28B Second auxiliary gate 28C First auxiliary gate 28D Second auxiliary gate 1A First cell area 1B Second cell area 2 opening pattern

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuhiro Toki             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Masaru Ogura             New York, United States 12590,             Wappingers Falls, Old               Hopewell Road 140, Halo               LSI Design and Deva             Chair Technology Incorporated             Inside F term (reference) 5F083 EP03 EP14 EP23 EP24 EP40                       EP53 EP56 ER15 ER22 ER30                       GA05 GA09 GA22 JA04 JA19                       NA01 PR09 PR29                 5F101 BA03 BA06 BA12 BA14 BA29                       BA36 BB04 BB05 BC01 BD02                       BD35 BD37 BE05 BE07 BH19

Claims (10)

[Claims] 1. An element isolation region formed on a semiconductor substrate for separating the semiconductor substrate into a plurality of element formation regions, and the plurality of element formation regions and a first element formation region on the semiconductor substrate.
A plurality of control gates formed so as to intersect with each other through the dielectric film and intersecting the element isolation regions, and formed so as to extend above the element isolation regions and intersect each control gate. A plurality of auxiliary gates are formed on the respective element formation regions and on one side surface of each control gate and on a side surface of the auxiliary gate connected to the one side surface with a second dielectric film interposed therebetween. And a plurality of floating gates. 2. The semiconductor memory device according to claim 1, wherein each of the auxiliary gates is provided independently between adjacent elements in a direction in which the control gate extends. 3. The auxiliary gates are provided so as to be shared by elements adjacent to each other in the direction in which the control gate extends, and each floating gate has an element formation region including the floating gate. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is not provided on a side surface of the auxiliary gate in another adjacent element formation region. 4. The element forming region shares a diffusion region in a direction in which the auxiliary gate extends, and one floating gate and another floating gate sharing the diffusion region are adjacent to each other. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed alternately only on one of the facing side surfaces. 5. An element isolation region formed on a semiconductor substrate and separating the semiconductor substrate into a plurality of element formation regions, and the plurality of element formation regions and a first element formation region on the semiconductor substrate.
A plurality of island-shaped floating gates formed so as to intersect each other through the dielectric film, and a second dielectric film formed on each of the floating gates and above the element isolation region. A plurality of control gates formed so as to intersect with the control gate, and a plurality of auxiliary gates formed so as to extend above the element isolation region and intersect the control gate, and each of the floating gates includes: A semiconductor memory device having a bent portion that bends in a direction in which the auxiliary gate extends in a lower portion of the auxiliary gate. 6. Each of the floating gates has a planar crank shape, and an end surface of the bent portion outside the corner portion is formed so that its surface direction intersects with the extending direction of the control gate. The semiconductor storage device according to claim 5, wherein the semiconductor storage device is a storage device. 7. The semiconductor memory device according to claim 5, wherein each of the auxiliary gates is provided independently between elements adjacent to each other in a direction in which the control gate extends. 8. The auxiliary gates are shared by the elements adjacent to each other in the direction in which the control gate extends, and the floating gates are connected to element formation regions including the floating gates. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is not provided below the auxiliary gate in another adjacent element formation region. 9. The element formation region shares a diffusion region in a direction in which the auxiliary gate extends, and one floating gate and another floating gate sharing the diffusion region have bent portions mutually. 9. The semiconductor memory device according to claim 8, wherein only one of adjacent auxiliary gates is alternately formed. 10. A step of forming an element isolation region on a semiconductor substrate to separate the semiconductor substrate into a plurality of element formation regions, and the plurality of element formation regions and a first element formation region on the semiconductor substrate.
Forming a plurality of control gates so as to intersect with the element isolation region while intersecting through the dielectric film, and a plurality of control gates extending above the element isolation region and intersecting the control gates. Forming an auxiliary gate, depositing a conductor film on the semiconductor substrate so as to cover the auxiliary gate and the control gate, and performing etchback on the deposited conductor film, thereby forming a side surface of each control gate and Forming a sidewall film made of the conductor film on a side surface of the auxiliary gate connected to the side surface through a second dielectric film; and a region on each side wall film on the side surface of the auxiliary gate. Is partially removed to form a floating gate for each element from each of the sidewall films. Method of manufacturing a semiconductor memory device characterized by there.