JP2003045897A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of lowering the contact resistance of a gate diffusion layer and a gate electrode and realizing a high- speed operation, and a manufacturing method. SOLUTION: The surface of the gate diffusion layer 24 and a metal layer as the gate electrode 25 in a high electron mobility transistor are made into an alloy. Thus, compared to the case that the surface of the gate diffusion layer 24 and the metal layer as the gate electrode 25 are simply in contact, the contact resistance of the gate diffusion layer 24 and the gate electrode 25 is low and the high-speed operation is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a gate diffusion layer and a gate electrode in contact with the gate diffusion layer, and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 5 shows a high electron mobility transistor as a conventional example of the present invention. In this conventional high electron mobility transistor, a buffer layer 12 such as an undoped GaAs layer is laminated on a semi-insulating substrate 11 such as a GaAs substrate.
A high resistance layer 13 such as a GaAs layer is laminated on the buffer layer 12. N-type AlGaA is formed on the high resistance layer 13.
An electron supply layer 14 such as an s layer is laminated, and a spacer layer 15 such as an undoped AlGaAs layer is laminated on the electron supply layer 14.

Undoped InG is formed on the spacer layer 15.
A channel layer 16 such as an aAs layer is laminated, and a spacer layer 17 such as an undoped AlGaAs layer is laminated on the channel layer 16. An electron supply layer 21 such as an n-type AlGaAs layer is laminated on the spacer layer 17, and a barrier layer 22 such as an undoped AlGaAs layer is laminated on the electron supply layer 21.

N ⁺ type AlGaAs is formed on the barrier layer 22.
The cap layer 23, which is a layer or the like, is stacked, and the p ⁺ -type gate diffusion layer 24 in which Zn is diffused is the barrier layer 22.
Provided on the surface of. The gate diffusion layer 24 has Ti /
The gate electrode 25 such as a Pt / Au layer is in contact,
The source / drain electrodes 26, which are ohmic resistance layers such as AuGe / Ni layers, are in contact with the cap layer 23.

[0005]

However, in the above-mentioned conventional high electron mobility transistor, the gate diffusion layer 2 is used.
4 was high in contact resistance with the gate electrode 25, and it was difficult to realize high-speed operation. Therefore, it is an object of the invention of the present application to provide a semiconductor device which has a low contact resistance between a gate diffusion layer and a gate electrode and can realize high-speed operation, and a manufacturing method thereof.

[0006]

In the semiconductor device according to the first aspect, since the surface of the gate diffusion layer and the metal layer as the gate electrode are alloyed, the surface of the gate diffusion layer and the metal layer as the gate electrode. The contact resistance between the gate diffusion layer and the gate electrode is lower than in the case where and are simply in contact with each other.

In the semiconductor device according to the second aspect, since the metal layer contains the metal as the impurity of the gate diffusion layer,
When alloying the surface of the gate diffusion layer and the metal layer as the gate electrode, metal as an impurity diffuses from the metal layer into the gate diffusion layer. Therefore, the impurity concentration of the gate diffusion layer is increased, and the contact resistance between the gate diffusion layer and the gate electrode is further low.

In the method of manufacturing a semiconductor device according to the third aspect, a metal layer for forming a gate electrode is deposited on the gate diffusion layer, and the surface of the gate diffusion layer and the metal layer are alloyed by heat treatment. Therefore, the contact resistance between the gate diffusion layer and the gate electrode can be reduced as compared with the case where the metal layer for forming the gate electrode is simply deposited on the gate diffusion layer.

In the method of manufacturing the semiconductor device according to the fourth aspect, since the metal layer containing the metal as the impurity of the gate diffusion layer is deposited, the alloy of the surface of the gate diffusion layer and the metal layer for forming the gate electrode. Upon conversion, metal as an impurity diffuses from the metal layer into the gate diffusion layer. Therefore, the impurity concentration of the gate diffusion layer can be increased, and the contact resistance between the gate diffusion layer and the gate electrode can be further reduced.

[0010]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention applied to a high electron mobility transistor and a method of manufacturing the same will be described below with reference to FIGS. In order to manufacture the high electron mobility transistor of this embodiment,
As shown in (a), an undoped GaAs layer or the like is formed on the semi-insulating substrate 11 such as a GaAs substrate by MOCV.
The buffer layer 12 is formed by epitaxial growth to a thickness of, for example, 200 nm by the D method or the like. Then, the high resistance layer 13 is formed on the buffer layer 12 by epitaxially growing an undoped AlGaAs layer or the like to a thickness of 50 nm by the MOCVD method or the like.

Next, n-type AlGaA is formed on the high resistance layer 13.
The electron supply layer 14 is formed by epitaxially growing the s layer or the like to a thickness of 3 nm by the MOCVD method or the like. Then, undoped Al is formed on the electron supply layer 14.
The spacer layer 1 is formed by epitaxially growing a GaAs layer or the like to a thickness of 2 nm by the MOCVD method or the like.
5 is formed. Then, an undoped InGaAs layer or the like is formed on the spacer layer 15 by the MOCVD method or the like to have a thickness of 15 nm, for example.
The channel layer 16 is formed by epitaxially growing to a thickness of.

Next, undoped A is formed on the channel layer 16.
The spacer layer 17 is formed by epitaxially growing the 1 GaAs layer or the like to a thickness of 2 nm by the MOCVD method or the like. Then, an n-type A is formed on the spacer layer 17.
The electron supply layer 21 is formed by epitaxially growing the 1 GaAs layer or the like to a thickness of 6 nm by the MOCVD method or the like. Then, an undoped AlGaAs layer or the like is formed on the electron supply layer 21 by the MOCVD method or the like, for example, with a thickness of 80 n.
The barrier layer 22 is formed by epitaxially growing to a thickness of m.

Next, n ⁺ type AlGa is formed on the barrier layer 22.
The cap layer 23 is formed by epitaxially growing the As layer or the like to a thickness of 50 nm by MOCVD or the like.
To form. Then, a resist (not shown) is applied on the cap layer 23, the resist is selectively exposed by an exposure device, and the resist is selectively removed by developing with a developing solution to form a channel portion. The cap layer 23 in the area is exposed.

Next, the exposed cap layer 23 is dipped in an etching solution such as citric acid to form an opening 31 in the cap layer 23 as shown in FIG. 2 (b). Then, the resist is removed by the plasma ashing method or the like. Then, as shown in FIG. 2 (c), Si ₃ N
The entire surface, for example, 300nm to _four layers or the like by a plasma CVD method or the like
To form the mask layer 32 by depositing the mask layer 32 to a thickness of. Then, a resist (not shown) is formed on the mask layer 32.
Is applied, the resist is selectively exposed by an exposure device, and the resist is selectively removed by developing with a developing solution, whereby the mask layer 3 in the region where the gate diffusion layer is to be formed is formed.
Expose 2

Next, the exposed mask layer 32 is anisotropically etched by the RIE method or the like using a CF ₄ -based etching gas to open the mask layer 32 as shown in FIG. 3A. 33 is formed. Then, the resist is removed by the plasma ashing method or the like. Then, heat treatment is performed at 600 ° C. in a gas atmosphere containing, for example, diethyl zinc and arsine, and the barrier layer 2 is opened from the opening 33.
2 (b) by diffusing Zn on the surface of FIG.
As shown in FIG. 5, a p ⁺ type gate diffusion layer 24 is formed.

Next, as shown in FIG. 3 (c), A
A metal layer 34 such as a u / Zn / Ti / Pt / Au layer having a thickness of, for example, 10/10/30/50/120 nm is deposited by an electron beam evaporation method, a sputtering method, or the like. Then, a resist (not shown) is applied on the metal layer 34, the resist is selectively exposed by an exposure device, and the resist is selectively removed by developing with a developing solution to form a gate electrode. The metal layer 34 in the area other than the area is exposed.

Next, the exposed metal layer 34 is subjected to an ion milling method or the like using Ar gas to form a gate electrode 25 as shown in FIG. 4 (a). Then, the resist is removed by the plasma ashing method or the like. After that, a resist (not shown) is applied on the entire surface, the resist is selectively exposed by an exposure device, and the resist is selectively removed by developing with a developing solution to form a region where the source / drain electrodes are to be formed. Exposing the mask layer 32 at.

Next, the exposed mask layer 32 is subjected to anisotropic etching by the RIE method or the like using a CF ₄ -based etching gas to open the mask layer 32 as shown in FIG. 4B. 35 is formed. Then, a metal layer such as an AuGe / Ni layer having a thickness of, for example, 160/40 nm is deposited by the resistance heating vapor deposition method or the like while leaving the above resist. Then, the metal layer on the resist is removed by a lift-off method to leave the metal layer only in the opening 35 and to form the source / drain electrode 26 as an ohmic resistance layer, as shown in FIG. 4C. To form.

Next, heat treatment is performed at 480 ° C. in a forming gas, for example, as shown in FIG.
The surface of the cap layer 23 and the source / drain electrode 26 are alloyed to make ohmic contact. By this heat treatment, the surface of the gate diffusion layer 24 and the gate electrode 25 are alloyed and brought into ohmic contact, and Zn is diffused from the gate electrode 25 to the gate diffusion layer 24 to increase the impurity concentration of the gate diffusion layer 24. .

In the conventional high electron mobility transistor shown in FIG. 5, the surface of the gate diffusion layer 24 and the gate electrode 25 are merely in contact with each other. However, in the high electron mobility transistor according to the present embodiment as described above, the surface of the gate diffusion layer 24 and the gate electrode 25 are alloyed, and moreover, Zn is diffused from the gate electrode 25 to the gate diffusion layer 24. The impurity concentration of the gate diffusion layer 24 is increased. Therefore, the contact resistance between the gate diffusion layer 24 and the gate electrode 25 is low, and high-speed operation can be realized.

Although the metal layer 34 is deposited by the electron beam evaporation method or the sputtering method in the above embodiment, the metal layer 34 may be deposited by other methods. In addition, as shown in FIG. 3B, the barrier layer 2 is formed through the opening 33.
Although the p ⁺ -type gate diffusion layer 24 is formed by diffusing Zn on the surface of No. 2, impurities other than Zn may be used to form the gate diffusion layer 24.

Further, from the gate electrode 25 to the gate diffusion layer 2
Since Zn is diffused into 4 to increase the impurity concentration of the gate diffusion layer 24, when impurities other than Zn are used to form the gate diffusion layer 24 as described above, Au / Zn is used as the metal layer 34. Metal layers other than the / Ti / Pt / Au layer can be used. Furthermore, although the invention of the present application is applied to the high electron mobility transistor and the manufacturing method thereof in the above-described embodiments, the invention of the present application can be applied to a semiconductor device other than the high electron mobility transistor and a manufacturing method thereof. it can.

[0023]

In the semiconductor device according to the first aspect, since the contact resistance between the gate diffusion layer and the gate electrode is low, high speed operation can be realized.

In the semiconductor device according to the second aspect, since the contact resistance between the gate diffusion layer and the gate electrode is further low, it is possible to realize a higher speed operation.

In the method of manufacturing the semiconductor device according to the third aspect, the contact resistance between the gate diffusion layer and the gate electrode can be reduced, so that the semiconductor device capable of realizing high-speed operation can be manufactured. .

In the method of manufacturing a semiconductor device according to the fourth aspect, since the contact resistance between the gate diffusion layer and the gate electrode can be further reduced, it is possible to manufacture a semiconductor device capable of realizing higher speed operation. You can

[Brief description of drawings]

FIG. 1 is a side sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing initial steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a side sectional view sequentially showing a middle-stage step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a side sectional view sequentially showing the final step of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 5 is a side sectional view of a semiconductor device according to a conventional example of the present invention.

[Explanation of symbols]

24 ... Gate diffusion layer, 25 ... Gate electrode, 34 ... Metal layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takayuki Toyama             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 4M104 AA05 BB09 DD57 DD78 DD83                       FF13 GG11 HH15                 5F102 FA00 GB01 GC01 GD04 GJ05                       GK05 GL04 GM06 GN06 GQ02                       GR09 GS02 GS04 GT01 GT03                       GV08 HC01 HC05 HC15 HC16                       HC19 HC21

Claims (4)

[Claims] 1. A semiconductor device having a gate diffusion layer and a gate electrode in contact with the gate diffusion layer, wherein the surface of the gate diffusion layer and a metal layer as the gate electrode are alloyed. 2. The semiconductor device according to claim 1, wherein the metal layer contains a metal as an impurity of the gate diffusion layer. 3. A method of manufacturing a semiconductor device having a gate diffusion layer and a gate electrode in contact with the gate diffusion layer, the step of depositing a metal layer for forming the gate electrode on the gate diffusion layer. And a step of alloying the surface of the gate diffusion layer and the metal layer by heat treatment. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the metal layer containing a metal as an impurity of the gate diffusion layer is deposited.