JP2002300121A - Optical network unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To economically and simply conduct adjustment and inspection of an optical module without the need for using an expensive exclusive measure ment instrument such as a multi-channel generator by providing a clock generat ing section generating a test pattern in an optical subscriber line terminating unit (ONU). SOLUTION: A CPU section 15 in an Ether/PDS-LSI 10 instructs a conversion circuit 15 for the operation in the optical module adjustment mode on the basis of an optical module adjustment mode command received from an adjustment inspection PC 24. The conversion circuit 16 generates a test pattern and a clock used for adjustment and inspection of an optical module section (LD/PD) 3 and supplies them to a test mode circuit 11. Thus, a laser diode in the optical module section 3 is driven via an analog IC interface circuit 12 and an analog IC 2 and an optical signal corresponding to the test pattern is transmitted. The test pattern to be generated can be selected on the basis of pattern designation data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical network unit (ONU).
More specifically, the present invention relates to an optical network unit that facilitates inspection and adjustment work in a factory or the like.

[0002]

2. Description of the Related Art FTTH (fiber to the h).
An Ome) system connects an optical fiber to a user's home in a subscriber line section, and as a configuration method for economically realizing the FTTH, a passive double star (PDS: passive double star) is provided.
The configuration is known.

FIG. 8 is a diagram showing an example of an FTTH system having a PDS configuration. The FTTH system having the PDS configuration includes an optical network unit (SLT: sub
scriber line terminal or O
LT: optical line terminal)
And an optical network unit (ONU) that is a user-side facility (subscriber-side facility)
It) interposes an optical star coupler (optical branching circuit), which is an optical passive element, between a plurality of users (for example, 32 users) and one optical subscriber line termination panel (OSU: optica).
l subscriber unit), transmission signals of a plurality of users are multiplexed and transmitted on one optical fiber. In the FTTH system having the PDS configuration, the point-to-multipoint access between the SLT and the ONU allows the transmission capacity of the optical fiber broadband to be shared by a plurality of users. Thus, efficient user multiplexing can be realized.

[0004] By providing a line card (BRI LC) for the ISDN basic interface in the ONU, the UNI of the ISDN basic interface (2B + D) is provided.
(User network interface) can be provided to the user. B is 64 kbi
t / s and D are 16 kbit / s. Also, an analog telephone interface line card (PO
TS LC: plainold telephone
By providing a service line card, it is possible to provide the user with the UNI of the analog telephone. Further, an Ethernet interface (Et) is provided in the ONU.
Her IF) provides a user with a UNI (LAN interface) for Ethernet (registered trademark) such as 10Base-T.

FIG. 9 is a diagram showing a PDS transmission system. P
In the FTTH system having the DS configuration, a time division directional control transmission scheme (TCM: time compression mu) is used.
ltiplexing) is adopted, and a downstream signal from the OSU to each ONU is TDM (time device).
The signal is transmitted in an Ion multiplex, and an upstream signal from each ONU to the OSU is TDMA (time devi).
It is transmitted in a multi-plex access.

FIG. 10 is a diagram showing a frame configuration of the PDS optical subscriber system. Since the fiber length from the optical star coupler to each ONU differs for each user, the transmission delay time differs for each user. Therefore, the OSU instructs the transmission timing of the delay measurement frame for each ONU, and the delay measurement frame transmitted from the ONU in accordance with the instruction is set to O
The transmission delay time for each ONU is measured based on the timing received on the SU side. Then, the OSU specifies a timing at which each ONU starts transmitting an upstream frame based on the measured transmission delay time. As a result, each ONU
Is designed to prevent collision of upstream frame signals transmitted by the TDMA method.

FIG. 11 is a functional block diagram of a conventional ONU. The ONU includes an optical line termination unit, a subscriber demultiplexing unit, a service demultiplexing unit, a communication line card, an Ethernet interface unit (Ether-IF), and a power supply unit. The downstream signal supplied via the optical subscriber line (optical fiber) is 1.3 μm via the optical connection.
The light is supplied to a light receiving element (PD: photodiode), converted into an electric signal by the light receiving element, amplified by a reception amplifier circuit, and supplied to a subscriber demultiplexing function unit. On the other hand, the driver drives a 1.3 μm laser diode (LD) based on the upstream signal output from the subscriber demultiplexing function unit. This LD converts an electric signal into an optical signal,
The optical signal is sent to the subscriber line via an optical connection.

[0008] The subscriber demultiplexing function section includes a descrambling processing section, a frame synchronizing section, an OH demultiplexing section, a confidential cancellation processing.
It includes a CRC calculation unit, a scramble processing unit, an OH generation unit, a secret processing / CRC calculation unit, and a control unit. The downlink signal output from the optical network unit is descrambled by a descramble processing unit, and frame synchronization is achieved by a frame synchronization unit. Then, a signal addressed to the own ONU is extracted by the OH separation unit, and a privacy release process and a CRC calculation unit perform a privacy release process and an error correction process. The signal decoded by the confidentiality release processing / CRC operation unit is supplied to the service demultiplexing function unit.

On the other hand, the uplink signal output from the service demultiplexing function unit is subjected to a privacy processing by a privacy processing / CRC operation unit, and is provided with an error correction code.
After the OH is generated by the generation unit and scrambled by the scramble processing unit, the OH is supplied to the optical network unit.

[0010] The service demultiplexing function unit includes a speed conversion unit,
It has a 4M highway terminal and a shared band highway terminal. The 4M highway terminator is connected to a communication line card via a 4M highway interface, and a UNI such as an analog telephone or ISDN is provided via the communication line card. The shared band highway termination is
It is connected to an Ethernet interface unit (Ether-IF) via a shared band highway interface, and a 10Base-T LA is connected via the Ethernet interface unit.
An N interface is provided. The power supply unit is
It supplies various DC power to the communication line card and the Ethernet interface unit, and controls charging of a backup battery for power failure.

In addition, a service of distributing a video signal using, for example, an optical signal having a wavelength of 1.5 μm by applying a wavelength multiplexing (WDM) technique to the FTTH system having the above-mentioned PDS configuration has been put to practical use.

In the conventional ONU, a subscriber multiplexing / demultiplexing function unit and a service multiplexing / demultiplexing function unit are provided by a dedicated LSI (PDS-L).
SI). And, PDS-P
The DS-LSI, the optical network unit (optical module unit), and their peripheral circuits are mounted. This ON
For U, adjustment inspection of the optical module unit and various inspections are required.

FIG. 12 is a diagram showing a conventional adjustment and inspection system for an ONU optical module in a factory. FIG.
Shows only the circuit blocks related to the adjustment inspection. The PDS-optical unit substrate 100 is a PDS-LSI 110
, An analog IC 120 constituting a driver or the like, an optical module unit 130 including a laser diode LD and a photodiode PD, an EEPROM 140, and an ONU.
ID setting switch section (ID
-SW) 150, a first connector 160, and a second connector 170.

The PDS-LSI 110 includes a test mode circuit 111 and an analog IC interface circuit 112.
, An EEPROM interface circuit 113, and an internal information storage unit 114.

Reference numeral 210 denotes an I / O tester, and reference numeral 220 denotes a personal computer (PC) for an I / O test. The I / O tester 210 and the I / O test PC 220 are connected by a serial data interface such as RS-232C. The I / O tester 210
An I / O pin test command signal is generated and output based on an I / O pin test command supplied from the I / O test PC 220. This I / O pin test command signal is supplied to the test mode circuit 111 via the second connector 170. The test mode circuit 111 assigns the I / O pin designated on the basis of the I / O pin test command signal to the I / O pin.
The designated logic level is output based on the pin test command signal. The output of the I / O pin is connected to the first connector 16
0 is supplied to the I / O tester 210. The I / O tester 210 checks whether the logic level of the I / O pin specified by the I / O pin test command matches a preset logic level, and compares the check result with the I / O pin.
Supply to the / O test PC 220. Thereby, PD
It can be checked whether or not each terminal of the S-LSI is correctly soldered to the wiring pattern of the PDS-optical part board 100 or not.

Reference numeral 270 is a relay box, and reference numeral 280 is a personal computer (PC) for reading internal information. Between the relay box 270 and the internal information reading personal computer PC280, for example, RS-232C
Etc. are connected by a serial data interface.
PC 280 for reading internal information
Outputs an internal information read command signal. This internal information read command signal is supplied to the test mode circuit 111 via the relay box 270 and the second connector 170.
The test mode circuit 111 reads the internal information stored in the internal information storage unit 114 based on the internal information read command signal, and reads the read internal information via the second connector 170 and the relay BOX 270 for reading the internal information. It is supplied to the computer PC280. Thus, various types of information stored in the internal information storage unit 114 can be read and the internal information can be checked.

Reference numeral 230 denotes a relay box, and reference numeral 240 denotes E.
It is a personal computer (PC) for EPROM writing control. Between the relay box 230 and the EEPROM write control PC 240, for example, RS-232C
Etc. are connected by a serial data interface.
The relay BOX 230 is a PC for controlling EEPROM writing.
Based on the write command, write address designation data, write data, and the like supplied from 240, these commands, data, and the like are converted into parallel data and output. These parallel data are supplied to the test mode circuit 111 via the second connector 170. The test mode circuit 111 transmits the command, data, and the like supplied through the relay BOX 230 to the EEPROM interface circuit 113.
Supplied to the EEPROM interface circuit 113.
, The designated data is written to the designated address of the EEPROM 140. Thus, for example, data for setting the bias current of the laser diode (LD) and data for setting the drive current when the laser diode emits light can be written in the EEPROM 140.

Reference numeral 250 denotes an optical unit adjustment jig, and reference numeral 260 denotes a jig.
Is a multi-channel generator. When adjusting the optical module, the multi-channel generator 26
The high-speed clock signal and data generated by 0 are supplied to the test mode circuit 111 via the optical unit adjustment jig 250 and the second connector 170. The test mode circuit 111 supplies a clock signal and data to the analog IC 120 via the analog IC interface circuit 112. Thus, the laser diode (LD) is driven in synchronization with the high-speed clock signal, and an optical signal modulated by data is output. Optical module 130
The optical signal output from is detected by an optical power meter (not shown). The output level of the optical signal is adjusted to a specified value by changing data for setting the bias current of the laser diode (LD) to be written into the EEPROM 140 and data for setting the drive current when the laser diode emits light. I do.

[0019]

As described above, the conventional optical network unit (ONU) is composed of the PDS-optical unit board 1.
It is necessary to connect a dedicated jig for each inspection / adjustment item of 00, and the inspection takes time. Further, the adjustment of the optical module requires an expensive dedicated measuring instrument such as the multi-channel generator 260, and a plurality of expensive dedicated measuring instruments are prepared at the time of mass production, so that the adjustment inspection system becomes expensive.

The present invention has been made to solve such a problem. By providing a clock generator for generating a test pattern in an ONU, an expensive dedicated measuring instrument such as a multi-channel generator can be used. It is an object of the present invention to provide an optical network unit (ONU) capable of economically and easily performing adjustment inspection of an optical module.

[0021]

In order to solve the above problems, an optical network unit (ONU) according to the present invention is an optical network unit installed on a user side of an optical subscriber line. A test pattern for decoding a test command signal instructed via an optical subscriber line and performing an adjustment test of an optical module unit, a test control unit for controlling clock generation and stop, and a control signal from the test control unit And a test pattern generating section for generating the test pattern and the clock based on the test pattern.

The optical line terminal according to the present invention (ON
In U), since the ONU includes the test pattern generation unit, the adjustment test of the optical module can be performed without using a dedicated measuring device such as a multi-channel generator. Further, since the optical network unit (ONU) according to the present invention includes the test control unit, the generation / stop of the test pattern and the clock can be controlled based on a test command supplied from the outside.

Further, the test pattern generator stores a plurality of test patterns registered in advance.

The test pattern generator of the present invention stores a plurality of types of test patterns, and selects and specifies the type of the test pattern based on a test command, thereby selecting an arbitrary pattern from the plurality of patterns. Can be generated.

Further, the test pattern generating section according to the present invention is characterized in that the test pattern generating section includes a test pattern storing section for storing a test pattern supplied from the outside.

The test pattern generation section of the present invention includes a test pattern storage section for storing a test pattern supplied from the outside, so that an arbitrary test pattern is supplied from the outside and registered in the test pattern storage section. A registered test pattern can be generated. Thereby, an arbitrary test pattern can be generated.

[0027]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a system for adjusting and inspecting an optical network unit (ONU) according to the present invention. FIG. 1 shows only circuit blocks related to the adjustment inspection.

In FIG. 1, reference numeral 1 denotes an integrated substrate, which is an Ether / PDS-LSI
10, an analog IC 2 constituting a driver, an optical module unit 3 comprising an LD and a PD, an EEPROM 4, an ON
ID setting switch section (I
D-SW) 5, first connector 6 and second connector 7
Is provided.

The Ether / PDS-LSI 10 corresponds to FIG.
The subscriber multiplexing / demultiplexing function unit, the service multiplexing / demultiplexing function unit, and the Ethernet interface (Ether-IF) unit shown in FIG. In the conventional optical network unit (ONU), a 30-pin connector is used to connect the service demultiplexing function unit and the Ethernet interface (Ether-IF) unit. In the present embodiment, the Ethernet interface is used. By employing the Ether / PDS-LSI 10 including the (Ether-IF) section, the above connector is not required, and the optical network unit (ONU) can be reduced in size and economical.

The Ether / PDS-LSI 10 includes a test mode circuit 11, an analog IC interface circuit 1,
2, an EEPROM interface circuit 13, an internal information storage unit 14, a CPU unit 15 forming a test control unit, and a conversion circuit unit 16 forming a test pattern generation unit.
The test mode circuit 11, the analog IC interface circuit 12, the EEPROM interface circuit 13, and the internal information storage unit 14 are the same as the conventional one shown in FIG.

Reference numeral 21 denotes an I / O tester, and reference numeral 22 denotes an I / O tester.
It is a personal computer (PC) for O test.
Between the I / O tester 21 and the I / O test PC 22
For example, they are connected by a serial data interface such as RS-232C. Reference numeral 23 denotes a level converter, and reference numeral 24 denotes a personal computer (PC) for adjustment inspection control (for setting). The level converter 23 and the adjustment inspection control PC 24 are connected by an RS-232C serial data interface.

The level converter 23 converts the logical level of the RS-232C serial data supplied from the adjustment / inspection control PC 24 into the logical level of the Ether / PDS-LSI 10, and converts the converted serial data to the second level. It is supplied to the CPU unit 15 via the connector 7. The level converter 23 converts the logical level of the serial data supplied from the CPU unit 15 into RS-232.
C to the logical level of C, and the converted RS-232C
Is supplied to the adjustment inspection control PC 24. As described above, the level converter 23 determines the logical level of the serial communication port of the adjustment inspection control PC 24 and the CP.
It performs mutual conversion with the logic level of the serial communication port of the U section 15.

The adjustment inspection control PC 24 and the I / O test PC 22 are connected via a LAN (not shown). When executing the I / O pin test, the adjustment inspection control PC 24 transmits the information on the execution of the I / O pin test and the test items via the LAN (not shown) to the I / O test PC.
Notify C22. At the time of the I / O pin test, the logic level of each I / O pin detected by the I / O tester 21 is supplied to the I / O test PC 22. Where I /
Since the O test PC 22 obtains information on the execution of the I / O pin test and the test items via the LAN as described above, each I / O supplied from the I / O tester 21 is used.
Pass / fail of the I / O test can be determined based on the logic level of the pin.

The CPU unit 15 includes a serial data communication unit,
A test control unit. The test control unit is configured by software control (test control program). The test control section decodes various commands supplied from the adjustment inspection control PC 24 via the serial data communication section, and converts the conversion circuit section 16 and the test mode circuit 1
1 to execute various tests, and supply predetermined read data as a result of the various tests to the adjustment inspection control PC 24 via the serial data communication unit.
Note that the CPU unit 15 uses the one provided in the Ethernet interface unit.

The conversion circuit section 16 includes a test pattern for performing an adjustment test of the optical module section 3 and a test pattern generating section for generating a clock. The test pattern generator stores a plurality of test patterns registered in advance. The adjustment inspection control (setting) PC 24 supplies the CPU unit 15 with a command for specifying the optical module adjustment mode and data for selecting and specifying the test pattern.
The type of the test pattern generated from the test pattern generation unit in the conversion circuit unit 16 can be selected and designated via the CPU unit 15.

PC 24 for adjustment inspection control (for setting)
Indicates that the data instructing the generation / stop of the test pattern is C
By supplying the test pattern to the PU unit 15, transmission / stop of the test pattern can be controlled via the CPU unit 15. Note that a test pattern storage unit that stores a test pattern supplied from the outside to the conversion circuit unit 16 may be provided.

The adjustment inspection control (setting) PC 24 is C
By writing the test pattern data into the test pattern storage unit via the PU unit 15, a test pattern based on the written test pattern data can be generated from the test pattern generation unit in the conversion circuit unit 16. Thereby, an arbitrary test pattern can be generated.

FIG. 2 is a block diagram showing a specific example of the conversion circuit section. The conversion circuit section 16 includes a CPU-IF register section 31 having a plurality of registers, and a sequence control section 3.
2, the serial transmission / reception unit 33, and the PDS register unit 36
Consists of The serial transmission / reception section 33 includes an EEPROM forced transmission / reception section 34, an optical adjustment transfer section (clock generation section) 35
Is provided.

The CPU-IF register section 31 has registers such as a mode register, a status register, an address register, and various data registers. Each register is set with an individual address. And C
The PU-IF register unit 31 is connected to the CPU unit 15 via a data bus, an address bus, and a control bus.
The CPU-IF register unit 31 fetches the data supplied from the CPU unit 15 into a register specified by an address in synchronization with the write control signal. The CPU-IF register unit 31 outputs the contents of the register specified by the address to the CPU unit 15 in synchronization with the read control signal. CP
Each value stored in each register in the U-IF register unit 31 is supplied to another block corresponding to each register. Further, since the CPU-IF register unit 31 holds data written by another block, the CPU unit 15 specifies the address of the register and reads out the data, thereby writing the data written by the other block. Data can be obtained.

The sequence control unit 32 monitors the value of the mode register and the value of the status register of the CPU-IF register unit 31, and outputs a sequence start signal corresponding to a specific pattern input. In the present embodiment, there are six types of sequences. Further, the sequence control unit 32 clears the status register of the CPU-IF register unit 31 at the end of the sequence.

The EEPROM compulsory transmission / reception unit 34 receives a C signal based on a sequence start signal from the sequence control unit 32.
The contents of the PU-IF register 31 are converted to serial and output to the test mode circuit 11 together with the contents of the internal register. Further, the EEPROM forced transmission / reception unit 34 converts the data signal from the test mode circuit 11 into parallel based on the sequence start signal from the sequence control unit 32 and outputs the data signal to the CPU-IF register 31.

The light adjustment transfer section (clock generation section) 35
The contents of the data register in the CPU-IF register 31 are fetched based on a sequence start signal from the sequence control unit 32, converted into serial data, and continuously transmitted to the test mode circuit 11. When the contents of the data register match a specific pattern, the light adjustment transfer unit (clock generation unit) 35 continuously transmits the corresponding pattern to the test mode circuit 11.

The PDS register section 36 has a CPU-I based on a sequence start signal from the sequence control section 32.
The contents of the address register and data register in the F register 31 are output to the test mode circuit 11. Also, PD
The S register section 36 outputs data from the test mode circuit 11 to the CPU-IF register 31 based on a sequence start signal from the sequence control section 32.

FIG. 3 is a diagram showing a device configuration in the adjustment step. As described above, the integrated board 1 and the PC 24 for adjustment inspection control (for setting) are connected using the serial data interface (serial I / O). Code 18
Denotes a PDS unit. The PDS unit 18 includes the test mode circuit 11, the analog IC interface circuit 12, the EEPROM interface circuit 13, and the internal information circuit unit 14 shown in FIG.

As shown in FIG. 11, in the conventional optical network unit (ONU), the PDS unit (subscriber demultiplexing function unit and service demultiplexing function unit) and the Ethernet interface unit are different cards (separate cards). In the process inspection at the time of shipment, individual items are implemented for each card. On the other hand, in the present embodiment, the PDS unit and the Ethernet interface unit are integrated. Therefore, in addition to the inspection items for the Ethernet interface unit, the following (1)
By adding items (1) to (4), the PDS unit is inspected. (1) PDS internal information read function: Reads the internal settings of the PDS section. (2) Optical module adjustment function: Output of a pattern for laser diode (LD) output adjustment and eye pattern measurement during process inspection. (3) I / O pin check function: LS in process inspection
Provides an I / O pin check mode. (4) EEPROM forced writing function: Provides an EEPROM writing interface for saving the settings of the PDS unit.

FIG. 4 is a diagram showing a configuration example of the mode setting register. The mode register is a register for setting the adjustment mode. In the present embodiment, six types of adjustment modes of mode numbers a to f are set by all of the bits D7, D2, D1 and D0 of the mode register. The read mode by the CPU unit 15 and the CPU unit 1 are determined by the most significant bit of the mode register.
5 is set.

FIG. 5 is a diagram showing an operation sequence in the optical module adjustment mode. When a PDS test command is supplied from the setting PC 24, the CPU 15 clears the status register and then sets the PDS test mode. After setting a waveform pattern by writing a value to the data register 0, the CPU unit 15 writes a value for instructing register reading to the status register. Thus, transmission / stop of the signal from the conversion circuit unit 16 to the PDS unit is controlled.

FIG. 6 is a diagram showing an operation sequence in the EEPROM forced write mode. The data transferred from the setting PC 24 is stored in the SDRAM in the CPU unit 15 and then written into the EEPROM 4 by one byte. The writing for each byte is repeatedly executed for the file size.

FIG. 7 is a diagram showing the configuration of the optical module adjustment inspection system. An optical signal is continuously transmitted from the optical module unit (LD / PD) 3 using the optical module adjustment mode described above, and the intensity of the optical signal is measured by the optical power meter 30.
The data of the measured light intensity is, for example, GP-I
By supplying the adjustment inspection control (setting) PC 24 via the measurement interface bus such as B, the optical signal intensity can be automatically adjusted. PC for adjustment inspection control (for setting)
Reference numeral 24 denotes data for setting a bias current of a laser diode (LD) to be written into the EEPROM 4 and data for setting a drive current when the laser diode emits light so that the light intensity detected by the optical power meter 30 becomes a predetermined level. To change. As a result, the optical signal level of the upstream signal is automatically adjusted.

[0050]

As described above, the optical network unit (ONU) according to the present invention has a test pattern generator in the ONU, so that it does not require a dedicated measuring device such as a multi-channel generator. An adjustment inspection of the optical module can be performed. Further, since the optical network unit (ONU) according to the present invention includes the test control unit, the generation / stop of the test pattern and the clock can be controlled based on a test command supplied from the outside.

[Brief description of the drawings]

FIG. 1 is a diagram showing an ONU adjustment inspection system according to the present invention.

FIG. 2 is a block diagram showing a specific example of a conversion circuit.

FIG. 3 is a device configuration diagram in an adjustment process.

FIG. 4 is a diagram illustrating a configuration example of a mode setting register.

FIG. 5 is an operation sequence diagram in an optical module adjustment mode.

FIG. 6 is an operation sequence diagram in an EEPROM forced write mode;

FIG. 7 is a configuration diagram of an optical module adjustment / inspection system.

FIG. 8 is an example of an FTTH system having a PDS configuration.

FIG. 9 is a diagram showing a PDS transmission system.

FIG. 10 is a frame configuration diagram of a PDS optical subscriber system;

FIG. 11 is a functional block diagram of a conventional ONU.

FIG. 12 is a diagram showing a conventional adjustment and inspection system for ONU optical modules at a factory.

[Description of Signs] 1 Integrated board 2 Analog IC 3 Optical module unit (LD / PD) 4 EEPROM 5 ID setting switch unit 6, 7 Connector 10 Ether / PDS-LSI 11 Test mode circuit 12 Analog IC interface circuit 13 EEPROM Interface circuit 14 Internal information storage unit 15 CPU unit 18 PDS unit 16 Conversion circuit unit 21 I / O tester 22 PC for I / O test 23 Level converter 24 PC for adjustment inspection control (setting) 31 CPU-IF register unit 32 Sequence control Unit 33 serial transmission / reception unit 34 EEPROM forced transmission / reception unit 35 optical adjustment transfer unit (clock generation unit) 36 PDS register unit

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideaki Yatabe 3-1, Tsunashimahigashi 4-chome, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 2G086 BB01 5K002 AA05 BA13 DA12 EA06 FA01 GA03 5K042 AA03 BA01 CA10 EA03 JA10

Claims (3)

[Claims] 1. An optical subscriber line termination device installed on a user side of an optical subscriber line, wherein a test command signal issued via the optical subscriber line is decoded to check the adjustment of an optical module unit. And a test control unit for controlling generation and stop of a clock, and a test pattern generation unit for generating the test pattern and the clock based on a control signal from the test control unit. The optical network unit. 2. The optical network unit according to claim 1, wherein said test pattern generator stores a plurality of test patterns registered in advance. 3. The optical network unit according to claim 1, wherein said test pattern generation unit includes a test pattern storage unit for storing a test pattern instructed from outside.