KR100270021B1 - Parity checking device of interface data - Google Patents

Abstract

PURPOSE: A device for checking a parity of interface data is provided to easily confirm troubles of the cable when adjacent shelves are connected to a cable so as to check cable error. CONSTITUTION: A window generator(10) generates a window corresponding to a using time slot. A frame parity checker(12) performs a conjunction for the window and frame data synchronized with a determined clock signal, and checks a parity of the using time slot by the data. A parity supplier(14) loads parity information of an E1 frame on a specific bit. A latch(16) latches remaining time slot data except for a frame alignment byte of a 0th time slot among the using time slot of the E1 frame. A multiplexer(18) multiplexes the data of the E1 frame and the parity information, and transmits the multiplexed data and the parity information to other party.

Description

Parity check device of interface data

The present invention relates to an apparatus for checking parity of interface data. In particular, the present invention provides an apparatus for easily checking when a problem occurs on a cable when adjacent shelves (Shelfs) interfaced with an E1 frame are connected by a cable.

In the related art, when adjacent shelves interfacing with E1 frames are connected by cables, it is not possible to check an error of data to be transmitted to each other, and thus there is a problem that it is not possible to know whether data transmission is smoothly performed.

Accordingly, an object of the present invention is to check the parity bit of the time slot used in the E1 frame when cables are connected between adjacent shelves that interface with the E1 frame, thereby easily confirming when a problem occurs on the cable. It is to provide a parity check device of the interface data.

Technical means of the present invention for achieving the above object, the window generating unit for generating a window corresponding to the time slot to be used among a plurality of timeslots of the E1 frame; A frame parity check unit configured to perform an AND operation on the window data generated by the window generation unit and the frame data synchronized with a predetermined clock signal, and to check the parity of the timeslot used for the frame by the AND product; A parity supply unit which carries parity information of an E1 frame output from the frame parity checker to a specific bit among a plurality of redundant bits of a 0th time slot; A latch unit for latching the remaining time slot data except the frame alignment byte of the 0 th time slot of the used time slots of the E1 frame according to the clock signal; And a multiplexer for multiplexing and transmitting the data of the corresponding E1 frame latched by the latch unit and the parity information contained in the 0 th time slot output from the parity supply unit.

1 is a block diagram showing an interface check apparatus according to the present invention,

FIG. 2 is a detailed circuit diagram illustrating a frame parity check unit of FIG. 1.

* Explanation of symbols for main parts of the drawings

10: window generation unit 12: frame data check unit

14 parity supply unit 16 latch unit

18: multiplexer

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an interface check apparatus according to the present invention, wherein the window generating unit 10 and the window generating unit 10 generate a window corresponding to a time slot used among a plurality of time slots of an E1 frame. A frame parity check unit 12 for logically multiplying the received window and frame data synchronized with a predetermined clock signal (2MHz) and checking the parity of the timeslot used for the frame by the logical multiplication data, and the frame parity check A parity supply unit 14 which carries parity information of the E1 frame output from the unit 12 to a specific bit among a plurality of redundant bits of the 0th time slot, and an E1 frame according to a predetermined clock signal (2 MHz). A latch portion 16 for latching the remaining timeslot data except for the frame alignment byte of the 0th timeslot among the timeslots of the < RTI ID = 0.0 > And a multiplexer 18 for multiplexing the data of the corresponding E1 frame and the parity information contained in the 0th time slot output from the parity supply unit 14. FIG.

In addition, the configuration of the E1 frame (Frame) is composed of two frame units, all the 0 th time slot (Time Slot) of the first frame is used as a frame word, bits 3 ~ 0 of the 0 th time slot of the second frame Is used as an extra bit for monitor.

The window generation unit 10 is a part for making an enable signal of a part of the format of the E1 frame except bits 3 to 0 of the 0th timeslot of the second frame (bits 3 to 0). All parts except the 'high' signal will be output.

Accordingly, the window generation unit 10 supplies the generated enable signal to the frame data check unit 12, and the frame data check unit 12 transmits the bits of the 0 th timeslot of the second frame according to the enable signal. Parity is generated by the parity supply unit 14 by passing data excluding parts 3 to 0, and then loaded into bits 3 to 0 of the 0 th timeslot of the second frame of the next E1 frame.

When described with reference to Figure 2 attached to the operation and operation of the present invention configured as described above are as follows.

First, the window generated by the window generation unit 10 is multiplied by the data of the E1 frame to be input to the deflip-flop (D1) of the frame parity check unit 12, the deflip-flop (D1) is input data When outputting to the exclusive logic gate (EX1) in synchronization with a clock corresponding to 2.048 MHz, the output data of the exclusive logic gate (EX1) is fed back to output a 'high' signal only when the signals are different and use the time slot of the E1 frame. Check the parity of the.

When the latch unit 16 latches data of the timeslot used by the E1 frame, the latch unit 16 latches the E1 frame data excluding the frame alignment byte of the 0th timeslot, and the parity supply unit 14 latches the corresponding E1 frame. The parity information of the E1 frame is loaded into one bit of the extra bits of the 0 th timeslot of the E1 frame, and the multiplexer multiplexes the parity information carried in the extra bits of the 0 th time slot with the data of the corresponding E1 frame latched by the latch unit. multiplexing) to deliver to the other party.

At this time, the frame alignment signal of the 0 th timeslot of the E1 frame is not included.

As described above, a path can be monitored by the E1 frame itself without the need for designing a parity line separately at the interface of the E1 frame.

Therefore, in the present invention, when the adjacent shelves are connected to each other by a cable, problems on the cable can be easily identified, and thus, when an interface to a nearby device or a cable or other device is interfaced, there is an effect of easily checking for abnormality of the cable or the device.

Claims (2)

A window generation unit generating a window corresponding to a time slot used among a plurality of time slots of the E1 frame; A frame parity check unit configured to perform an AND operation on the window data generated by the window generation unit and the frame data synchronized with a predetermined clock signal, and to check the parity of the timeslot used for the frame by the AND product; A parity supply unit which carries parity information of an E1 frame output from the frame parity checker to a specific bit among a plurality of redundant bits of a 0th time slot; A latch unit for latching the remaining time slot data except the frame alignment byte of the 0 th time slot among the used time slots of the E1 frame according to the clock signal; And a multiplexer for multiplexing and transmitting the data of the corresponding E1 frame latched by the latch unit and the parity information contained in the 0th time slot output from the parity supply unit. The apparatus of claim 1, wherein the frame parity check unit comprises: a flip-flop provided with data obtained by logically multiplying a window generated by the window generator with data of an E1 frame according to the clock signal, and output and feedback of the flip-flop And an exclusive logic sum gate for outputting a 'high' signal when a different output signal is received and a different output signal is input.