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JP2002374131A - Automatic correction circuit of operational amplifier offset voltage - Google Patents

Automatic correction circuit of operational amplifier offset voltage

Info

Publication number
JP2002374131A
JP2002374131A JP2001180108A JP2001180108A JP2002374131A JP 2002374131 A JP2002374131 A JP 2002374131A JP 2001180108 A JP2001180108 A JP 2001180108A JP 2001180108 A JP2001180108 A JP 2001180108A JP 2002374131 A JP2002374131 A JP 2002374131A
Authority
JP
Japan
Prior art keywords
voltage
operational amplifier
offset voltage
circuit
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001180108A
Other languages
Japanese (ja)
Inventor
Shoko Cho
小興 張
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2001180108A priority Critical patent/JP2002374131A/en
Publication of JP2002374131A publication Critical patent/JP2002374131A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To automatically correct an offset voltage by using an input offset voltage of an operational amplifier. SOLUTION: When an input offset voltage Voffset of the operational amplifier OP is generated, the voltage of a non-inverted input terminal of the operational amplifier is a reference voltage VREF, the input offset voltage is applied to an inverted input terminal, and (1+RF/RG)×Voffset appears as the output voltage of an inversion amplification circuit. When the voltage of the non-inverted input terminal of the operational amplifier is corrected as VREF-Voffset by using this circuit, the voltage of the inverted input terminal become equal to the reference voltage VREF and the inverted amplification circuit can obtain an output voltage which is not related to the input offset voltage Voffset .

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,反転増幅回路及び
アクティブフィルタなどのアナログ信号処理回路に用い
られる演算増幅器のオフセット電圧自動校正回路に関す
る。
The present invention relates to an automatic offset voltage calibration circuit for an operational amplifier used in an analog signal processing circuit such as an inverting amplifier circuit and an active filter.

【0002】[0002]

【従来の技術】図3は,従来の演算増幅器のオフセット
電圧調整回路のブロック図である。通常これらの技術
は,演算増幅器の入力オフセット電圧を検出し,その電
圧を電流に変換し,また入力オフセット電圧に合わせる
調整を行い,入力端子で入力オフセット電圧による出力
を引く。
2. Description of the Related Art FIG. 3 is a block diagram of a conventional offset voltage adjusting circuit of an operational amplifier. Normally, these techniques detect an input offset voltage of an operational amplifier, convert the voltage to a current, make adjustments to match the input offset voltage, and pull the output by the input offset voltage at an input terminal.

【0003】[0003]

【発明が解決しようとする課題】ここで、正確に電圧調
整するため,入力オフセット電圧検出回路自身の入力オ
フセット電圧を克服するのが困難であり,その精度が高
く要求され,半導体の製造のプロセスも難しいという課
題がある。
Here, in order to accurately adjust the voltage, it is difficult to overcome the input offset voltage of the input offset voltage detection circuit itself, and high accuracy is required. Is also difficult.

【0004】さらに,アナログ信号処理回路に用いられ
る演算増幅器の入力オフセット電圧Voffsetが生じる場
合,従来の技術は外付け回路を利用し,外部のパラメー
タなどの設定と調整を行う必要がある。
Further, when an input offset voltage V offset of an operational amplifier used in an analog signal processing circuit occurs, the conventional technique needs to use an external circuit to set and adjust external parameters and the like.

【0005】[0005]

【課題を解決する為の手段】本発明の目的は,これらの
設定と調整を一切行わず,また製造上のばらつきと温度
特性に関わらず,演算増幅器の非反転入力電圧を調整
し,オフセット電圧Vo ffsetに関係なく理想出力に等し
い安定した出力信号を得ることにある。
SUMMARY OF THE INVENTION It is an object of the present invention to adjust and adjust the non-inverting input voltage of an operational amplifier irrespective of manufacturing variations and temperature characteristics without performing any of these settings and adjustments. is to obtain a stable output signal is equal to the ideal output regardless V o ffset.

【0006】本発明はチップ内蔵回路で,演算増幅器の
オフセット電圧Voffsetの検出と反転増幅を行い,正電
源VDDのみにて動作する回路の場合,演算増幅器の反転
入力端子と非反転入力端子の電圧をそれぞれVDD/2とVD
D/2−Voffsetに,正電源VDDと負電源VSSにて動作する
回路の場合,演算増幅器の反転入力端子と非反転入力端
子の電圧をGNDと−Voffsetに自動調整し,理想出力に等
しい出力信号得られるオフセット電圧自動校正回路を設
けたものである。
According to the present invention, in a circuit with a built-in chip, which detects an offset voltage V offset of an operational amplifier and inverts and amplifies it, and operates only with a positive power supply VDD, the inverting input terminal and non-inverting input terminal of the operational amplifier are used. Voltage is VDD / 2 and VD respectively
In the case of a circuit that operates with the positive power supply VDD and the negative power supply VSS at D / 2−V offset , the voltage of the inverting input terminal and non-inverting input terminal of the operational amplifier is automatically adjusted to GND and −V offset , and the ideal output is obtained. An offset voltage automatic calibration circuit for obtaining an equal output signal is provided.

【0007】[0007]

【発明の実施の形態】図1に本発明によるオフセット電
圧自動校正の具体的な回路構成を示す。アナログ信号処
理回路においては,入力Vinを基準電源VREFに接続し,
出力Voutをアナログ信号処理回路に用いられる演算増幅
器の非反転入力端子に接続する。
FIG. 1 shows a specific circuit configuration of the automatic offset voltage calibration according to the present invention. In the analog signal processing circuit is connected to the input V in to the reference power supply V REF,
The output Vout is connected to a non-inverting input terminal of an operational amplifier used in an analog signal processing circuit.

【0008】本発明においては、入力電圧を入力する一
方の入力端子と、基準電源電圧を入力する他方の入力端
子を有し、オフセット電圧を検出する第1の反転増幅器
と、前記第1の反転増幅器の出力接続する非反転入力端
子を有する第2の反転増幅器からなる演算増幅器電圧校
正回路とした。
According to the present invention, there is provided a first inverting amplifier having one input terminal for inputting an input voltage and the other input terminal for inputting a reference power supply voltage, for detecting an offset voltage, and the first inverting amplifier. An operational amplifier voltage calibration circuit comprising a second inverting amplifier having a non-inverting input terminal connected to the output of the amplifier.

【0009】ここで、前記第1の反転増幅器または前記
第2の反転増幅器に接続された抵抗が、基本セルまたは
基本セルが直列に接続された抵抗を使用することができ
る。
Here, as the resistor connected to the first inverting amplifier or the second inverting amplifier, a basic cell or a resistor in which basic cells are connected in series can be used.

【0010】また、本発明においては、入力端子を基準
電源VREFに接続し,一段目の反転増幅器によって演算増
幅器のオフセット電圧を検出し,前記オフセット電圧を
二段目で調整し,出力端子を反転増幅回路及びアクティ
ブフィルタなどのアナログ信号処理回路に用いられる演
算増幅器の非反転入力端子に接続し,演算増幅器のオフ
セット電圧を自動校正する回路を設けたことを特徴とす
るチップ内蔵演算増幅器オフセット電圧自動校正回路と
した。
In the present invention, the input terminal is connected to the reference power supply V REF , the offset voltage of the operational amplifier is detected by the inverting amplifier of the first stage, the offset voltage is adjusted by the second stage, and the output terminal is connected. An operational amplifier offset voltage built in a chip, comprising a circuit connected to a non-inverting input terminal of an operational amplifier used for an analog signal processing circuit such as an inverting amplifier circuit and an active filter, and for automatically calibrating an offset voltage of the operational amplifier. An automatic calibration circuit was used.

【0011】そして、前記チップ内蔵演算増幅器オフセ
ット電圧自動校正回路に接続された抵抗が、基本セル及
び基本セルの正数倍の抵抗で,基本セルの直列に接続さ
れたことを特徴とするチップ内蔵演算増幅器オフセット
電圧自動校正回路。
The resistor connected to the operational amplifier offset voltage automatic calibration circuit with built-in chip is connected in series with the basic cell with a resistance of a positive multiple of the basic cell and the basic cell. Operational amplifier offset voltage automatic calibration circuit.

【0012】[0012]

【実施例】ここで,図面を参照して本発明の実施例を説
明する。図1は、本発明の実施例を示す回路で、回路入
力電圧Vinと基準電源電圧VREFを入力した演算増幅器O
P1と、回路入力電圧Vinに直列に接続された抵抗Rs1
と,演算増幅器の入出力端子間に接続された抵抗R
F1と、抵抗RF1に接続された図2のような反転増幅回路
の縦続接続したものである。回路は動作する場合,演算
増幅器の非反転入力端子を基準電源VREFに接続する。こ
の回路を例として解析する。演算増幅器OPを理想なもの
とすると,反転入力端子の電圧VAと非反転入力端子の電
圧VBは、式(1)
An embodiment of the present invention will now be described with reference to the drawings. FIG. 1 shows a circuit according to an embodiment of the present invention, in which an operational amplifier O to which a circuit input voltage Vin and a reference power supply voltage VREF are inputted.
And P1, resistor R s1 connected in series to the circuit input voltage V in
And a resistor R connected between the input and output terminals of the operational amplifier.
This is a cascade connection of F1 and an inverting amplifier circuit as shown in FIG. 2 connected to a resistor R F1 . When the circuit operates, the non-inverting input terminal of the operational amplifier is connected to the reference power supply V REF . This circuit will be analyzed as an example. When the operational amplifier OP the ideal ones, the voltage V B of the voltage V A of the inverting input and non-inverting input terminal of the formula (1)

【0013】[0013]

【式1】 (Equation 1)

【0014】となる。入力信号Vinと出力信号VOUTの関
係を式(2)で表わす。
## EQU1 ## The relationship between the input signal V in and the output signal V OUT represented by the formula (2).

【0015】[0015]

【式2】 (Equation 2)

【0016】実際の応用においては,演算増幅器OPは非
理想なものであり,入力オフセット電圧Voffsetが生じ
る場合,それを考慮した入力信号と出力信号の関係は式
(3)になる。
In an actual application, the operational amplifier OP is non-ideal, and when an input offset voltage V offset occurs, the relationship between the input signal and the output signal taking into account the input offset voltage V offset is expressed by equation (3).

【0017】[0017]

【式3】 (Equation 3)

【0018】入力端子電圧VAとVBは、式(4)となる。The input terminal voltage V A and V B is a formula (4).

【0019】[0019]

【式4】 (Equation 4)

【0020】ここで,VB=VREF,従って,VA=VREF+V
offsetとなる。入力信号Vinと出力信号Voutの関係を式
(5)のように表現する。
Here, V B = V REF , therefore, V A = V REF + V
offset . The relationship between the input signal V in and the output signal V out is expressed by the equation (5).

【0021】[0021]

【式5】 (Equation 5)

【0022】式(5)より分かるように,演算増幅器の
入力オフセット電圧Voffsetを(1+R F/RS)倍に増幅し
て出力する。また式(2)と比べ,入力オフセット電圧V
offse tは出力誤差が生じる要因となる。
As can be seen from equation (5), the operational amplifier
Input offset voltage VoffsetTo (1 + R F/ RS) Amplify twice
Output. Also, compared to equation (2), the input offset voltage V
offse tCauses an output error.

【0023】図2の解析より,入力オフセット電圧V
offsetを考慮した図1の回路を解析する。上に述べたよ
うに,図1の回路は図2の回路を縦続接続したものであ
る。図1に示すように,一段目の反転増幅回路の入力電
圧をVin,出力電圧をVo1とすると,二段目の入力電圧と
出力電圧はそれぞれVo1,Vo2となる。すると,式(5)
より全体回路の入力と出力関係は式(6)で表わされ
る。
From the analysis of FIG. 2, the input offset voltage V
The circuit of FIG. 1 considering the offset is analyzed. As mentioned above, the circuit of FIG. 1 is a cascade connection of the circuit of FIG. As shown in FIG. 1, the input voltage of the inverting amplifier circuit in the first stage V in, the output voltage and V o1, the respective input and output voltages of the second stage V o1, V o2. Then, equation (5)
The relationship between the input and output of the entire circuit is expressed by equation (6).

【0024】[0024]

【式6】 (Equation 6)

【0025】ここで,図2と同様にVB=VREF,VA=VREF
+Voffsetである。また入力電圧Vin=VREFを式(6)に
代入すると,出力電圧Vo2は式(7)となる。
Here, similarly to FIG. 2, V B = V REF and V A = V REF
+ V offset . The Substituting input voltage V in = V REF in equation (6), the output voltage V o2 becomes Equation (7).

【0026】[0026]

【式7】 Equation 7

【0027】式(2)と式(3)を比較すると,演算増幅
器の反転入力端子の電圧VAを基準電圧VREFにすれば,式
(2)のような入力オフセット電圧Voffsetと無関係に理
想的な出力電圧VOUTを得ることができる。また式(4)
より,VA=VREFにするため,演算増幅器の非反転入力端
子の電圧VBは基準電圧VREFではなく,基準電圧からオフ
セット電圧を引けば良い、式(8)。
Comparing equations (2) and (3), if the voltage VA at the inverting input terminal of the operational amplifier is set to the reference voltage V REF , regardless of the input offset voltage V offset as in equation (2) An ideal output voltage V OUT can be obtained. Equation (4)
Accordingly, in order to make V A = V REF , the voltage V B at the non-inverting input terminal of the operational amplifier may be obtained by subtracting the offset voltage from the reference voltage instead of the reference voltage V REF (Equation (8)).

【0028】[0028]

【式8】 (Equation 8)

【0029】更に,式(7)と(8)より,図1回路の出
力電圧Vo2をVBにすれば,式(9)が得られる。
Furthermore, from equations (7) (8), if the output voltage V o2 of Figure 1 circuit to V B, the equation (9) is obtained.

【0030】[0030]

【式9】 [Equation 9]

【0031】式(9)より,入力オフセット電圧に関係
なく,抵抗値の比例関係のみとなる。それは式(10)
のように表現できる。
From equation (9), there is only a proportional relationship between the resistance values irrespective of the input offset voltage. It is equation (10)
Can be expressed as

【0032】[0032]

【式10】 (Equation 10)

【0033】式(10)より,それぞれの抵抗値は、式
(11)となる。
From Equation (10), each resistance value is given by Equation (11).

【0034】[0034]

【式11】 [Equation 11]

【0035】とすると,式(12)となる。Then, equation (12) is obtained.

【0036】[0036]

【式12】 (Equation 12)

【0037】となる。ここで,R0を抵抗の基本セルと
し,式(11)と(12)より抵抗RS1、R S2、RF1、RF2は全
て基本セルR0によって構成されれば,抵抗値の精度に関
係なく,式(10)に示すような比例さえ保つことができ
れば,温度特性,抵抗値のバラツキに強い安定した出力
電圧が得られるものである。
Is as follows. Where R0The resistance of the basic cell and
Equation (11) and (12) show that the resistance RS1, R S2, RF1, RF2Is all
Base cell R0If it is composed of
Regardless, the proportionality as shown in equation (10) can be maintained.
And stable output that is resistant to variations in temperature characteristics and resistance
A voltage is obtained.

【0038】[0038]

【発明の効果】上述のように,本発明はアナログ信号処
理回路に用いられる演算増幅器と同様なものを使用し,
基本抵抗セルR0を用いた簡単な回路構成である。また,
それぞれの演算増幅器と抵抗は同一半導体基板上で作ら
れ,演算増幅器が同じもので,その精度が特別に要求さ
れていない。更に式(10)より抵抗値の精度に関係な
く,その比例関係のみが要求される。最後に回路の入力
電圧は安定的な基準電圧VR EFなので,温度特性とパラメ
ータのバラツキに強い安定的な出力電圧が容易に実現で
きるという優れた効果を有する。
As described above, the present invention uses an operational amplifier similar to that used in an analog signal processing circuit.
This is a simple circuit configuration using a basic resistance cell R0 . Also,
The operational amplifiers and resistors are made on the same semiconductor substrate, and the operational amplifiers are the same, and the precision is not particularly required. Further, from equation (10), only the proportional relationship is required regardless of the accuracy of the resistance value. Finally the input voltage of the circuit has an excellent effect of so stable reference voltage V R EF, strong stable output voltage by variations in the temperature characteristics and parameters can be easily realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】本発明の実施例に関する反転増幅回路である。FIG. 2 is an inverting amplifier circuit according to an embodiment of the present invention.

【図3】従来の技術による調整回路ブロック図である。FIG. 3 is a block diagram of an adjustment circuit according to a conventional technique.

【図4】本発明の効果を確認する実施例を示す回路図で
ある。
FIG. 4 is a circuit diagram showing an example for confirming the effect of the present invention.

【図5】図4の回路のDC出力特性を示す図である。FIG. 5 is a diagram showing DC output characteristics of the circuit of FIG.

【図6】本発明に関する他の実施例を示す図である。FIG. 6 is a diagram showing another embodiment according to the present invention.

【符号の説明】[Explanation of symbols]

OP,OP1,OP2 演算増幅器 R0,RS,RF,RS1,RF1,RS2,RF2 抵抗 Vin 回路入力電圧 Vout,VOUT,Vo1,Vo2 回路出力電圧 VA 演算増幅器の反転入力端子電圧 VB 演算増幅器の非反転入力端子電圧 Voffset 演算増幅器の入力オフセット電圧 VDD 正電源電圧 VSS 負電源電圧 VREF 基準電源電圧 GND グランドOP, OP1, OP2 Operational amplifiers R 0 , R S , R F , R S1 , R F1 , R S2 , R F2 Resistance V in Circuit input voltage V out , V OUT , V o1 , V o2 Circuit output voltage V A calculation inverting input terminal voltage V B operational amplifier input offset voltage VDD positive power supply voltage VSS negative supply voltage V REF reference source voltage GND ground the non-inverting input terminal voltage V offset operational amplifier in amplifier

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 入力電圧を入力する一方の入力端子と、
基準電源電圧を入力する他方の入力端子を有し、オフセ
ット電圧を検出する第1の反転増幅器と、前記第1の反
転増幅器の出力接続する非反転入力端子を有する第2の
反転増幅器からなる演算増幅器電圧校正回路。
A first input terminal for inputting an input voltage;
An operation comprising a first inverting amplifier having another input terminal for inputting a reference power supply voltage and detecting an offset voltage, and a second inverting amplifier having a non-inverting input terminal connected to the output of the first inverting amplifier. Amplifier voltage calibration circuit.
【請求項2】 前記第1の反転増幅器または前記第2の
反転増幅器に接続された抵抗が、基本セルまたは基本セ
ルが直列に接続された抵抗である請求項1記載の演算増
幅器電圧校正回路。
2. The operational amplifier voltage calibration circuit according to claim 1, wherein the resistor connected to the first inverting amplifier or the second inverting amplifier is a basic cell or a resistor in which basic cells are connected in series.
【請求項3】 入力端子を基準電源VREFに接続し,一段
目の反転増幅器によって演算増幅器のオフセット電圧を
検出し,前記オフセット電圧を二段目で調整し,出力端
子を反転増幅回路及びアクティブフィルタなどのアナロ
グ信号処理回路に用いられる演算増幅器の非反転入力端
子に接続し,演算増幅器のオフセット電圧を自動校正す
る回路を設けたことを特徴とするチップ内蔵演算増幅器
オフセット電圧自動校正回路。
3. An input terminal is connected to a reference power supply V REF , an offset voltage of an operational amplifier is detected by an inverting amplifier of a first stage, the offset voltage is adjusted by a second stage, and an output terminal is connected to an inverting amplifier circuit and an active amplifier. An on-chip operational amplifier offset voltage automatic calibration circuit, comprising: a circuit connected to a non-inverting input terminal of an operational amplifier used for an analog signal processing circuit such as a filter, for automatically calibrating an offset voltage of the operational amplifier.
【請求項4】 前記チップ内蔵演算増幅器オフセット電
圧自動校正回路に接続された抵抗が、基本セル及び基本
セルの正数倍の抵抗で,基本セルの直列に接続されたこ
とを特徴とするチップ内蔵演算増幅器オフセット電圧自
動校正回路。
4. A chip built-in chip wherein the resistor connected to the chip built-in operational amplifier offset voltage automatic calibration circuit is connected in series with the base cell and a resistance of a positive multiple of the base cell. Operational amplifier offset voltage automatic calibration circuit.
JP2001180108A 2001-06-14 2001-06-14 Automatic correction circuit of operational amplifier offset voltage Pending JP2002374131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001180108A JP2002374131A (en) 2001-06-14 2001-06-14 Automatic correction circuit of operational amplifier offset voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001180108A JP2002374131A (en) 2001-06-14 2001-06-14 Automatic correction circuit of operational amplifier offset voltage

Publications (1)

Publication Number Publication Date
JP2002374131A true JP2002374131A (en) 2002-12-26

Family

ID=19020574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001180108A Pending JP2002374131A (en) 2001-06-14 2001-06-14 Automatic correction circuit of operational amplifier offset voltage

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100698332B1 (en) 2005-02-04 2007-03-23 삼성전자주식회사 Gain Control Amplifier
KR100744592B1 (en) * 2005-10-25 2007-08-01 후지쯔 가부시끼가이샤 Dc-dc converter, dc-dc converter control circuit, and dc-dc converter control method
JP2010004193A (en) * 2008-06-19 2010-01-07 Mitsumi Electric Co Ltd Semiconductor integrated circuit device and offset cancel setting system
CN103675651A (en) * 2013-12-25 2014-03-26 工业和信息化部电子第五研究所 Test system of long-term stability of input offset voltage of operational amplifier
CN111766435A (en) * 2019-04-02 2020-10-13 全球能源互联网研究院有限公司 Active calibration high-voltage measuring device and method
CN113114144A (en) * 2021-05-11 2021-07-13 山东浪潮科学研究院有限公司 Circuit for correcting input offset voltage in quantum measurement and control system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100698332B1 (en) 2005-02-04 2007-03-23 삼성전자주식회사 Gain Control Amplifier
KR100744592B1 (en) * 2005-10-25 2007-08-01 후지쯔 가부시끼가이샤 Dc-dc converter, dc-dc converter control circuit, and dc-dc converter control method
US7279870B2 (en) 2005-10-25 2007-10-09 Fujitsu Limited DC-DC converter and method of controlling DC-DC converter
JP2010004193A (en) * 2008-06-19 2010-01-07 Mitsumi Electric Co Ltd Semiconductor integrated circuit device and offset cancel setting system
CN103675651A (en) * 2013-12-25 2014-03-26 工业和信息化部电子第五研究所 Test system of long-term stability of input offset voltage of operational amplifier
CN111766435A (en) * 2019-04-02 2020-10-13 全球能源互联网研究院有限公司 Active calibration high-voltage measuring device and method
CN113114144A (en) * 2021-05-11 2021-07-13 山东浪潮科学研究院有限公司 Circuit for correcting input offset voltage in quantum measurement and control system
CN113114144B (en) * 2021-05-11 2022-05-13 山东浪潮科学研究院有限公司 Circuit for correcting input offset voltage in quantum measurement and control system

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