JP2002353305A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent voids from occurring in a wiring and a plug when a multilayer interconnection structure is formed by forming the wiring and the plug using a groove interconnection method in a manufacturing process of a semiconductor device. SOLUTION: In a method for manufacturing the semiconductor device, where the wiring grooves 11, 14 or a contact hole 9 are formed in insulating films 2, 5, 7, and a metal material layer (Cu film 17) is formed so as to be buried in the wiring grooves 11, 14 or the contact hole 9, and the groove wirings 3, 12 or the plug 10 are formed by eliminating the metal material layer on the insulating films 2, 7, and barrier layers 4, 8 are formed thereupon, and the wiring layer is further formed on the barrier layers 4, 8, after having formed the groove wirings 3, 12 or the plug 10, before forming the barrier layers 4, 8, an annealing is performed by introducing an oxidizing gas and a reducing gas at the same time or alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which wiring and plugs are formed by a trench wiring method.

[0002]

2. Description of the Related Art With the miniaturization and high integration of semiconductor devices,
In the internal wiring, resistance rise due to fine wiring,
There are problems such as a wiring delay and a decrease in reliability due to an increase in wiring capacitance. Therefore, as the wiring material, the conventional Al
Instead of alloy material, C with low resistance and excellent wiring reliability
The development and introduction of u-wiring is rapidly progressing.

[0003] In general, it is difficult to form a wiring or a plug by forming a wiring groove or a connection hole in an insulating film and embedding a metal material in the wiring groove or the connection hole because it is difficult to process a Cu wiring with high precision by dry etching. It is formed by a groove wiring method. As the groove wiring method, a so-called single damascene method, in which a wiring groove and a connection hole are separately formed, and a so-called dual damascene method, in which a wiring groove and a connection hole are opened and a metal material is buried at the same time, have been developed. And
The latter method has the advantage of fewer process steps.

FIG. 4 is a cross-sectional view of a typical example of a Cu wiring formed by a dual damascene method. In this wiring structure, a substrate 1 on which a transistor or the like is formed, a first insulating film 2 made of SiO ₂ formed on the substrate 1, and a lower Cu wiring 3 embedded in the first insulating film 2 Si formed sequentially on the Cu wiring 3 and the first insulating film 2
The second barrier layer 6 made of the second insulating film 5, SiN formed of the first barrier layer 4, SiO ₂ consisting of N, SiO ₂
Insulating film 7 made of SiN, third barrier layer 8 made of SiN, connecting hole 9 formed in second insulating film 5, wiring groove 11 formed in third insulating film 7, connecting hole 9 And wiring groove 11
Plug 10 and Cu embedded through a TaN layer 13
It consists of wiring 12. Here, the barrier layers 4 and 8
Is provided to prevent diffusion and oxidation of Cu.

On the other hand, in order to solve the problem of wiring delay, a technique for forming a low dielectric constant film such as an organic polymer in place of the conventional interlayer insulating film mainly composed of SiO ₂ has been introduced. Attempts have been made to further improve the wiring delay by combining the dielectric film technology and the Cu wiring technology.

[0006]

However, the above-mentioned conventional Cu wiring technique by the groove wiring method has the following problems. That is, an insulating film is further deposited on the Cu wiring 12 covered with the barrier layer 8, and an upper wiring layer is formed. Deposition of the insulating film involves heating of the substrate. For example, SiO 2 is used as an insulating film by plasma CVD.
_When forming the film ₂ , the substrate is usually heated to 350 to 400 ° C. When a low dielectric constant film made of an organic polymer is formed as an insulating film, a heat treatment at about 400 ° C. is performed as a cure after the application of the organic polymer. When such a heat treatment is performed, the Cu wirings 3 and 12
As shown in FIG. 5, the interface between the upper part of the Cu wiring 3 and the barrier layer 4 and the upper part of the Cu wiring 12 and the barrier layer 8 due to the growth of Cu crystal grains and the effect of surface diffusion accompanying the release of Cu surface energy. Void A is formed at the interface with. Void A
Is formed, electromigration and stress migration of Cu are promoted due to the void A when the Cu wiring 12 is used, and the reliability of the wiring is reduced.

In order to solve such a problem, the present invention does not cause voids in wirings and plugs when forming wirings and plugs by a trench wiring method and forming a multilayer wiring structure in a semiconductor device manufacturing process. The purpose is to be.

[0008]

Means for Solving the Problems The present inventor has proposed that (i) growth of Cu crystal grains and surface diffusion immediately before the Cu wiring or plug formed by the trench wiring method is covered with the barrier layer, and then the barrier Even if heat treatment is performed to deposit an insulating film on the layer,
(Ii) growth of Cu crystal grains usually proceeds by heating at about 300 ° C.
Since surface diffusion of Cu occurs at a high temperature of 500 ° C. or higher, C
Such high-temperature heat treatment is required to grow Cu crystal grains and diffuse the surface of the u-wiring or plug, but such high-temperature heat treatment reduces the reliability of the wiring. In addition, where it is impossible to use a low-dielectric-constant film having relatively low heat resistance such as an organic polymer, an oxidizing gas and a reducing gas are introduced into the surface of the Cu wiring or plug and annealing is performed. By heating the substrate at about 400 ° C., not only the growth of Cu crystal grains but also the surface diffusion can be sufficiently advanced. (Iii) Therefore, such annealing
It has been found that the above object can be achieved by performing the process immediately before the u wiring and the plug are covered with the barrier layer.

That is, the present invention provides a method of forming a wiring groove or a connection hole in an insulating film, forming a metal material layer so as to fill the wiring groove or the connection hole, and removing the metal material layer on the insulating film. In a method for manufacturing a semiconductor device in which a grooved wiring or a plug is formed, a barrier layer is formed thereon, and a wiring layer is further formed on the barrier layer, after forming the grooved wiring or the plug and before forming the barrier layer And an oxidizing gas and a reducing gas are simultaneously or alternately introduced and annealed to provide a method of manufacturing a semiconductor device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

FIG. 1 and FIG. 2 are process explanatory views of one embodiment of the present invention.

In this embodiment, an insulating film 2 is formed on a substrate 1 on which element isolation, element formation and the like have been performed.
_Two films are deposited in a thickness of 300 to 600 nm by a CVD method, and a wiring groove 14 is formed by ordinary dry etching.
(1)).

Next, the Ta film 15 and the Cu film 16 are each 30 nm thick by DC magnetron sputtering.
Deposit about 50 nm (FIG. 1 (2)).

Next, a Cu film 17 is deposited to a thickness of about 1.5 μm by electroplating, and Cu is filled in the wiring groove 14 (FIG. 1C).

Next, the Ta film 15 and the Cu films 16 and 17 deposited on the insulating film 2 other than the area where the wiring groove 14 is formed are polished and removed by CMP (chemical mechanical polishing). 14 are filled with Cu films 16 and 17 by Cu wiring 3
(FIG. 1 (4)).

After forming the Cu wiring 3 in this manner, annealing is performed (FIG. 1 (5)).

In this annealing, an ordinary annealing furnace is used, O ₂ is used as an oxidizing gas, H ₂ is used as a reducing gas, and a mixed gas thereof is introduced into the substrate under the following conditions, for example. Performed by H ₂ partial pressure: 10 Torr (1.3 × 10 ³ Pa) O ₂ partial pressure: 1 Torr (1.3 × 10 ² Pa) Temperature: 350 ° C. Time: 30 minutes

By this annealing, the next oxidation reaction and reduction reaction are continuously performed on the surface of the Cu wiring 3 filled in the wiring groove 14.

[0019]

## EQU1 ## Cu + _1/2 O ₂ = CuO-37.9 kcal / mol CuO + H ₂ = Cu + H ₂ O-20.8 kcal / mol

These reactions are exothermic reactions, and since these reactions are continuously performed on the surface of the Cu wiring 3, Cu
The vicinity of the surface of the wiring 3 is locally heated, so that not only the growth of Cu crystal grains but also the surface diffusion proceeds near the surface of the Cu wiring 3. In this case, since the temperature rise of the entire substrate due to the exothermic reaction is several degrees Celsius, the reliability of the wiring does not decrease.

In the present invention, the conditions at the time of annealing using O ₂ gas and H ₂ gas are not limited to the above-described example.
The partial pressure ratio of ₂ and _{O 2 H 2 / O 2>} 5, 1~ the total pressure of the gas
50 Torr (1.3 × 10 ^{2 to} 65 × 10 ² Pa), temperature 250 to
It is preferable that the reaction time is 450 ° C. and the reaction time is 10 to 120 minutes.

Instead of using a mixed gas of O ₂ gas and H ₂ gas, O ₂ gas and H ₂ gas alone may be alternately introduced. In this case, the interval between the introduction of the O ₂ gas and the H ₂ gas can be about several seconds.

In the present invention, as the oxidizing gas and the reducing gas, those in which the oxidation reaction and the reduction reaction are exothermic in total and the oxidation reaction and the reduction reaction are continuously performed can be used. As the reducing gas, CO, a Knox-based gas (NO, NO ₂ ), H ₂ O, or the like can be used in addition to O _{2. As} the reducing gas, NH ₃ or the like is used in addition to H _2. be able to.

Further, as a heating device for performing the annealing,
In addition to the annealing furnace, a lamp heating device or the like may be used.
Further, in addition to using a single heating device, the heating is performed in a pretreatment chamber of the SiN film forming device, and the S
The iN film may be formed in a vacuum.

After the annealing, a SiN film is deposited to a thickness of about 50 nm as the barrier layer 4 by plasma CVD (FIG. 1 (6)). Note that an insulating film such as SiC may be formed as the barrier layer 4 instead of the SiN film.

Next, by a known dual damascene forming process, SiO ₂ films 400 to 8 are used as the second insulating film 5.
00 nm, SiN films 30 to 10 as second barrier layers 6
0 nm, SiO ₂ films 300 to 60 as third insulating film 7
0 nm is sequentially deposited (FIG. 1 (7)), and the third insulating film 7 is etched using the second barrier layer (SiN film) 6 as an etching stopper to form a wiring groove 11 (FIG. 1 (8)). ), And further etching is performed to open a connection hole 9 in the second barrier layer (SiN film) 6 and the second insulating film (SiO ₂ ) 5 (FIG. 1 (9)), and the connection hole 9 and the wiring groove are formed. 11, the Ta film 1 is formed in the same manner as when the lower Cu wiring 3 is formed.
5 and a Cu film are formed by sputtering, and C is formed by electroplating.
Then, the plug 10 and the upper Cu wiring 12 are formed (FIG. 2 (10)).

The upper Cu wiring 12 thus formed is annealed in the same manner as the lower Cu wiring 3, so that the growth of Cu crystal grains and the surface diffusion on the surface of the Cu wiring 12 proceed (FIG. 2 (11)). 2) After annealing, the surface is covered with a third barrier layer 8 (FIG. 2 (12)).

Hereinafter, a multilayer wiring can be formed by sequentially repeating the same process.

FIG. 3 is a process explanatory view of still another embodiment of the present invention.

In this embodiment, a wiring groove 14 is formed in the insulating film 2 on the substrate 1 and a Ta film 15 and a Cu film formed by sputtering are formed in the insulating film 2 on the substrate 1 as in the above-described embodiments shown in FIGS. Membrane 1
The Cu film 17 is buried by an electroplating method through the film 6 (FIG. 3A).

Next, the Ta film 15 and the Cu film deposited on the insulating film 2 in a region other than the region where the wiring groove 14 is formed by the CMP method.
The films 16 and 17 are polished and removed.
At this time, excess CMP polishing is performed to cause dishing 18 in the Cu wiring 3 in the wiring groove 14 (FIG. 3 (2)). The maximum depth of the dishing 18 is about 20 nm.

Next, the Cu wiring 3
Is annealed. By this annealing, the surface of the Cu wiring 3 on which the dishing 18 has been formed is planarized (FIG. 3C).

Next, a Ta film is deposited to a thickness of about 50 nm as the barrier layer 4 by DC magnetron sputtering (FIG. 3D). In addition, the barrier layer 4 is replaced with Ta,
It may be formed of a barrier metal such as TaN, TiN, WN and WSiN.

Next, the barrier layer 4 other than the area where the wiring groove 14 is formed is removed by CMP (FIG. 3 (5)).

Thereafter, a dual damascene forming process is performed as in the embodiment shown in FIG.
And a wiring structure having the upper Cu wiring 12 (FIG. 3).
(6)). In this wiring structure, since the barrier layer 4 having a high relative dielectric constant such as SiN is not formed between the first insulating film 2 and the second insulating film 5, the wiring capacity can be reduced. Circuit delay can be prevented. Further, the resistance of the wiring can be reduced. Note that FIG.
In (6), the connection hole 9 penetrates the barrier layer 4 and the lower layer C
Although the aspect reaching the u wiring 3 is shown, when the barrier layer 4 is formed from a barrier metal as in the present embodiment, the connection hole 9 only needs to reach the barrier layer 4 and does not necessarily penetrate the barrier layer 4. You don't have to.

The present invention can take various other modes. For example, in the above-described example, an example is shown in which a Cu wiring is formed by electroplating as a groove wiring.
The Cu wiring may be formed by another film forming method such as the CVD method, and Au, Ag, or the like may be used instead of Cu as the metal material to be embedded in the wiring groove.

[0037]

According to the present invention, in the process of manufacturing a semiconductor device, wirings and plugs are formed by a trench wiring method such as a damascene method or a dual damascene method, and when forming a multilayer wiring structure, the wirings and plugs are formed. The occurrence of voids can be prevented.

[Brief description of the drawings]

FIG. 1 is a process explanatory view of an embodiment of the present invention.

FIG. 2 is a process explanatory view of an example of the present invention.

FIG. 3 is a process explanatory view of another embodiment of the present invention.

FIG. 4 shows a C formed by a conventional dual damascene method.
It is sectional drawing of u wiring.

FIG. 5 shows a C formed by a conventional dual damascene method.
It is sectional drawing which shows the problem of u wiring.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... board | substrate, 2 ... 1st insulating film, 3 ... Cu wiring of a lower layer, 4 ... 1st barrier layer, 5 ... 2nd insulating film, 6
... second barrier layer, 7 ... third insulating film, 8 ... third barrier layer, 9 ... connection hole, 10 ... plug, 11 ... wiring groove, 12 ... upper Cu wiring, 13 ... TaN layer,
14: wiring groove, 15: Ta film, 16: Cu film, 1
7 ... Cu film by electroplating 18 ... Dishing
A ... void

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) RR06 SS11 SS15 TT02 XX00

Claims (2)

[Claims] A trench wiring or plug is formed by forming a wiring groove or a connection hole in an insulating film, forming a metal material layer so as to be embedded in the wiring groove or the connection hole, and removing the metal material layer on the insulating film. Forming a barrier layer thereon, and further forming a wiring layer on the barrier layer. In the method of manufacturing a semiconductor device, after forming a trench wiring or a plug, before forming a barrier layer, an oxidizing gas is formed. And simultaneously and alternately introducing a reducing gas and annealing. 2. The method according to claim 1, wherein a barrier metal layer is formed as the barrier layer.