JP2002134557A - Method for mounting semiconductor chip and structure for mounting semiconductor chip - Google Patents
Method for mounting semiconductor chip and structure for mounting semiconductor chipInfo
- Publication number
- JP2002134557A JP2002134557A JP2000322206A JP2000322206A JP2002134557A JP 2002134557 A JP2002134557 A JP 2002134557A JP 2000322206 A JP2000322206 A JP 2000322206A JP 2000322206 A JP2000322206 A JP 2000322206A JP 2002134557 A JP2002134557 A JP 2002134557A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- connection terminal
- bumps
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本願発明は、基板上に異方性
導電膜を介して半導体チップを実装する半導体チップの
実装方法、および半導体チップの実装構造に関する。The present invention relates to a semiconductor chip mounting method for mounting a semiconductor chip on a substrate via an anisotropic conductive film, and a semiconductor chip mounting structure.
【0002】[0002]
【従来の技術】半導体チップの実装構造には、主面の周
縁部に突出形成された複数のバンプを有する半導体チッ
プが、上記複数のバンプのそれぞれと対応する複数の接
続端子部を有する基板上に異方性導電膜を介して実装さ
れているものがある。この種の従来の半導体チップの実
装構造の一例を図10に示す。この半導体チップの実装
構造は、液晶テレビや携帯型電話機などに組み込まれて
いる液晶表示モジュール100に適用されたものであ
り、半導体チップ4を、液晶表示面となる一方のガラス
基板10上に直接実装した構造、いわゆるCOG(Chip
On Glass)方式のものである。2. Description of the Related Art In a semiconductor chip mounting structure, a semiconductor chip having a plurality of bumps protruding from a peripheral portion of a main surface is formed on a substrate having a plurality of connection terminal portions corresponding to each of the plurality of bumps. Is mounted via an anisotropic conductive film. FIG. 10 shows an example of this type of conventional semiconductor chip mounting structure. This semiconductor chip mounting structure is applied to a liquid crystal display module 100 incorporated in a liquid crystal television, a portable telephone, or the like, and the semiconductor chip 4 is directly mounted on one glass substrate 10 serving as a liquid crystal display surface. The mounted structure, so-called COG (Chip)
On Glass) method.
【0003】この液晶表示モジュール100は、重なり
合った2枚のガラス基板10,20間に液晶封止部を有
して構成される。一方の基板10は、他方の基板20の
側部から延出した部分(延出部10A)を有しており、
その表面には液晶封止部から引き出すようにして透明電
極パターンPが形成されている。なお、この従来例で
は、半導体チップ4の複数のバンプ41…のそれぞれと
対応する複数の接続端子部2…は、図12に示すよう
に、透明電極パターンPにおけるバンプ41が対面する
領域とされている。The liquid crystal display module 100 has a liquid crystal sealing portion between two overlapping glass substrates 10 and 20. One substrate 10 has a portion (extending portion 10A) extending from the side of the other substrate 20,
On its surface, a transparent electrode pattern P is formed so as to be drawn out of the liquid crystal sealing portion. In this conventional example, the plurality of connection terminal portions 2 corresponding to each of the plurality of bumps 41 of the semiconductor chip 4 are regions where the bumps 41 face the transparent electrode pattern P as shown in FIG. ing.
【0004】上記半導体チップ4は、この従来例では、
液晶駆動用のドライバICなどであり、液晶表示の高精
細化などのために、接点となるバンプ41…の個数が比
較的大とされ、これに伴ってバンプの外形サイズが比較
的小とされたものが用いられている。半導体チップ4
は、図11に示すように、各バンプ41…と各接続端子
部2…とを導通させるようにして、異方性導電膜3を介
して実装されている。[0004] The semiconductor chip 4 is, in this conventional example,
It is a driver IC for driving a liquid crystal, and the number of bumps 41 serving as contacts is relatively large, and accordingly, the outer size of the bumps is relatively small in order to increase the definition of the liquid crystal display. Is used. Semiconductor chip 4
Are mounted via the anisotropic conductive film 3 so that each bump 41... And each connection terminal portion 2.
【0005】上記半導体チップ4を実装するには、基板
10上に異方性導電膜3を形成し、その後、半導体チッ
プ4を、主面を下にして、各バンプ41…が各接続端子
部2…に対応するように基板10に向けて熱圧着する。In order to mount the semiconductor chip 4, the anisotropic conductive film 3 is formed on the substrate 10, and then the semiconductor chip 4 is placed on the main surface with each bump 41 being connected to each connection terminal portion. 2. Thermocompression bonding is performed on the substrate 10 so as to correspond to 2.
【0006】異方性導電膜3は、たとえば、樹脂の表面
にNiおよびAuをメッキして形成された導電性粒子3
2…を、エポキシ樹脂など絶縁性を有する接着母材31
中に分散混入したものである。このような異方性導電膜
3を用いれば、バンプ41…と接続端子部2…との厚み
方向に沿う隙間に、導電粒子32…を挟み込むように介
在させることによって、これらの導電粒子32を介して
半導体チップ4と接続端子部2…とを導通させることが
できる。The anisotropic conductive film 3 is made of, for example, conductive particles 3 formed by plating Ni and Au on the surface of a resin.
2 is a bonding base material 31 having an insulating property such as an epoxy resin.
It is dispersed and mixed in. When such an anisotropic conductive film 3 is used, the conductive particles 32 are interposed so as to sandwich the conductive particles 32 in a gap along the thickness direction between the bumps 41 and the connection terminal portions 2. The semiconductor chip 4 and the connection terminal portions 2.
【0007】しかしながら、半導体チップ4を基板10
に熱圧着する際には、接着母材31が溶融し、流動可能
な状態になる。このような状態で、半導体チップを押圧
すると、接着母材31および導電粒子32…は、全体と
して、半導体チップ4の中央部分からその外側に向って
流動しようとする。このとき、各バンプ41…と各接続
端子部2…との隙間では、距離が狭くなっているので導
電粒子32…の流速が大となる。また、各バンプ41…
の外形サイズが小とされているので、導電粒子32…を
この隙間に挟み込むのが極めて困難となる。したがっ
て、図12に示すように、各バンプ41…と各接続端子
部2…との隙間に十分な個数の導電粒子32…を介在さ
せることができず、各バンプ41…と各接続端子部2…
とを確実に導通させることができなかった。その結果、
半導体チップ4の接続不良が生じてしまうことがあっ
た。However, the semiconductor chip 4 is mounted on the substrate 10
When thermocompression bonding is performed, the adhesive base material 31 is melted and becomes in a flowable state. When the semiconductor chip is pressed in such a state, the adhesive base material 31 and the conductive particles 32 tend to flow from the central portion of the semiconductor chip 4 toward the outside as a whole. At this time, in the gaps between the bumps 41 and the connection terminal portions 2, the distance is narrow, so that the flow velocity of the conductive particles 32 is large. Also, each bump 41 ...
Are small in size, it is extremely difficult to sandwich the conductive particles 32 in this gap. Therefore, as shown in FIG. 12, a sufficient number of conductive particles 32 cannot be interposed in the gap between each bump 41 and each connection terminal 2. …
Cannot be reliably conducted. as a result,
In some cases, connection failure of the semiconductor chip 4 may occur.
【0008】[0008]
【発明が解決しようとする課題】本願発明は、上記した
事情のもとで考え出されたものであって、半導体チップ
のバンプと基板の接続端子部とを確実に導通させること
ができる半導体チップの接続方法、および半導体チップ
の接続構造を提供することをその課題とする。SUMMARY OF THE INVENTION The present invention has been conceived in view of the above-mentioned circumstances, and provides a semiconductor chip capable of reliably connecting a bump of a semiconductor chip to a connection terminal of a substrate. It is an object of the present invention to provide a connection method and a semiconductor chip connection structure.
【0009】[0009]
【発明の開示】上記課題を解決するため、本願発明で
は、次の技術的手段を講じている。DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention employs the following technical means.
【0010】すなわち、本願発明の第1の側面により提
供される半導体チップの接続方法は、主面の周縁部に突
出形成された複数のバンプを有する半導体チップを、上
記複数のバンプのそれぞれと対応する複数の接続端子部
を有する基板上に異方性導電膜を介して実装する方法で
あって、上記基板における、複数の接続端子部よりも外
側において、隣り合う接続端子部間の各領域と対応させ
て所定の厚みをもつ複数の凸部を形成する工程と、上記
基板上に異方性導電膜を配置する工程と、上記半導体チ
ップを、主面を下にして、各バンプが各接続端子部に対
応するように上記基板に向けて熱圧着する工程と、を含
むことことを特徴としている。That is, the method of connecting a semiconductor chip provided by the first aspect of the present invention is a method of connecting a semiconductor chip having a plurality of bumps protrudingly formed on a peripheral portion of a main surface to each of the plurality of bumps. A method of mounting via a anisotropic conductive film on a substrate having a plurality of connection terminal portions to be performed, wherein, on the substrate, outside the plurality of connection terminal portions, each region between adjacent connection terminal portions and A step of forming a plurality of convex portions having a predetermined thickness corresponding to each other; a step of arranging an anisotropic conductive film on the substrate; Thermocompression bonding to the substrate so as to correspond to the terminal portion.
【0011】具体的には、上記基板は、ガラス基板であ
り、上記接続端子部は、透明電極である。More specifically, the substrate is a glass substrate, and the connection terminal is a transparent electrode.
【0012】半導体チップを熱圧着する際に、異方性導
電膜の接着母材が溶融し、流動可能な状態となる。この
ような状態で半導体チップが押圧されると、接着母材お
よび導電粒子は、全体として、半導体チップの中央部分
からその外側へ流動しようとするが、本願発明の第1の
側面では、上記基板には、上記の複数の凸部が形成され
るので、接着母材および導電粒子は、半導体チップの中
央部分から各凸部の間に向って流動しようとする。これ
らの凸部は、複数の接続端子部よりも外側において、隣
り合う接続端子部間の各領域と対応させて形成されるの
で、導電粒子の多くが、各接続端子部上を通るようにな
る。したがって、各バンプと各接続端子部との隙間に挟
み込まれる導電粒子の個数を増加させることができる。
その結果、各バンプと各接続端子部とを確実に導通させ
ることができ、半導体チップの接続不良を防止すること
が可能となる。When the semiconductor chip is thermocompression-bonded, the adhesive base material of the anisotropic conductive film is melted and becomes flowable. When the semiconductor chip is pressed in such a state, the adhesive base material and the conductive particles as a whole tend to flow from the central portion of the semiconductor chip to the outside, but according to the first aspect of the present invention, the substrate Since the plurality of convex portions are formed in the semiconductor chip, the adhesive base material and the conductive particles tend to flow from the central portion of the semiconductor chip to between the convex portions. Since these convex portions are formed outside the plurality of connection terminal portions and in correspondence with each region between adjacent connection terminal portions, most of the conductive particles pass over each connection terminal portion. . Therefore, it is possible to increase the number of conductive particles sandwiched in the gap between each bump and each connection terminal portion.
As a result, each of the bumps and each of the connection terminal portions can be reliably connected to each other, and a connection failure of the semiconductor chip can be prevented.
【0013】好ましい実施の形態においては、上記凸部
は、上記基板の表面からの高さが異方性導電膜に含まれ
ている導電粒子の粒径よりも大、かつ上記半導体チップ
が上記基板に実装されたときの上記半導体チップと上記
基板との間の距離よりも小となるように形成される。In a preferred embodiment, the height of the projection from the surface of the substrate is larger than the particle diameter of conductive particles contained in the anisotropic conductive film, and the semiconductor chip is formed of the substrate. It is formed to be smaller than the distance between the semiconductor chip and the substrate when mounted on the substrate.
【0014】このような構成によれば、上記凸部の上面
と半導体チップの主面との間に隙間が生じる。これによ
り、この隙間からも溶融した異方性導電膜を流出させる
ことができる。したがって、半導体チップを基板に実装
した際に、基板と半導体チップとの間の距離が必要以上
に大きくなるのを防止することができる。なお、凸部
は、基板の表面からの高さが導電粒子の粒径よりも大と
されているので、導電粒子が凸部を乗り越えて流出して
しまうのを抑制することができ、各バンプと各接続端子
部との隙間に十分な個数の導電粒子を介在させる効果を
あまり損なうことがない。According to such a configuration, a gap is generated between the upper surface of the projection and the main surface of the semiconductor chip. As a result, the molten anisotropic conductive film can flow out of the gap. Therefore, it is possible to prevent the distance between the substrate and the semiconductor chip from becoming unnecessarily large when the semiconductor chip is mounted on the substrate. In addition, since the height of the protrusion from the surface of the substrate is larger than the particle diameter of the conductive particles, it is possible to suppress the conductive particles from flowing over the protrusion and flowing out. The effect of having a sufficient number of conductive particles interposed in the gaps between the connection terminals and the connection terminals is not significantly impaired.
【0015】好ましい実施の形態においてはまた、上記
凸部は、感光性樹脂を用いてフォトリソグラフィー法に
より形成される。したがって、比較的サイズが小さい凸
部を多量に形成するのが容易となる。In a preferred embodiment, the projection is formed by a photolithography method using a photosensitive resin. Therefore, it is easy to form a large number of relatively small convex portions.
【0016】本願発明の第2の側面により提供される半
導体チップの接続構造は、主面の周縁部に突出形成され
た複数のバンプを有する半導体チップが、上記複数のバ
ンプのそれぞれと対応する複数の接続端子部を有する基
板上に異方性導電膜を介して実装される構造であって、
上記基板における、複数の接続端子部よりも外側におい
て、隣り合う接続端子部間の各領域と対応させて所定の
厚みをもつ複数の凸部が形成されていることを特徴とし
ている。According to a second aspect of the present invention, there is provided a connection structure for a semiconductor chip, wherein a semiconductor chip having a plurality of bumps protrudingly formed on a peripheral portion of a main surface is provided with a plurality of bumps corresponding to each of the plurality of bumps. A structure mounted on a substrate having a connection terminal portion through an anisotropic conductive film,
A plurality of projections having a predetermined thickness are formed outside the plurality of connection terminal portions on the substrate so as to correspond to respective regions between adjacent connection terminal portions.
【0017】本願発明の第2の側面は、本願発明の第1
の側面により提供される半導体チップの実装方法により
製造される半導体チップの実装構造である。したがっ
て、本願発明の第1の側面に係る半導体チップの実装方
法と同様の作用効果を奏することができる。The second aspect of the present invention is the first aspect of the present invention.
And a semiconductor chip mounting structure manufactured by the semiconductor chip mounting method provided by the aspect of the present invention. Therefore, the same operation and effect as those of the semiconductor chip mounting method according to the first aspect of the present invention can be obtained.
【0018】本願発明のその他の特徴および利点につい
ては、以下に行う発明の実施の形態の説明から、より明
らかになるであろう。Other features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention.
【0019】[0019]
【発明の実施の形態】以下、本願発明の好ましい実施の
形態について、図面を参照して具体的に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.
【0020】図1は、本願発明に係る半導体チップの実
装構造の一例を示す概略斜視図、図2は、図1のII-II
線に沿う断面図、図3は、図2における凸部の配置を示
す概略斜視図である。図4ないし図7は、本願発明に係
る半導体チップの実装方法を説明するための断面図であ
る。図8は、図2における導電粒子の分布状況を示す平
面図である。なお、これらの図において、従来例を示す
図10ないし図12に表された部材、部分等と同等のも
のにはそれぞれ同一の符号を付してある。FIG. 1 is a schematic perspective view showing an example of a semiconductor chip mounting structure according to the present invention, and FIG. 2 is a sectional view taken along line II-II of FIG.
3 is a schematic perspective view showing the arrangement of the protrusions in FIG. 2. 4 to 7 are cross-sectional views illustrating a method for mounting a semiconductor chip according to the present invention. FIG. 8 is a plan view showing the distribution of the conductive particles in FIG. In these figures, the same reference numerals are given to members and parts equivalent to those shown in FIGS. 10 to 12 showing a conventional example.
【0021】図1および図2に表われているように、本
願発明に係る半導体チップの実装構造は、主面4Aの周
縁部に突出形成された複数のバンプ41…を有する半導
体チップ4が、上記複数のバンプ41…のそれぞれと対
応する複数の接続端子部2…を有する基板10上に異方
性導電膜3を介して実装された構造であり、本実施形態
では、液晶表示モジュールAに適用されている。As shown in FIGS. 1 and 2, the semiconductor chip mounting structure according to the present invention comprises a semiconductor chip 4 having a plurality of bumps 41 projecting from a peripheral portion of a main surface 4A. In this embodiment, the liquid crystal display module A is mounted on a substrate 10 having a plurality of connection terminals 2 corresponding to each of the plurality of bumps 41 via an anisotropic conductive film 3. Have been applied.
【0022】上記半導体チップ4は、本実施形態では、
液晶駆動用のドライバICであり、液晶表示の高精細化
などのために、接点となるバンプ41…の個数が比較的
大とされ、これに伴ってバンプ41…の外形サイズが比
較的小とされたものが用いられている。これらのバンプ
41…が突出形成されている主面4Aは、平坦とされて
いる。また、各バンプ41…は、平坦な矩形状の底面を
有している。In the present embodiment, the semiconductor chip 4 is
This is a driver IC for driving a liquid crystal. The number of bumps 41 serving as contacts is relatively large in order to increase the definition of a liquid crystal display, and accordingly, the outer size of the bumps 41 is relatively small. What was done is used. The main surface 4A on which the bumps 41 are formed so as to protrude is flat. Each of the bumps 41 has a flat rectangular bottom surface.
【0023】上記基板10は、本実施形態では、ガラス
基板であり、図1に示すように、ガラス基板20ととも
に液晶表示モジュールAの液晶表示面を構成している。
この基板10には、他方の基板20の側部20aからは
み出るようにして、半導体チップ4実装用の延出部10
Aが形成されている。延出部10Aの表面には、たとえ
ば、ITO(Indium Tin Oxide)を蒸着するなどして、
透明電極パターンPが形成されている。なお、本実施形
態では、上記接続端子部2…は、図3に示すように、透
明電極パターンPにおける上記バンプ41が対面する領
域とされている。In the present embodiment, the substrate 10 is a glass substrate, and constitutes a liquid crystal display surface of the liquid crystal display module A together with the glass substrate 20, as shown in FIG.
The extension 10 for mounting the semiconductor chip 4 is provided on the substrate 10 so as to protrude from the side portion 20 a of the other substrate 20.
A is formed. On the surface of the extension 10A, for example, ITO (Indium Tin Oxide) is deposited,
A transparent electrode pattern P is formed. In the present embodiment, the connection terminal portions 2 are regions in the transparent electrode pattern P where the bumps 41 face, as shown in FIG.
【0024】また、上記基板10上には、複数の接続端
子部2…よりも外側において、隣り合う接続端子部2…
間の各領域と対応させて所定の厚みをもつ複数の凸部5
…が形成されている。本実施形態では、各凸部5…は、
図3に示すように、半導体チップ4を実装した際に、各
バンプ41…の外側となるように配置されており、隣り
合う接続端子部2…間に跨るようにして形成されてい
る。各凸部5…は、図2に示すように、上記基板10の
表面からの高さが異方性導電膜3に含まれている導電粒
子32の粒径よりも大、かつ半導体チップ4が基板10
に実装されたときの半導体チップ4と基板10との間の
距離hよりも小となるように形成される。Further, on the substrate 10, adjacent connection terminal portions 2... Outside the plurality of connection terminal portions 2.
A plurality of convex portions 5 having a predetermined thickness corresponding to each region between
... are formed. In the present embodiment, each of the projections 5.
As shown in FIG. 3, when the semiconductor chip 4 is mounted, it is arranged so as to be outside each of the bumps 41... And is formed so as to straddle between the adjacent connection terminal portions 2. As shown in FIG. 2, each of the protrusions 5 has a height from the surface of the substrate 10 larger than the particle size of the conductive particles 32 included in the anisotropic conductive film 3 and the semiconductor chip 4 Substrate 10
Is formed so as to be smaller than the distance h between the semiconductor chip 4 and the substrate 10 when mounted on the substrate.
【0025】上記異方性導電膜3は、絶縁性を有する接
着母材31内に導電粒子32…を分散混入させたもので
ある。接着母材31としては、たとえばエポキシ樹脂な
どの熱硬化性樹脂から形成され、熱硬化させる前の段階
においてフィルム状(固体状)のものや粘液状のものが
あり、本実施形態では、フィルム状のものが用いられて
いる。各導電粒子32…としては、本実施形態では、粒
径が約5μm程度のボール状とされており、たとえば、
樹脂の表面にNiおよびAuをメッキすることによって
形成される。このような異方性導電膜3は、半導体チッ
プ4を実装する際、加圧・加熱などによって接着母材3
1が軟化させられ、その後、冷却・固化されることによ
って、半導体チップ4の主面4Aと基板10の表面とを
接合する。このとき、バンプ41…と接続端子部2…と
の間のように異方性導電膜3の厚みが比較的小となる部
位では、図2に示すように、導電粒子32…がバンプ4
1…と接続端子部2…との間に挟み込まれるように介在
し、半導体チップ4と接続端子部2…とが導通される。
一方、異方性導電膜3の厚みが比較的大となる部位で
は、各導電粒子32…が分散したままの状態となり、絶
縁性が維持される。The anisotropic conductive film 3 is obtained by dispersing and mixing conductive particles 32 in an adhesive base material 31 having an insulating property. The adhesive base material 31 is formed of, for example, a thermosetting resin such as an epoxy resin, and may be in the form of a film (solid) or a viscous liquid before being thermally cured. Is used. In the present embodiment, each of the conductive particles 32 is in the form of a ball having a particle size of about 5 μm.
It is formed by plating Ni and Au on the surface of the resin. When the semiconductor chip 4 is mounted, such an anisotropic conductive film 3 is bonded to the adhesive base material 3 by pressing and heating.
1 is softened, and then cooled and solidified, thereby joining the main surface 4A of the semiconductor chip 4 and the surface of the substrate 10. At this time, in the portion where the thickness of the anisotropic conductive film 3 becomes relatively small, such as between the bumps 41 and the connection terminal portions 2, as shown in FIG.
1 and the connection terminal portions 2 are interposed so as to be sandwiched between the semiconductor chip 4 and the connection terminal portions 2.
On the other hand, in a portion where the thickness of the anisotropic conductive film 3 is relatively large, the conductive particles 32 are kept in a dispersed state, and the insulating property is maintained.
【0026】以下、半導体チップの実装方法を順を追っ
て説明する。Hereinafter, a method for mounting a semiconductor chip will be described step by step.
【0027】上記半導体チップ4を上記基板10上に実
装するには、まず、図4に示すように、基板10におけ
る、複数の接続端子部2…よりも外側において、隣り合
う接続端子部2…間の各領域と対応させて所定の厚みを
もつ複数の凸部5…を形成する。In order to mount the semiconductor chip 4 on the substrate 10, first, as shown in FIG. 4, adjacent connection terminal portions 2 on the substrate 10 outside the plurality of connection terminal portions 2. A plurality of convex portions 5 having a predetermined thickness are formed in correspondence with the respective regions therebetween.
【0028】上記各凸部5…は、感光性樹脂を用いてフ
ォトリソグラフィー法により形成される。より詳細に
は、まず、図7(a)に示すように、上記接続端子部2
…(および透明電極パターンP)が形成された基板10
の表面全体に感光性樹脂5aを塗布する。この工程にお
いて、感光性樹脂5aは、凸部5の所定の厚み、すなわ
ち上記基板10の表面からの高さが上記導電粒子32の
粒径よりも大、かつ半導体チップ4が基板10に実装さ
れたときの半導体チップ4と基板10との間の距離hよ
りも小となるように、塗布される。また、感光性樹脂5
aとして、本実施形態では、露光された部分が現像液に
不溶化するネガ型の感光性ポリイミドが使用されてい
る。次に、各凸部5…の形状通りに露光を行う。この工
程において、本実施形態では、各凸部5…に対応する部
位に所定形状の開口部50aを有する露光用マスク50
が用いられる。この露光用マスク50を、図7(b)に
示すように、上記感光性樹脂5aに密着させ、その上か
ら紫外光などを照射する。その後、現像液に浸すなどし
て感光性樹脂の不要部分を除去することにより、各凸部
5…が形成される。Each of the convex portions 5 is formed by a photolithography method using a photosensitive resin. More specifically, first, as shown in FIG.
... (and the transparent electrode pattern P) formed on the substrate 10
The photosensitive resin 5a is applied to the entire surface of the substrate. In this step, the photosensitive resin 5a has a predetermined thickness of the convex portion 5, that is, a height from the surface of the substrate 10 larger than a particle size of the conductive particles 32, and the semiconductor chip 4 is mounted on the substrate 10. The coating is performed so as to be smaller than the distance h between the semiconductor chip 4 and the substrate 10 at the time of the contact. In addition, photosensitive resin 5
In the present embodiment, a negative photosensitive polyimide in which the exposed portion is insoluble in the developer is used as a. Next, exposure is performed according to the shape of each convex portion 5. In this step, in the present embodiment, in this embodiment, the exposure mask 50 having an opening 50a of a predetermined shape at a portion corresponding to each of the protrusions 5.
Is used. As shown in FIG. 7B, the exposure mask 50 is brought into close contact with the photosensitive resin 5a, and ultraviolet light or the like is irradiated thereon. Thereafter, unnecessary portions of the photosensitive resin are removed by immersion in a developer or the like, so that the respective convex portions 5 are formed.
【0029】半導体チップ4が液晶駆動用のドライブI
Cである場合には、液晶表示の高精細化などのために、
バンプ数が比較的大となり、これに伴って隣り合う接続
端子部2…間の距離を比較的小(数十μm程度)としな
ければならない。したがって、比較的サイズが小さい凸
部5…を多量に形成しなければならないが、上述したよ
うに、感光性樹脂を用いてフォトリソグラフィー法によ
り各凸部5…を形成することによって、凸部の形成を容
易にすることができる。The semiconductor chip 4 is a drive I for driving a liquid crystal.
In the case of C, in order to increase the definition of the liquid crystal display,
The number of bumps becomes relatively large, and accordingly, the distance between adjacent connection terminal parts 2 must be made relatively small (about several tens of μm). Therefore, it is necessary to form a large amount of the protrusions 5 having a relatively small size. As described above, by forming each of the protrusions 5 by the photolithography method using the photosensitive resin, the protrusions 5 are formed. Formation can be facilitated.
【0030】次いで、図5に示すように、上記基板10
上に異方性導電膜3を配置する。異方性導電膜3は、本
実施形態では、上記接着母材31がフィルム状に形成さ
れており、基板10上における上記接続端子部2…を含
む所定の領域を覆うようなサイズにされたものが、基板
10上に載置される。なお、異方性導電膜3は、基板1
0上において不用意に位置ずれしないように、基板10
表面に仮固定されることが好ましい。Next, as shown in FIG.
An anisotropic conductive film 3 is disposed thereon. In the present embodiment, the anisotropic conductive film 3 is formed such that the adhesive base material 31 is formed in a film shape and is sized to cover a predetermined region including the connection terminal portions 2 on the substrate 10. The object is placed on the substrate 10. Note that the anisotropic conductive film 3 is
Substrate 10 so as not to be inadvertently displaced on
Preferably, it is temporarily fixed to the surface.
【0031】次いで、上記半導体チップ4を、主面4A
を下にして、各バンプ41…が各接続端子部2…に対応
するように上記基板10に向けて熱圧着する。本実施形
態では、この工程において、予め半導体チップ4を異方
性導電膜3上に吸着コレットなどにより載置しておき、
図6に示すように、半導体チップ4の上から発熱ヘッド
9を所定の圧力で基板10に押しつける。このとき、上
記導電粒子32…は、各バンプ41…と各接続端子部2
…との間で挟み込まれた状態となり、半導体チップ4と
接続端子部2…とを導通させることができる。その後、
異方性導電膜3が冷却・固化し、半導体チップ4と基板
10とが接合される。Next, the semiconductor chip 4 is attached to the main surface 4A.
Is thermocompression-bonded to the substrate 10 so that the bumps 41 correspond to the connection terminals 2. In the present embodiment, in this step, the semiconductor chip 4 is previously placed on the anisotropic conductive film 3 by using an adsorption collet or the like.
As shown in FIG. 6, the heating head 9 is pressed against the substrate 10 from above the semiconductor chip 4 with a predetermined pressure. At this time, the conductive particles 32 are connected to the bumps 41 and the connection terminals 2.
, So that the semiconductor chip 4 and the connection terminal portions 2 can be electrically connected. afterwards,
The anisotropic conductive film 3 is cooled and solidified, and the semiconductor chip 4 and the substrate 10 are joined.
【0032】次に、上述した半導体チップの実装方法の
作用について簡単に説明する。Next, the operation of the above-described semiconductor chip mounting method will be briefly described.
【0033】半導体チップ4を熱圧着する際に、異方性
導電膜3の接着母材31が発熱ヘッド9の熱により溶融
し、流動可能な状態となる。このような状態で半導体チ
ップ4が押圧されると、接着母材31および導電粒子3
2…は、全体として、半導体チップ4の中央部分からそ
の外側へ向って流動しようとする。従来では、導電粒子
32…をこの隙間に挟み込むのが極めて困難となり、十
分な個数の導電粒子32…をこの隙間に介在させること
ができなかった。When the semiconductor chip 4 is thermocompression-bonded, the adhesive base material 31 of the anisotropic conductive film 3 is melted by the heat of the heating head 9 and becomes in a flowable state. When the semiconductor chip 4 is pressed in such a state, the adhesive base material 31 and the conductive particles 3 are pressed.
2 tend to flow from the central portion of the semiconductor chip 4 toward the outside thereof. In the related art, it is extremely difficult to sandwich the conductive particles 32 in this gap, and a sufficient number of the conductive particles 32 cannot be interposed in this gap.
【0034】しかし、上述した半導体チップの実装方法
によれば、上記基板10上には、所定の厚みをもつ複数
の凸部5…が形成されるので、導電粒子32…は、全体
として、半導体チップ4の中央部分から各凸部5…の間
に向って流動しようとする。これらの凸部5…は、複数
の接続端子部2…よりも外側において、隣り合う接続端
子部2…間の各領域と対応させて形成されるので、導電
粒子32…の多くが、各接続端子部2…上を通るように
なる。したがって、図8に示すように、各バンプ41…
と各接続端子部2…との隙間に挟み込まれる導電粒子3
2…の個数を増加させることができる。その結果、各バ
ンプ41…と各接続端子部2…とを確実に導通させるこ
とができ、半導体チップの接続不良を防止することが可
能となる。However, according to the above-described method for mounting a semiconductor chip, a plurality of protrusions 5 having a predetermined thickness are formed on the substrate 10, so that the conductive particles 32 It tends to flow from the central portion of the chip 4 to between the convex portions 5. These convex portions 5 are formed outside the plurality of connection terminal portions 2 so as to correspond to the respective regions between the adjacent connection terminal portions 2. Therefore, most of the conductive particles 32. Terminal part 2 ... passes over. Therefore, as shown in FIG.
Conductive particles 3 sandwiched in the gaps between
2 can be increased. As a result, the respective bumps 41 and the respective connection terminal portions 2 can be reliably connected to each other, and a connection failure of the semiconductor chip can be prevented.
【0035】また、各凸部5…は、上述したように、上
記基板10の表面からの高さが導電粒子32の粒径より
も大、かつ半導体チップ4が基板10に実装されたとき
の半導体チップ4と基板10との間の距離hよりも小と
なるように形成されているので、上記凸部5…の上面と
半導体チップの主面4Aとの間に隙間が生じる。これに
より、この隙間からも溶融した異方性導電膜3を流出さ
せることができる。したがって、半導体チップ4を基板
10に実装した際に、基板10と半導体チップ4との間
の距離が必要以上に大きくなるのを防止することができ
る。なお、各凸部5…は、上述したように、基板10の
表面からの高さが導電粒子32の粒径よりも大とされて
いるので、導電粒子32…が凸部5…を乗り越えて流出
してしまうのを抑制することができ、各バンプ41…と
各接続端子部2…との隙間に介在する導電粒子32…を
増加させる効果をあまり損なうことがない。As described above, each of the projections 5 is formed when the height from the surface of the substrate 10 is larger than the particle size of the conductive particles 32 and the semiconductor chip 4 is mounted on the substrate 10. Since it is formed to be smaller than the distance h between the semiconductor chip 4 and the substrate 10, a gap is generated between the upper surface of the protrusions 5 and the main surface 4A of the semiconductor chip. Thereby, the melted anisotropic conductive film 3 can flow out of the gap. Therefore, when the semiconductor chip 4 is mounted on the substrate 10, it is possible to prevent the distance between the substrate 10 and the semiconductor chip 4 from becoming unnecessarily large. As described above, since the height of each of the protrusions 5 from the surface of the substrate 10 is larger than the particle diameter of the conductive particles 32, the conductive particles 32 pass over the protrusions 5. Outflow can be suppressed, and the effect of increasing the number of conductive particles 32 interposed in the gap between each bump 41 and each connection terminal portion 2 is not significantly impaired.
【0036】なお、図9は、上述した半導体チップの実
装構造における、上記各接続端子部2…の面積Sと、各
バンプ41…と各接続端子部2…との隙間に介在する導
電粒子32…の個数Nとの関係を、本願発明者が行った
実験の結果に基づいて示すグラフである。なお、この実
験では、半導体チップ4が基板10に実装されたときに
おける半導体チップ4と基板10との間の距離を17μ
m、凸部5の高さを10μm、接続端子部2の長さを1
00μm、接続端子部2…間距離:凸部5の接続端子部
2…間方向の長さを1:1、とし、上記面積Sを200
0、3000、4000、5000μm2としたとき
の、それぞれについて上記導電粒子個数Nをカウントし
た。また、図9のグラフ中では、上記凸部5…が形成さ
れていない半導体チップの実装構造(従来例)につい
て、一点鎖線で示している。FIG. 9 shows the area S of the connection terminals 2 and the conductive particles 32 interposed in the gaps between the bumps 41 and the connection terminals 2 in the semiconductor chip mounting structure described above. Is a graph showing the relationship with the number N of ... based on the results of experiments conducted by the inventor of the present application. In this experiment, the distance between the semiconductor chip 4 and the substrate 10 when the semiconductor chip 4 was mounted on the substrate 10 was 17 μm.
m, the height of the projection 5 is 10 μm, and the length of the connection terminal 2 is 1
00 μm, the distance between the connection terminal portions 2...: The length between the connection terminal portions 2.
The number N of the conductive particles was counted for each of 0, 3000, 4000, and 5000 μm 2 . Further, in the graph of FIG. 9, the mounting structure (conventional example) of the semiconductor chip on which the above-mentioned protrusions 5 are not formed is indicated by a chain line.
【0037】このグラフより、本実施形態の半導体チッ
プの実装方法では、上記各接続端子部2…の単位面積当
りに対する、各バンプ41…と各接続端子部2…との隙
間に介在する導電粒子32…の個数が、従来例のものと
比較して約2倍程度となっているのがわかる。このよう
に、上記凸部5…を形成することにより、各バンプ41
…と各接続端子部2…との隙間に介在する導電粒子32
…を大幅に増加させることができるのが確認された。According to this graph, in the semiconductor chip mounting method of the present embodiment, the conductive particles interposed in the gaps between each bump 41 and each connection terminal portion 2 per unit area of each connection terminal portion 2. It can be seen that the number of 32... Is about twice that of the conventional example. In this manner, by forming the above-mentioned protrusions 5.
And the conductive particles 32 interposed in the gaps between the connecting terminals 2.
… Can be greatly increased.
【0038】もちろん、本願発明の範囲は、上述した実
施形態に限定されるものではない。たとえば、上記実施
形態は、液晶表示モジュールに適用したものであるが、
本願発明は、液晶表示モジュールに限らず、その他の装
置に適用できるのはいうまでもない。Of course, the scope of the present invention is not limited to the above embodiment. For example, the above embodiment is applied to a liquid crystal display module,
Needless to say, the present invention is applicable not only to the liquid crystal display module but also to other devices.
【図1】本願発明に係る半導体チップの実装構造の一例
を示す概略斜視図である。FIG. 1 is a schematic perspective view showing an example of a mounting structure of a semiconductor chip according to the present invention.
【図2】図1のII-II線に沿う断面図である。FIG. 2 is a sectional view taken along the line II-II in FIG.
【図3】図2における凸部の配置を示す概略斜視図であ
る。FIG. 3 is a schematic perspective view showing an arrangement of convex portions in FIG.
【図4】本願発明に係る半導体チップの実装方法を説明
するための断面図である。FIG. 4 is a cross-sectional view for explaining a semiconductor chip mounting method according to the present invention.
【図5】本願発明に係る半導体チップの実装方法を説明
するための断面図である。FIG. 5 is a cross-sectional view for explaining a semiconductor chip mounting method according to the present invention.
【図6】本願発明に係る半導体チップの実装方法を説明
するための断面図である。FIG. 6 is a cross-sectional view for explaining a semiconductor chip mounting method according to the present invention.
【図7】本願発明に係る半導体チップの実装方法を説明
するための断面図である。FIG. 7 is a cross-sectional view for explaining a semiconductor chip mounting method according to the present invention.
【図8】図2における導電粒子の分布状況を示す平面図
である。FIG. 8 is a plan view showing a distribution state of conductive particles in FIG.
【図9】本願発明に係る半導体チップの実装方法の実施
形態に係る実験結果を示すグラフである。FIG. 9 is a graph showing experimental results according to the embodiment of the semiconductor chip mounting method according to the present invention.
【図10】従来の半導体チップの実装構造の一例を示す
概略斜視図である。FIG. 10 is a schematic perspective view showing an example of a conventional mounting structure of a semiconductor chip.
【図11】図10のXI-XI線に沿う断面図である。FIG. 11 is a sectional view taken along the line XI-XI in FIG. 10;
【図12】図11における導電粒子の分布状況を示す平
面図である。FIG. 12 is a plan view showing a distribution state of conductive particles in FIG.
2 接続端子部 3 異方性導電膜 4 半導体チップ 5 凸部 4A 主面 10 基板 32 導電粒子 41 バンプ 2 Connection terminal part 3 Anisotropic conductive film 4 Semiconductor chip 5 Convex part 4A Main surface 10 Substrate 32 Conductive particles 41 Bump
Claims (5)
ンプを有する半導体チップを、上記複数のバンプのそれ
ぞれと対応する複数の接続端子部を有する基板上に異方
性導電膜を介して実装する方法であって、 上記基板における、複数の接続端子部よりも外側におい
て、隣り合う接続端子部間の各領域と対応させて所定の
厚みをもつ複数の凸部を形成する工程と、 上記基板上に異方性導電膜を配置する工程と、 上記半導体チップを、主面を下にして、各バンプが各接
続端子部に対応するように上記基板に向けて熱圧着する
工程と、 を含むことを特徴とする、半導体チップの実装方法。1. A semiconductor chip having a plurality of bumps protrudingly formed at a peripheral portion of a main surface is provided on a substrate having a plurality of connection terminals corresponding to each of the plurality of bumps via an anisotropic conductive film. Forming a plurality of convex portions having a predetermined thickness corresponding to each region between adjacent connection terminal portions, outside the plurality of connection terminal portions in the substrate, A step of disposing an anisotropic conductive film on the substrate; and a step of thermocompression-bonding the semiconductor chip toward the substrate such that each bump corresponds to each connection terminal, with the main surface facing down. A method of mounting a semiconductor chip, comprising:
が異方性導電膜に含まれている導電粒子の粒径よりも
大、かつ上記半導体チップが上記基板に実装されたとき
の上記半導体チップと上記基板との間の距離よりも小と
なるように形成される、請求項1に記載の半導体チップ
の実装方法。2. The method according to claim 1, wherein the height of the projection from the surface of the substrate is larger than the particle size of conductive particles contained in the anisotropic conductive film, and the semiconductor chip is mounted on the substrate. The method of mounting a semiconductor chip according to claim 1, wherein the semiconductor chip is formed to be smaller than a distance between the semiconductor chip and the substrate.
続端子部は、透明電極である、請求項1または2に記載
の半導体チップの実装方法。3. The semiconductor chip mounting method according to claim 1, wherein the substrate is a glass substrate, and the connection terminal portion is a transparent electrode.
リソグラフィー法により形成される、請求項3に記載の
半導体チップの実装方法。4. The method according to claim 3, wherein the projection is formed by a photolithography method using a photosensitive resin.
ンプを有する半導体チップが、上記複数のバンプのそれ
ぞれと対応する複数の接続端子部を有する基板上に異方
性導電膜を介して実装される構造であって、 上記基板における、複数の接続端子部よりも外側におい
て、隣り合う接続端子部間の各領域と対応させて所定の
厚みをもつ複数の凸部が形成されていることを特徴とす
る、半導体チップの実装構造。5. A semiconductor chip having a plurality of bumps protrudingly formed on a peripheral portion of a main surface is provided on a substrate having a plurality of connection terminal portions corresponding to each of the plurality of bumps via an anisotropic conductive film. A plurality of protrusions having a predetermined thickness are formed outside the plurality of connection terminal portions on the substrate in correspondence with each region between adjacent connection terminal portions. A mounting structure of a semiconductor chip, characterized in that:
Priority Applications (1)
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JP2000322206A JP2002134557A (en) | 2000-10-23 | 2000-10-23 | Method for mounting semiconductor chip and structure for mounting semiconductor chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000322206A JP2002134557A (en) | 2000-10-23 | 2000-10-23 | Method for mounting semiconductor chip and structure for mounting semiconductor chip |
Publications (1)
Publication Number | Publication Date |
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JP2002134557A true JP2002134557A (en) | 2002-05-10 |
Family
ID=18800120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000322206A Pending JP2002134557A (en) | 2000-10-23 | 2000-10-23 | Method for mounting semiconductor chip and structure for mounting semiconductor chip |
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Country | Link |
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JP (1) | JP2002134557A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100943731B1 (en) | 2003-06-28 | 2010-02-23 | 엘지디스플레이 주식회사 | Chip on glass type Display Device |
JP2014086616A (en) * | 2012-10-25 | 2014-05-12 | Denso Corp | Electronic device and manufacturing method therefor |
CN110265373A (en) * | 2019-04-29 | 2019-09-20 | 京东方科技集团股份有限公司 | The binding method of display device and driving chip |
KR102138667B1 (en) * | 2019-05-14 | 2020-07-28 | (주)비티비엘 | Smart card with improved battery terminal-soldering sites |
-
2000
- 2000-10-23 JP JP2000322206A patent/JP2002134557A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100943731B1 (en) | 2003-06-28 | 2010-02-23 | 엘지디스플레이 주식회사 | Chip on glass type Display Device |
JP2014086616A (en) * | 2012-10-25 | 2014-05-12 | Denso Corp | Electronic device and manufacturing method therefor |
CN110265373A (en) * | 2019-04-29 | 2019-09-20 | 京东方科技集团股份有限公司 | The binding method of display device and driving chip |
KR102138667B1 (en) * | 2019-05-14 | 2020-07-28 | (주)비티비엘 | Smart card with improved battery terminal-soldering sites |
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