JP2002009196A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JP2002009196A JP2002009196A JP2000185426A JP2000185426A JP2002009196A JP 2002009196 A JP2002009196 A JP 2002009196A JP 2000185426 A JP2000185426 A JP 2000185426A JP 2000185426 A JP2000185426 A JP 2000185426A JP 2002009196 A JP2002009196 A JP 2002009196A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- semiconductor device
- resist pattern
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 229920005989 resin Polymers 0.000 claims abstract description 57
- 239000011347 resin Substances 0.000 claims abstract description 57
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 32
- 238000007789 sealing Methods 0.000 claims description 25
- 238000004070 electrodeposition Methods 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000565 sealant Substances 0.000 abstract 1
- 238000005323 electroforming Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 230000000669 biting effect Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 3
- 239000002659 electrodeposit Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- QXZUUHYBWMWJHK-UHFFFAOYSA-N [Co].[Ni] Chemical compound [Co].[Ni] QXZUUHYBWMWJHK-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置に関し、
特に、小型・薄型化を図れ、低価格化を可能とする樹脂
封止型の半導体装置の製造方法に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a method for manufacturing a resin-encapsulated semiconductor device which can be reduced in size and thickness and can be reduced in cost.
【0002】[0002]
【従来の技術】従来の半導体装置、特に、リードレス表
面実装方式の樹脂封止された半導体装置については、図
10に示すごとく、通常ガラスエポキシやセラミック等
のプリント基板51の一面に搭載された半導体素子52
と上記プリント基板51の当該一面に形成された複数の
接続用電極53とを導電性のワイヤ54にて電気的に接
続するとともに、プリント基板51裏面に上記各接続用
電極53と対向して形成される電極層55と上記各接続
用電極53とを各々スルーホール56に配した導電体5
7を通して電気的に接続する形態を呈しており、半導体
素子52周りをエポキシ樹脂58等により樹脂封止して
構成されている。2. Description of the Related Art As shown in FIG. 10, a conventional semiconductor device, in particular, a semiconductor device sealed with a resin of a leadless surface mounting method is usually mounted on one surface of a printed board 51 made of glass epoxy or ceramic. Semiconductor element 52
And the plurality of connection electrodes 53 formed on the one surface of the printed board 51 are electrically connected by conductive wires 54 and formed on the back surface of the printed board 51 so as to face the connection electrodes 53. Conductor 5 in which the electrode layer 55 to be formed and the connection electrodes 53 are disposed in the through holes 56, respectively.
The semiconductor device 52 is electrically sealed through an epoxy resin 58 or the like.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、この種
従来の半導体装置にあっては、その製造工程において、
プリント基板51一面側の接続用電極53と裏面側の電
極層55とをプリント基板51上で正確に位置合わせし
た状態で形成する必要がある。また各位置合わせして形
成した電極53と電極層55とがスルーホール56によ
り位置ズレなく、確実に導通されている必要もあり、製
造時の精度が要求されるものである。これら精度の要求
は、プリント基板51へのスルーホール56形成や導電
体57の印刷のための製造工数のアップと合わせて、製
造コスト低減のためのネックとなるとともに、製造時に
プリント基板51上に多数隣接させて配置する半導体素
子間にスルーホール形成のための領域が必要となり、一
枚のプリント基板上に配設して形成できる半導体装置の
個数も制限されてしまうものである。However, in this kind of conventional semiconductor device, in the manufacturing process,
It is necessary to form the connection electrode 53 on one side of the printed board 51 and the electrode layer 55 on the back side in a state where they are accurately aligned on the printed board 51. In addition, it is necessary that the electrode 53 and the electrode layer 55 formed in alignment with each other are electrically connected without misalignment by the through-holes 56, and precision during manufacturing is required. These demands for accuracy, along with the increase in the number of manufacturing steps for forming the through-holes 56 on the printed circuit board 51 and printing the conductors 57, become a bottleneck for reducing the manufacturing cost, and also cause a problem on the printed circuit board 51 during manufacturing. A region for forming a through hole is required between a large number of semiconductor elements arranged adjacent to each other, which limits the number of semiconductor devices that can be formed and formed on one printed circuit board.
【0004】しかも比較的厚みのあるプリント基板51
上に半導体素子を搭載した上で樹脂封止するような製法
であるため、プリント基板51自体の存在が半導体装置
の小型化,薄型化の支障となるとともに半導体素子52
の動作時に発生した熱が基板自体に蓄積され易く、放熱
性に劣るという欠点もあった。In addition, a relatively thick printed circuit board 51
Since the manufacturing method is such that a semiconductor element is mounted thereon and then sealed with a resin, the presence of the printed board 51 itself hinders miniaturization and thinning of the semiconductor device, and the semiconductor element 52
There is also a disadvantage that heat generated at the time of the operation is easily accumulated in the substrate itself and heat radiation is poor.
【0005】本発明の目的は、かかる従来の問題点を解
決するために提案されたものであり、高精度であって、
かつ小型で特に薄型の半導体装置を、量産性に優れかつ
安価に生産できる製造方法を提供するにある。An object of the present invention has been proposed to solve such a conventional problem.
Another object of the present invention is to provide a manufacturing method capable of producing a small and particularly thin semiconductor device with excellent mass productivity and at low cost.
【0006】[0006]
【課題を解決するための手段】本発明は、上記課題を解
決するための半導体装置の製造方法であって、少なくと
も一面に導電性を有する基板の該一面側に、所定のパタ
ーンニングを施したレジストパターン層を形成する工程
と、上記基板のレジストパターン層を除く露出面に導電
性金属を電着することで、基板上に半導体素子搭載用の
金属層と1以上の電極層とをそれぞれ独立して並設形成
する工程と、基板より上記レジストパターン層を除去す
る工程と、上記金属層上に半導体素子を搭載した後、半
導体素子上の電極と上記電極層とを電気的に接続する工
程と、上記基板上において半導体素子搭載部分を樹脂層
で封止する工程と、上記基板を除去して、金属層と電極
層の各裏面が露出した樹脂封止体を得る工程とからなる
ことを特徴とする。According to the present invention, there is provided a method of manufacturing a semiconductor device for solving the above-mentioned problems, wherein a predetermined patterning is applied to at least one surface of a substrate having conductivity. The step of forming a resist pattern layer and the step of depositing a conductive metal on the exposed surface of the above-mentioned substrate except for the resist pattern layer, thereby forming a metal layer for mounting a semiconductor element and one or more electrode layers on the substrate independently. Forming the resist pattern layer from the substrate, mounting the semiconductor element on the metal layer, and then electrically connecting the electrode on the semiconductor element to the electrode layer. And sealing the semiconductor element mounting portion on the substrate with a resin layer, and removing the substrate to obtain a resin sealing body in which the back surfaces of the metal layer and the electrode layer are exposed. Feature
【0007】また、請求項2に示す本発明は、基板上に
導電性金属を電着する工程において、導電性金属をレジ
ストパターン層の厚みを越えて電着させることで、金属
層および電極層の上端部周縁に張り出し部を形成するよ
うにした請求項1に記載の半導体装置の製造方法であ
る。According to a second aspect of the present invention, in the step of electrodepositing a conductive metal on a substrate, the conductive metal is electrodeposited beyond the thickness of the resist pattern layer, thereby forming a metal layer and an electrode layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an overhang portion is formed at a periphery of an upper end portion of the semiconductor device.
【0008】また、請求項3に示す本発明は、張り出し
部の張出し長さを、5〜20μmの範囲とした請求項1
又は2に記載の半導体装置の製造方法である。According to a third aspect of the present invention, the overhang length of the overhang portion is in the range of 5 to 20 μm.
Or a method for manufacturing a semiconductor device according to item 2.
【0009】また、請求項4に示す本発明は、導電性金
属を電着する前の工程で、基板の表面を活性化処理した
後電着工程を行うようにした請求項1に記載の半導体装
置の製造方法である。According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the electrodeposition step is performed after activating the surface of the substrate before the electrodeposition of the conductive metal. It is a manufacturing method of an apparatus.
【0010】また、請求項5に示す本発明は、基板上に
金属層と電極層との対を複数組並列して形成し、各金属
層上に搭載された複数の半導体素子と各素子の電極に対
応する電極層とを電気的に接続した後、複数組の素子搭
載部分を連続した樹脂層で封止し、基板を除去した後、
個々の樹脂封止体に切断する工程を有する、請求項1に
記載の半導体装置の製造方法である。According to a fifth aspect of the present invention, a plurality of pairs of a metal layer and an electrode layer are formed in parallel on a substrate, and a plurality of semiconductor elements mounted on each metal layer and a plurality of elements of each element are formed. After electrically connecting the electrode layers corresponding to the electrodes, sealing the plural sets of element mounting portions with a continuous resin layer, removing the substrate,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of cutting into individual resin sealing bodies.
【0011】[0011]
【作用】本発明では、基板上に半導体素子搭載用の金属
層と電極層とを各々電鋳により同時形成するとともに、
基板表面の金属層上に半導体素子搭載の後素子上の電極
と基板上の電極層とを電気的に接続し、素子搭載部分を
樹脂封止した後基板のみを除去する工程とから半導体装
置を製造するので、電着で構成される核部分の積層が極
めて良好で微細な配置にも対応でき、かつ半導体装置を
構成する部品としてガラスエポキシやセラミック等の高
価なプリント基板を使用する必要がなく、材料費を低減
できるとともに、樹脂封止される半導体素子搭載用の構
成部品としてのこの種プリント基板を必要としないた
め、半導体装置自体の小型化、特に薄型化を著しく推進
できるものである。また、電鋳工程により金属層と電極
層とを形成するための母型となる基板を、後工程である
樹脂封止工程まで残存させ、その後除去するものとして
いる為、後工程中の金属層と電極層各々の主面を保護す
る役割も果たすものである。According to the present invention, a metal layer for mounting a semiconductor element and an electrode layer are simultaneously formed on a substrate by electroforming.
After the semiconductor element is mounted on the metal layer on the surface of the substrate, the electrode on the element is electrically connected to the electrode layer on the substrate, the element mounting portion is sealed with resin, and only the substrate is removed. Because it is manufactured, the core portion formed by electrodeposition can be laminated very well and it can cope with fine arrangement, and there is no need to use expensive printed boards such as glass epoxy or ceramic as components that constitute semiconductor devices. In addition, the material cost can be reduced, and this type of printed circuit board is not required as a component for mounting a semiconductor element to be sealed with a resin, so that the semiconductor device itself can be significantly reduced in size, particularly, thinner. In addition, since a substrate serving as a matrix for forming a metal layer and an electrode layer by an electroforming process is left until a resin sealing process, which is a subsequent process, and then removed, a metal layer in a subsequent process is removed. It also plays a role of protecting the main surface of each of the electrode layers.
【0012】さらに、基板上に導電性金属を電着する電
鋳工程において、導電性金属をレジストパターン層の厚
みを越えて、いわゆるオーバーハングさせて電着させる
ことで、金属層および電極層の上端部周縁に張り出し部
を形成するようにしているので、レジストパターン層を
除去した後の樹脂封止工程において、樹脂層に対し各張
り出し部がくい込み状に位置するため、この喰い付き効
果により剥離作業等により基板を樹脂封止体側から引き
剥し除去をする際、金属層および電極層が基板側にくっ
ついて引き離されることなく、確実に樹脂封止体側に残
り、ズレや欠け等が効果的に防止でき、半導体装置の信
頼性を向上させることができる。また、金属層および電
極層の上端部周縁全周にわたって形成される特有の張り
出し形状により、半導体装置裏面側からの金属層,電極
層各層と樹脂層との境界部分を通して侵入する水分等の
上方への侵入を阻止し、耐水性にも優れたものとするこ
とができる。この際張出し部の張り出し長さは、5〜2
0μmの範囲となるように電着時オーバーハングさせる
ことで、張り出し部と樹脂層との確実な食い付き効果に
よる基板除去作業の確実性を向上させるとともに、樹脂
封止前のレジストパターン層の除去工程時に、レジスト
パターンと共に金属層,電極層各層が基板から浮き上が
ったり、剥がれることも生じない。Further, in the electroforming step of electrodepositing a conductive metal on the substrate, the conductive metal is electrodeposited in a so-called overhang over the thickness of the resist pattern layer, so that the metal layer and the electrode layer are electrodeposited. Since the overhanging portion is formed at the periphery of the upper end portion, in the resin sealing step after the removal of the resist pattern layer, since each overhanging portion is located in a bite shape with respect to the resin layer, it is peeled off by this biting effect. When the substrate is peeled off from the resin sealing body side by work or the like, the metal layer and the electrode layer do not stick to the substrate side and are securely separated and remain on the resin sealing body side without being separated. The reliability of the semiconductor device can be improved. In addition, due to the unique overhanging shape formed over the entire periphery of the upper end portion of the metal layer and the electrode layer, upward of moisture invading from the back side of the semiconductor device through the boundary between the metal layer, the electrode layer and the resin layer. Can be prevented, and excellent water resistance can be obtained. In this case, the overhang length of the overhang portion is 5 to 2
Overhanging at the time of electrodeposition so as to be within the range of 0 μm improves the reliability of the substrate removal work due to the reliable biting effect between the overhang portion and the resin layer, and also removes the resist pattern layer before resin sealing. During the process, the metal layer and the electrode layer together with the resist pattern do not float or peel off from the substrate.
【0013】導電性金属を電着する前の工程において、
基板の表面をいわゆる活性化処理した後電着工程を行う
ようにしているので、基板と電着物である金属層と電極
層との密着力が向上し、金属層への半導体素子搭載後の
ワイヤ結線工程において、ボンディング装置側の超音波
振動により電極層が基板側から脱落したり浮いたりする
ことがなくなる。In the step before electrodeposition of the conductive metal,
Since the electrodeposition step is performed after the so-called activation treatment of the surface of the substrate, the adhesion between the substrate and the metal layer, which is the electrodeposit, and the electrode layer are improved, and the wire after the semiconductor element is mounted on the metal layer In the connection step, the electrode layer does not drop off or float from the substrate side due to ultrasonic vibration on the bonding apparatus side.
【0014】また、基板上に金属層と電極層との対を複
数組並列して形成し、各金属層上に搭載された複数の半
導体素子と各素子の電極に対応する電極層とを電気的に
接続した後、複数組の素子搭載部分を連続した樹脂層で
封止し、基板を除去した後、個々の樹脂封止体に切断す
るようにしているので、量産性に優れ、製造コストを低
減することができる。A plurality of pairs of metal layers and electrode layers are formed in parallel on a substrate, and a plurality of semiconductor elements mounted on each metal layer and an electrode layer corresponding to an electrode of each element are electrically connected. After the electrical connection, multiple sets of element mounting parts are sealed with a continuous resin layer, the substrate is removed, and then cut into individual resin sealing bodies. Can be reduced.
【0015】[0015]
【発明の実施の形態】(第1実施例)図1乃至図3に本
発明に係る半導体装置を製造する場合の第1実施例を示
す。図1は、本発明に係るリードレス表面実装型の半導
体装置を示しており、同図(a)は断面図、同図(b)
は底面図である。同図において、Sは半導体素子であっ
て、金属層2a上に接着されて搭載されている。Lは半
導体素子S上に形成された電極であり、上記金属層2a
と独立して並設された対応する電極層2bと金等の導電
性のワイヤ3により結線され、電気的に接続されてい
る。上記半導体素子Sの搭載部分は熱硬化性エポキシ樹
脂等の樹脂層4にて封止されており、上記金属層2aと
電極層2bの各裏面が露出した樹脂封止体が構成されて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 3 show a first embodiment in the case of manufacturing a semiconductor device according to the present invention. 1A and 1B show a leadless surface-mount type semiconductor device according to the present invention. FIG. 1A is a sectional view, and FIG.
Is a bottom view. In the figure, S is a semiconductor element, which is bonded and mounted on the metal layer 2a. L denotes an electrode formed on the semiconductor element S, and the metal layer 2a
And a corresponding electrode layer 2b, which is provided independently and side by side, and is electrically connected by a conductive wire 3 such as gold. The mounting portion of the semiconductor element S is sealed with a resin layer 4 made of a thermosetting epoxy resin or the like, thereby forming a resin sealing body in which the back surfaces of the metal layer 2a and the electrode layer 2b are exposed.
【0016】図2及び図3は上記半導体装置の製造方法
を工程ごとに示しており、図2(a)はステンレスやア
ルミ、銅等の導電性の金属板、例えば本実施例の場合S
US430により形成された0.1mm厚の基板1の両
面に約50μm厚のアルカリタイプの感光性フィルムレ
ジストをラミネートする等して、感光性レジスト層5,
5を密着させる工程であり、次いで図2(b)のごとく
基板1の一面側の感光性レジスト層5上に所定パターン
のフィルムFを配した状態で紫外線照射による両面露光
を行った後現像処理を行い図2(c)に示すような、基
板1の一面側に所定のパターンニングを施したレジスト
パターン層6とその裏面に硬化したレジスト層5を得
る。FIGS. 2 and 3 show a method of manufacturing the above-described semiconductor device for each step. FIG. 2A shows a conductive metal plate such as stainless steel, aluminum, or copper, for example, S in the case of this embodiment.
Laminating about 50 μm thick alkaline type photosensitive film resist on both sides of a 0.1 mm thick substrate 1 formed by US430, etc.
2B, and then a double-sided exposure by ultraviolet irradiation with a film F having a predetermined pattern disposed on the photosensitive resist layer 5 on one side of the substrate 1 as shown in FIG. As shown in FIG. 2 (c), a resist pattern layer 6 having a predetermined pattern formed on one side of the substrate 1 and a cured resist layer 5 formed on the back side are obtained.
【0017】次いで、基板1の一面側のレジストパター
ン層6で覆れていない露出面に対し、必要に応じて化学
エッチングによる表面酸化被膜除去や薬品による周知の
化学処理等の表面活性化処理を行った後、基板1に電鋳
を行い、図2(d)に示すごとく基板1のレジストパタ
ーン層6により規定された露出面より導電性金属の電着
物を成長させ、半導体搭載用の金属層2aと1の金属層
2aに対して1以上の独立した電極層2bを各々対とし
て、複数組を並列形成する。なお、電着物としてはニッ
ケルやニッケル−コバルト合金銅その他種々の金属が考
えられるが、本実施例においては、スルファミン酸ニッ
ケルの無光沢浴を使用し、レジストパターン層6の厚さ
範囲内の、40〜50μmの厚さで電着させた。上記表
面活性化処理の工程については、必須の工程ではない。Next, the exposed surface of the substrate 1 which is not covered with the resist pattern layer 6 on one side is subjected to a surface activation treatment such as removal of a surface oxide film by chemical etching or a well-known chemical treatment with chemicals as necessary. After that, the substrate 1 is electroformed, and as shown in FIG. 2D, an electrodeposit of a conductive metal is grown from the exposed surface defined by the resist pattern layer 6 of the substrate 1 to form a metal layer for mounting a semiconductor. Plural sets are formed in parallel with one or more independent electrode layers 2b as pairs for each of the metal layers 2a and 2a. As the electrodeposit, nickel, nickel-cobalt alloy copper, and other various metals can be considered. In the present embodiment, a matte bath of nickel sulfamate is used, and Electrodeposited with a thickness of 40-50 μm. The step of the surface activation treatment is not an essential step.
【0018】次いで、必要に応じて各金属層2aおよび
電極層2bの表面に結着力向上用の金メッキ等を0.3
〜0.4μm厚で行い、基板1の両面よりレジストパタ
ーン層6及びレジスト層5を除去することで、図2
(e)の状態となる。なお、レジストの除去法としては
アルカリ溶液による膨潤除去の方法等が考えられる。Next, if necessary, the surface of each of the metal layers 2a and the electrode layers 2b is coated with 0.3% of gold plating or the like for improving the binding force.
By removing the resist pattern layer 6 and the resist layer 5 from both sides of the substrate 1, the thickness of FIG.
The state shown in FIG. As a method for removing the resist, a method for removing swelling with an alkali solution or the like is conceivable.
【0019】次いで図3(a)に示すごとく、半導体素
子Sを公知の手法により金属層2a上に接着して搭載す
るとともに、上記半導体素子S上の電極Lにこれと対応
する電極層2bとを、図3(b)のごとく、金線等の導
電性のワイヤ3を用いて超音波ボンディング装置等によ
り結線する。ここで、ワイヤ3を結線するにあたり、各
電極層2bにはボンディング装置からの引き離し力が作
用し、基板1から浮き上がろうとするが、上記のごと
く、電鋳工程に先立って、基板1の露出面に対し表面活
性化処理を行うことにより、基板1と電着層との密着力
を予め向上させているため、結線時における電極層2b
の脱落や浮き上がりを効果的に予防でき、製造工程時の
不良品形成率を低減できる。Next, as shown in FIG. 3A, the semiconductor element S is bonded and mounted on the metal layer 2a by a known method, and the electrode L on the semiconductor element S is connected to the corresponding electrode layer 2b. Are connected by an ultrasonic bonding device or the like using a conductive wire 3 such as a gold wire as shown in FIG. Here, when the wires 3 are connected, a separating force from the bonding device acts on each electrode layer 2b, and the electrode layers 2b tend to float up from the substrate 1. However, as described above, before the electroforming process, Since the adhesion between the substrate 1 and the electrodeposition layer is improved in advance by performing the surface activation treatment on the exposed surface, the electrode layer 2b at the time of connection is formed.
Can be effectively prevented from falling off and rising, and the defective product formation rate during the manufacturing process can be reduced.
【0020】次いで基板1上の半導体素子S搭載部分
を、図3(c)のごとく熱硬化性エポキシ樹脂等の樹脂
層4でモールドし、基板1上に樹脂封止体を形成する。
具体的には基板1一面側をモールド金型(上型)に装着
するともに、モールド金型内にエポキシ樹脂をキャビテ
ィにより圧入するもので、基板1上に並列して形成し
た、複数組の半導体素子搭載部が樹脂層4により連続し
て封止された形態となる。この場合基板1自体が樹脂モ
ールド時における下型の機能を果たす。なお、モールド
時に複数の基板1を並列に配置して、エポキシ樹脂をラ
イナを通して各基板1と上金型との間に圧入するように
すれば、効率良く多数の樹脂封止を行うことが可能であ
る。Next, as shown in FIG. 3C, the portion on which the semiconductor element S is mounted on the substrate 1 is molded with a resin layer 4 such as a thermosetting epoxy resin, and a resin sealing body is formed on the substrate 1.
More specifically, a plurality of sets of semiconductors are formed by mounting one surface of the substrate 1 on a mold (upper die) and press-fitting an epoxy resin into the mold by a cavity. The element mounting portion is continuously sealed by the resin layer 4. In this case, the substrate 1 itself functions as a lower mold at the time of resin molding. In addition, when a plurality of substrates 1 are arranged in parallel at the time of molding and epoxy resin is press-fitted between each substrate 1 and the upper mold through a liner, a large number of resin sealing can be performed efficiently. It is.
【0021】次いで、図3(d)のごとく、樹脂封止体
から基板1を除去することにより、樹脂封止体の底面に
は複数組の金属層2aと電極層2bの各裏面が露出する
とともに、金属層2a,電極層2bの各裏面と樹脂層4
の底面は略同一平面となっている。上記基板1を除去す
る方法としては、樹脂封止体から基板1を引き剥がす等
強制的に剥離除去する方法の他、例えば基板1等を構成
する材質に応じては、樹脂封止体側への影響のない溶剤
等により基板1を溶解して除去する方法も含まれるもの
である。なお、本工程後必要に応じて、各電極層2bあ
るいは電極層2bと金属層2aの裏面のみに実装用に
金,銀等の導電性金層の薄膜をフラッシュメッキ等の周
知の方法により、0.3〜0.5μm厚で形成するよう
にしても良い。Next, as shown in FIG. 3D, by removing the substrate 1 from the resin sealing body, a plurality of sets of the back surfaces of the metal layer 2a and the electrode layer 2b are exposed on the bottom surface of the resin sealing body. In addition, the respective back surfaces of the metal layer 2a and the electrode layer 2b and the resin layer 4
Are substantially flush with each other. As a method for removing the substrate 1, besides a method for forcibly removing the substrate 1 such as peeling the substrate 1 from the resin sealing body, for example, depending on a material constituting the substrate 1 and the like, The method also includes a method of dissolving and removing the substrate 1 with a solvent or the like having no influence. After this step, if necessary, a thin film of a conductive gold layer such as gold or silver is mounted on only the back surface of each electrode layer 2b or the electrode layer 2b and the metal layer 2a by a known method such as flash plating. It may be formed in a thickness of 0.3 to 0.5 μm.
【0022】次いで、図3(e)のごとく樹脂封止体を
切断線X−Xに沿って1つの半導体素子の対毎に切断し
て切り離すダイシングの工程を経て、個々の樹脂封止体
すなわち半導体装置が完成するものである。Next, as shown in FIG. 3E, a dicing step of cutting and separating the pair of semiconductor elements along the cutting line XX as shown in FIG. The semiconductor device is completed.
【0023】(第2実施例)次に、基板1上に導電性金
属を電着する工程において、導電性金属をレジストパタ
ーン層6の厚みを越えて電着させることで、金属層2a
および電極層2bの上端部周縁に張り出し部11,11
を形成するようにする点につき説明する。(Second Embodiment) Next, in the step of electrodepositing a conductive metal on the substrate 1, the conductive metal is electrodeposited beyond the thickness of the resist pattern layer 6, thereby forming the metal layer 2a.
And overhanging portions 11, 11 on the periphery of the upper end of electrode layer 2b.
Will be described.
【0024】すなわち、本発明においては図2(d)の
電鋳工程において、電着金属はレジストパターン層6の
厚みの範囲内に押さえて電着形成しても良いが、本実施
例のものは図4に示すごとく、電着金属(金属層2a,
電極層2b)を電着範囲を規制するレジストパターン層
6の厚みを越えて電着させるいわゆるオーバーハングさ
せることで、レジストパターン層6除去後図5に示すよ
うに金属層2aおよび電極層2bの周縁に断面庇形状の
張り出し部11,11が一体に形成されるような形状と
なるごとくしたものである。特にこの張り出し部11,
11の張り出し長さTは5〜20μmの範囲とすること
が好ましい。That is, in the present invention, in the electroforming step of FIG. 2D, the electrodeposited metal may be formed by electrodeposition by pressing the electrodeposited metal within the thickness range of the resist pattern layer 6. Is the electrodeposited metal (metal layer 2a,
The electrode layer 2b) is electrodeposited beyond the thickness of the resist pattern layer 6 that regulates the electrodeposition range, so-called overhang, so that the metal layer 2a and the electrode layer 2b are removed after the resist pattern layer 6 is removed as shown in FIG. The overhanging portions 11, 11 having a cross-sectional eaves shape are formed on the periphery so as to be integrally formed. In particular, this overhang 11,
The overhang length T of 11 is preferably in the range of 5 to 20 μm.
【0025】上記のごとく金属層2aおよび電極層2b
の周縁に張り出し部11,11を形成しておけば、後工
程の樹脂層4による樹脂封止状態において、図6のごと
く樹脂層4は各張り出し部11,11がくい込み状に位
置した状態で硬化しているため、この喰い付き効果によ
り、樹脂封止体からの基板1の剥離作業時に基板1を引
き剥がし除去する際、金属層2aおよび電極層2bは樹
脂層4側に確実に残留し、基板1とともにくっついて引
き離されることはなく、ズレや欠落等が効果的に防止で
き、製造工程時の歩留まりが向上する。さらに、特有の
庇形状を持つ張り出し部11の存在により、金属層2a
および電極層2bの裏面側の樹脂層4との微細な隙間か
ら侵入する水分等の上方部すなわち結線部分や半導体素
子搭載部分への侵入を阻止する効果もあり、半導体素子
Sやワイヤとの結線個所への耐水性をも向上し、完成し
た半導体装置自体の信頼性も向上させることができるも
のである。As described above, the metal layer 2a and the electrode layer 2b
If the overhang portions 11 are formed on the periphery of the resin layer 4 in a resin-sealed state by the resin layer 4 in a later step, the resin layer 4 is in a state where the overhang portions 11 are positioned in a recessed shape as shown in FIG. Due to the hardening, the metal layer 2a and the electrode layer 2b surely remain on the resin layer 4 side when the substrate 1 is peeled and removed during the peeling operation of the substrate 1 from the resin sealing body due to the biting effect. In addition, it does not stick together with the substrate 1 and is separated from the substrate 1, which can effectively prevent displacement and dropout, thereby improving the yield in the manufacturing process. Furthermore, the presence of the overhang portion 11 having a unique eaves shape allows the metal layer 2a
In addition, there is also an effect of preventing moisture and the like entering from a minute gap between the resin layer 4 on the back surface side of the electrode layer 2b and the upper portion, that is, the connection portion and the semiconductor element mounting portion, from connecting to the semiconductor element S and the wire. It is also possible to improve the water resistance at each location and to improve the reliability of the completed semiconductor device itself.
【0026】なお、各張り出し部11については、出願
人において実験により検証した結果、長さTはレジスト
パターン層6の厚みを越えてオーバーハングさせる高さ
に略比例して成長するものであり、その長さTが5μm
以下だとモールド時の樹脂層4に対する喰い付き効果が
弱く、基板1の引き剥がしの際、基板1側に若干ではあ
るが金属層2aおよび電極層2bがくっついて引き離さ
れ、ズレや欠落を生じる現象が見受けられるため、これ
以上の長さに設定することが好ましく、また20μmを
越えると電着工程後のレジストパターン層6の除去の
際、アルカリ溶剤によるレジストパターン層6の膨潤除
去時に膨潤したレジストパターン層6が張り出し部1
1,11を介して電着金属(金属層2a,電極層2b)
を基板1から浮き上がらせてしまう虞れがあるため、こ
れらの点を考慮して5〜20μmの範囲内に設定するこ
とが好ましい。As for each overhanging portion 11, as a result of an experiment conducted by the applicant, the length T grows substantially in proportion to the height at which the resist pattern layer 6 overhangs beyond the thickness thereof. Its length T is 5 μm
Below this, the biting effect on the resin layer 4 at the time of molding is weak, and when the substrate 1 is peeled off, the metal layer 2a and the electrode layer 2b are slightly but adhered to the substrate 1 side and are separated from each other, resulting in displacement or chipping. Since a phenomenon is observed, it is preferable to set the length to be longer than this. If the length exceeds 20 μm, the resist pattern layer 6 swells when the resist pattern layer 6 is removed by swelling with an alkaline solvent during removal of the resist pattern layer 6 after the electrodeposition step. The resist pattern layer 6 is overhanging part 1
Electrodeposited metal via 1 and 11 (metal layer 2a, electrode layer 2b)
There is a possibility that the substrate may be lifted from the substrate 1. Therefore, it is preferable that the distance be set in the range of 5 to 20 μm in consideration of these points.
【0027】(第3実施例)図7(a),(b)の実施
例は、異なる対の隣接する電極層2b,2bを、その左
右に配した金属層2a上の半導体素子Sに対して、連接
して形成しておき、半導体素子Sを搭載してワイヤ結線
し、樹脂層4による封止の後、最終の切断線X−X(X
1−X1,X2−X2)に沿ってダイシングする工程におい
て、電極層2b,2bを連接する中央部分で切断して個
々の半導体装置側に切り離すようにしたもので、この場
合基板1上への電極層2b,2bの配置を接近させて効
率的に行なえ、1つの基板1からの取り数を増やすこと
が可能で、量産化,コスト低減に適するものとなる。(Third Embodiment) In the embodiment shown in FIGS. 7A and 7B, different pairs of adjacent electrode layers 2b, 2b are used for a semiconductor element S on a metal layer 2a disposed on the left and right sides thereof. The semiconductor element S is mounted, connected to a wire, sealed with the resin layer 4, and then sealed with a final cutting line XX (X
In the step of dicing along (1-X1, X2-X2), the electrode layers 2b, 2b are cut at the connecting central portion and separated into individual semiconductor device sides. The arrangement of the electrode layers 2b, 2b can be efficiently performed by bringing them closer to each other, so that the number of pieces to be taken from one substrate 1 can be increased, which is suitable for mass production and cost reduction.
【0028】(第4実施例)図8(a),(b)の実施
例のごとく、電着形成した金属層2a,電極層2b裏面
のいずれか一方もしくは両方を樹脂封止した際、樹脂層
4の裏面よりも若干突出させるように構成することも可
能である(実施例は金属層2a,電極層2b両方の底面
を突出させたものを示す)。この場合の製造方法として
は、図9aに示すように、基板1一面側の金属層2a,
電極層2bが形成される部分と対応する位置に、予め突
出させる量に応じて、例えば5〜15μm程度の凹部2
1をエッチングやプレス等により形成しておく。後の工
程は本願通常の工程と同一であるが、この場合もレジス
トパターン層6の高さを越えて、オーバーハングさせて
電着を施し、張り出し部11を設けておくことが好まし
い。レジストパターン層6の除去後、図9(b)のよう
に半導体素子S搭載,結線,樹脂層4封止の各工程の
後、基板1を除去することで、凹部21の凹入量がその
まま樹脂層4裏面に対する金属層2a,電極層2b裏面
の突出量として反映され、樹脂層4の裏面よりも突出し
て形成される。最後に切断線X−Xに沿ってダイシング
し、個々の樹脂封止体が完成する。もちろんこの後各金
属層2aや電極層2b等の裏面に金,銀等をフラッシュ
メッキにより薄膜形成しても良い。(Fourth Embodiment) As shown in FIGS. 8 (a) and 8 (b), when one or both of the back surfaces of the electrodeposited metal layer 2a and the electrode layer 2b are sealed with resin, It is also possible to have a configuration in which the bottom surface of each of the metal layer 2a and the electrode layer 2b is protruded (the embodiment shows a configuration in which both the metal layers 2a and the electrode layers 2b are protruded slightly). As a manufacturing method in this case, as shown in FIG. 9A, the metal layer 2a,
A concave portion 2 having a size of, for example, about 5 to 15 μm is formed at a position corresponding to the portion where the electrode layer 2 b is formed, in accordance with the amount of protrusion.
1 is formed by etching or pressing. Subsequent steps are the same as the ordinary steps of the present application, but also in this case, it is preferable that the overhanging portion is applied over the height of the resist pattern layer 6 to perform electrodeposition to provide the overhang portion 11. After the resist pattern layer 6 is removed, the substrate 1 is removed after each step of mounting the semiconductor element S, connecting wires, and sealing the resin layer 4 as shown in FIG. This is reflected as the amount of protrusion of the back surface of the metal layer 2a and the back surface of the electrode layer 2b with respect to the back surface of the resin layer 4, and is formed so as to protrude from the back surface of the resin layer 4. Finally, dicing is performed along the cutting line XX to complete individual resin sealing bodies. Of course, after that, a thin film of gold, silver, or the like may be formed on the back surface of each metal layer 2a or electrode layer 2b by flash plating.
【0029】(他の実施例)上記第4実施例では、樹脂
封止した際、金属層2a,電極層2b裏面のいずれか一
方もしくは両方を、樹脂層4の裏面よりも若干突出させ
るように構成したものであるが、逆にこれら電着層裏面
を樹脂層4の裏面よりも若干凹入させるごとく構成する
ことも可能である。この場合は、基板1一面側の金属層
2a,電極層2bと対応する位置のみを突出させるごと
く、エッチング,プレス等により予め基板1を形成して
おけば良く、後の工程は本願通常工程と同一で良い。(Other Embodiments) In the fourth embodiment, one or both of the rear surface of the metal layer 2a and the rear surface of the electrode layer 2b are slightly projected from the rear surface of the resin layer 4 when the resin is sealed. In this case, the back surface of the electrodeposited layer may be slightly recessed from the back surface of the resin layer 4. In this case, the substrate 1 may be formed in advance by etching, pressing or the like so that only the position corresponding to the metal layer 2a and the electrode layer 2b on one surface side of the substrate 1 is projected. It may be the same.
【0030】[0030]
【発明の効果】以上説明したように、本発明によれば、
従来半導体装置を構成する部品として要していた、プリ
ント基板を使用する必要がなく、材料費や各種加工費を
低減できるとともに、半導体装置自体の小型化、特に薄
型化を図ることができるものである。また半導体素子を
搭載する部分や外部導出用の電極部分が電鋳により構成
されるため、精度が極めて良好で、微細な配置にも対応
でき、半導体の高密度化に伴う他ピン化にも対応するこ
とができるものである。さらに、半導体素子Sを搭載す
る金属層が樹脂層裏面から露出する形態であるため放熱
性にも優れる。As described above, according to the present invention,
This eliminates the need to use a printed circuit board, which was conventionally required as a component of a semiconductor device, and can reduce material costs and various processing costs, as well as reduce the size of the semiconductor device itself, especially the thickness. is there. In addition, since the part for mounting the semiconductor element and the electrode part for external derivation are formed by electroforming, the precision is extremely good, it can correspond to fine arrangement, and it corresponds to other pins due to the high density of semiconductors Is what you can do. Further, since the metal layer on which the semiconductor element S is mounted is exposed from the back surface of the resin layer, the heat dissipation is excellent.
【0031】さらに、基板上に導電性金属を電着する電
鋳工程において、導電性金属をレジストパターン層の厚
みを越えて、オーバーハングさせて電着するように構成
すれば、金属層2aや電極層2bの上端部周縁に意図的
に庇状の張り出し部11を形成することが可能で、この
場合、レジストパターン層6を除去した後の樹脂封止工
程において、樹脂層に対し各張り出し部11がくい込み
状に位置するため、この喰い付き効果により、金属層2
a,電極層2bと樹脂層4との結着力が向上し、製品化
後の品質向上はもちろんのこと、後工程で基板を引き離
す際、金属層2aや電極層2b等の重要部品が、基板側
にくっついて引き離されることなく、確実に樹脂封止体
側に残り、ズレや欠落等が効果的に防止できるもので、
半導体装置の信頼性を向上させることができる。また、
庇状の張り出し部11の特有の形状により、水分等の浸
入を阻止するとともに、沿面距離も稼ぐ効果もあり、結
線部分や半導体素子側への耐水性耐湿性の向上も図るこ
とができるものである。Further, in the electroforming step of electrodepositing the conductive metal on the substrate, the conductive metal may be overhanged and electrodeposited by overhanging beyond the thickness of the resist pattern layer. It is possible to intentionally form an eave-shaped overhang 11 on the periphery of the upper end of the electrode layer 2b. In this case, in the resin sealing step after removing the resist pattern layer 6, each overhang is formed on the resin layer. 11 is bite-shaped, the metal layer 2
a, the binding force between the electrode layer 2b and the resin layer 4 is improved, and not only the quality after commercialization is improved, but also important components such as the metal layer 2a and the electrode layer 2b are separated when the substrate is separated in a later process. Without sticking to the side and being separated, it is surely left on the resin sealing body side, which can effectively prevent displacement and omission, etc.
The reliability of the semiconductor device can be improved. Also,
The unique shape of the overhang-like overhanging portion 11 prevents water and the like from entering, and also has the effect of increasing the creepage distance, thereby improving the water resistance and moisture resistance to the connection portion and the semiconductor element side. is there.
【図1】(a)は、本発明の半導体装置の一実施例を示
す断面図,(b)はその裏面図である。FIG. 1A is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 1B is a rear view thereof.
【図2】(a)乃至(e)は、本発明の第1実施例に示
す半導体装置の製造方法を説明する断面図である。FIGS. 2A to 2E are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図3】(a)乃至(e)は、図2(e)に続く半導体
装置の製造方法を説明する断面図である。FIGS. 3A to 3E are cross-sectional views illustrating a method for manufacturing the semiconductor device following FIG. 2E.
【図4】本発明の第2実施例に示す半導体装置の製造方
法を説明する断面図(一部拡大図)である。FIG. 4 is a cross-sectional view (partially enlarged view) illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図5】本発明の第2実施例に示す半導体装置の製造方
法を説明する断面図(一部拡大図)である。FIG. 5 is a cross-sectional view (a partially enlarged view) illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
【図6】本発明の第2実施例に示す半導体装置の製造方
法を説明する断面図である。FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
【図7】(a)は、本発明の第3実施例に示す半導体装
置の製造方法を説明する透視上面図、(b)はその断面
図である。FIG. 7A is a perspective top view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention, and FIG. 7B is a cross-sectional view thereof.
【図8】(a)は、本発明の第4実施例に示す半導体装
置の断面図、(b)はその裏面斜視図である。FIG. 8A is a sectional view of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 8B is a rear perspective view thereof.
【図9】(a),(b)は本発明の第4実施例に示す半
導体装置の製造方法を説明する断面図である。FIGS. 9A and 9B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
【図10】従来の半導体装置を示す断面図である。FIG. 10 is a cross-sectional view showing a conventional semiconductor device.
1 基板 2a 金属層 2b 電極層 4 樹脂層 6 レジストパターン層 S 半導体素子 Reference Signs List 1 substrate 2a metal layer 2b electrode layer 4 resin layer 6 resist pattern layer S semiconductor element
───────────────────────────────────────────────────── フロントページの続き (72)発明者 沼田 典之 福岡県田川郡方城町大字伊方4680番地 九 州日立マクセル株式会社内 (72)発明者 木村 浩 東京都江東区越中島1丁目2−7 トレッ クス・セミコンダクター株式会社東京支店 内 Fターム(参考) 5F061 AA01 BA03 CA21 CB13 ──────────────────────────────────────────────────続 き Continued on the front page (72) Noriyuki Numata, Inventor 4680, Ikata, Fukuoka, Tagawa-gun, Fukuoka Prefecture Inside Kyushu Hitachi Maxell Co., Ltd. (72) Inventor Hiroshi Kimura 1-2-7 Ecchujima, Koto-ku, Tokyo Trek 5F061 AA01 BA03 CA21 CB13
Claims (5)
の該一面側に、所定のパターンニングを施したレジスト
パターン層6を形成する工程と、上記基板1のレジスト
パターン層6を除く露出面に導電性金属を電着すること
で、基板1上に半導体素子搭載用の金属層2aと1以上
の電極層2bとをそれぞれ独立して並設形成する工程
と、基板1より上記レジストパターン層6を除去する工
程と、上記金属層2a上に半導体素子Sを搭載した後、
半導体素子上の電極と上記電極層2bとを電気的に接続
する工程と、上記基板1上において半導体素子S搭載部
分を樹脂層4で封止する工程と、上記基板1を除去し
て、金属層2aと電極層2bの各裏面が露出した樹脂封
止体を得る工程とを有する半導体装置の製造方法。1. A substrate 1 having conductivity on at least one surface.
Forming a resist pattern layer 6 with a predetermined patterning on the one surface side, and electrodepositing a conductive metal on an exposed surface of the substrate 1 excluding the resist pattern layer 6, thereby forming A step of independently forming a metal layer 2a for mounting a semiconductor element and one or more electrode layers 2b in parallel, a step of removing the resist pattern layer 6 from the substrate 1, and a step of forming a semiconductor element on the metal layer 2a. After installing S,
A step of electrically connecting an electrode on the semiconductor element to the electrode layer 2b, a step of sealing the semiconductor element S mounting portion on the substrate 1 with a resin layer 4, and a step of removing the substrate 1 Obtaining a resin sealing body in which the back surfaces of the layer 2a and the electrode layer 2b are exposed.
おいて、導電性金属をレジストパターン層6の厚みを越
えて電着させることで、金属層2aおよび電極層2bの
上端部周縁に張り出し部を形成するようにした請求項1
に記載の半導体装置の製造方法。2. In the step of electrodepositing a conductive metal on the substrate 1, the conductive metal is electrodeposited beyond the thickness of the resist pattern layer 6 so that the upper edge of the metal layer 2a and the electrode layer 2b is formed. An overhanging portion is formed.
13. The method for manufacturing a semiconductor device according to item 5.
0μmの範囲とした請求項1又は2に記載の半導体装置
の製造方法。3. The overhang length of the overhang portion 11 is 5 to 2
3. The method for manufacturing a semiconductor device according to claim 1, wherein the range is 0 μm.
の表面を活性化処理した後電着工程を行うようにした請
求項1に記載の半導体装置の製造方法。4. The method according to claim 1, wherein the step of depositing the conductive metal comprises:
2. The method for manufacturing a semiconductor device according to claim 1, wherein the electrodeposition step is performed after activating the surface of the semiconductor device.
を複数組並列して形成し、各金属層2a上に搭載された
複数の半導体素子と各素子の電極に対応する電極層2b
とを電気的に接続した後、複数組の素子搭載部分を連続
した樹脂層4で封止し、基板1を除去した後、個々の樹
脂封止体に切断する工程を有する、請求項1に記載の半
導体装置の製造方法。5. A plurality of pairs of a metal layer 2a and an electrode layer 2b are formed in parallel on a substrate 1, and a plurality of semiconductor elements mounted on each metal layer 2a and electrodes corresponding to the electrodes of each element. Layer 2b
2. The method according to claim 1, further comprising the steps of: after electrically connecting the device, sealing a plurality of sets of element mounting portions with a continuous resin layer 4, removing the substrate 1, and cutting the individual resin sealing bodies. The manufacturing method of the semiconductor device described in the above.
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