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JP2002083920A - Circuit board for reducing power supply voltage fluctuation - Google Patents

Circuit board for reducing power supply voltage fluctuation

Info

Publication number
JP2002083920A
JP2002083920A JP2000273532A JP2000273532A JP2002083920A JP 2002083920 A JP2002083920 A JP 2002083920A JP 2000273532 A JP2000273532 A JP 2000273532A JP 2000273532 A JP2000273532 A JP 2000273532A JP 2002083920 A JP2002083920 A JP 2002083920A
Authority
JP
Japan
Prior art keywords
wiring
power supply
semiconductor element
bypass capacitor
potential fluctuation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000273532A
Other languages
Japanese (ja)
Inventor
Tatsuji Noma
辰次 野間
Taku Suga
卓 須賀
Makoto Torigoe
誠 鳥越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000273532A priority Critical patent/JP2002083920A/en
Publication of JP2002083920A publication Critical patent/JP2002083920A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a voltage drop occurring in a wiring due to its impedance due to a high frequency current on a feed wiring of a semicon ductor element is suppressed by a bypass capacitor but, if the wiring is long between a semiconductor electric power source terminal and the bypass capaci tor, this capacitor cannot effectively suppress the potential fluctuation at the semiconductor element power source terminal. SOLUTION: A series resonance circuit is connected in parallel to a wiring between a semiconductor element power source terminal and a bypass capacitor, and the resonance frequency of this circuit is set to the frequency of a major component among high frequency components of a potential fluctuation. This reduces the wiring impedance to a very low value at this frequency, and hence the bypass capacitor can effectively suppress the potential fluctuation.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子装置に用いる
半導体素子の搭載された回路基板に関し、特に半導体素
子電源端子の電位変動を抑制する回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board on which a semiconductor element used for an electronic device is mounted, and more particularly to a circuit board for suppressing a potential change of a power supply terminal of a semiconductor element.

【0002】[0002]

【従来の技術】従来、半導体素子電源端子での電位変動
を抑制するために、バイパスコンデンサが用いられてき
た。しかし、バイパスコンデンサを効果的に用いるため
には、半導体素子電源端子とバイパスコンデンサの距離
を短くする必要があり、特開平3−254150号公報に開示
されているように、半導体チップ上にチップコンデンサ
を搭載する等の方法が考えられている。
2. Description of the Related Art Conventionally, a bypass capacitor has been used to suppress a potential change at a power supply terminal of a semiconductor device. However, in order to use the bypass capacitor effectively, it is necessary to shorten the distance between the semiconductor element power supply terminal and the bypass capacitor, and as disclosed in JP-A-3-254150, a chip capacitor is provided on the semiconductor chip. For example, a method of mounting the device has been considered.

【0003】[0003]

【発明が解決しようとする課題】半導体素子がスイッチ
ングすると、貫通電流により、半導体素子への給電配線
に高周波電流が流れる。この高周波電流が流れると、給
電配線が持つインピーダンスにより電圧降下が生じ、半
導体素子電源端子の電位変動が起こる。この電位変動が
出力に重畳され、次段の入力の許容範囲を超えると誤動
作を起こしてしまう。
When the semiconductor element is switched, a high-frequency current flows through a power supply wiring to the semiconductor element due to a through current. When this high-frequency current flows, a voltage drop occurs due to the impedance of the power supply wiring, and the potential of the semiconductor element power supply terminal fluctuates. If this potential fluctuation is superimposed on the output and exceeds the allowable range of the input of the next stage, a malfunction will occur.

【0004】この半導体素子電源端子の電位変動を抑制
するためにバイパスコンデンサが用いられている。電荷
をバイパスコンデンサから供給することによって半導体
素子電源端子の電位変動を抑制する為、バイパスコンデ
ンサと半導体素子電源端子間の配線は短くする必要があ
る。長くなると、配線のインピーダンスが大きくなる
為、バイパスコンデンサの効果がなくなり、半導体素子
電源端子の電位変動が大きくなってしまう。
[0004] A bypass capacitor is used to suppress the potential fluctuation of the power supply terminal of the semiconductor element. In order to suppress the potential fluctuation of the semiconductor element power supply terminal by supplying the electric charge from the bypass capacitor, it is necessary to shorten the wiring between the bypass capacitor and the semiconductor element power supply terminal. If the length increases, the impedance of the wiring increases, so that the effect of the bypass capacitor is lost, and the potential fluctuation of the power supply terminal of the semiconductor element increases.

【0005】しかし、半導体素子のピン数が多くなった
り、実装面積を小さくしようとすると、半導体電源端子
とバイパスコンデンサ間の配線を短くすることができ
ず、配線が長い為インピーダンスが大きくなり、半導体
素子電源端子の電位変動をバイパスコンデンサにより効
果的に抑制することが難しいという問題があり、半導体
素子電源端子とバイパスコンデンサ間の配線が長くなっ
ても、半導体素子電源端子の電位変動を効果的に抑制す
るという課題があった。
However, when the number of pins of the semiconductor element is increased or the mounting area is reduced, the wiring between the semiconductor power supply terminal and the bypass capacitor cannot be shortened. There is a problem that it is difficult to effectively suppress the potential fluctuation of the element power supply terminal by the bypass capacitor, and even if the wiring between the semiconductor element power supply terminal and the bypass capacitor becomes long, the potential fluctuation of the semiconductor element power supply terminal is effectively prevented. There was a problem of suppression.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
には、半導体素子電源端子とバイパスコンデンサ間の配
線のインピーダンスを同じ配線長でも、小さくすれば良
い。
In order to solve the above-mentioned problems, it is only necessary to reduce the impedance of the wiring between the power supply terminal of the semiconductor element and the bypass capacitor even with the same wiring length.

【0007】本発明は半導体素子電源端子の電位変動
で、高周波成分の大きな周波数を共振周波数に持つ直列
共振回路1を図1に示す様に、半導体素子6電源端子とバ
イパスコンデンサ4間の配線に並列に接続することによ
り、課題を解決しようとするものである。
According to the present invention, a series resonance circuit 1 having a resonance frequency having a large frequency of a high-frequency component due to a potential change of a power supply terminal of a semiconductor element is connected to a wiring between a power supply terminal of a semiconductor element 6 and a bypass capacitor 4 as shown in FIG. The problem is to be solved by connecting them in parallel.

【0008】直列共振回路を並列に接続することによ
り、共振周波数での配線のインピーダンスは、非常に小
さな値となり、その周波数の高周波電流成分による、電
圧降下を小さくすることができる。これにより、半導体
素子電源端子の電位変動を、バイパスコンデンサにより
効果的に抑制することができる。
By connecting the series resonance circuits in parallel, the impedance of the wiring at the resonance frequency has a very small value, and the voltage drop due to the high-frequency current component at that frequency can be reduced. Thus, the fluctuation of the potential of the semiconductor element power supply terminal can be effectively suppressed by the bypass capacitor.

【0009】更に、複数の直列共振回路を並列に接続す
ることにより、複数の周波数成分に対応することができ
る。
Furthermore, by connecting a plurality of series resonance circuits in parallel, it is possible to cope with a plurality of frequency components.

【0010】実際に実装する時には、キャパシタンスと
インダクタンスを用いて直列共振回路を形成するが、例
えば、コンデンサ素子には、直列等価インダクタンスが
ある為、コンデンサ素子そのものが直列共振回路となっ
ているので、目的の共振周波数を持つコンデンサ素子を
配線パターン上に実装すれば良い。
When actually mounting, a series resonance circuit is formed using the capacitance and the inductance. For example, since the capacitor element has a series equivalent inductance, the capacitor element itself is a series resonance circuit. What is necessary is just to mount the capacitor element having the target resonance frequency on the wiring pattern.

【0011】[0011]

【発明の実施の形態】以下、実施例を用いて、本発明を
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

【0012】図2に実施例に用いた回路を示す。回路基
板は層間厚さ0.4mmの4層基板を用い、バイパスコンデ
ンサ9と半導体素子電源端子11、12間の配線は、幅2m
m、長さ10mmとした。半導体素子には、バスバッファに
使用される74AC541(SOP)10を用い、入力信号として、10
MHzのデューティー比50%のクロック14を与えた。擬似
負荷13として10pFの静電容量を接続した。バイパスコ
ンデンサ9には、0.1μFの静電容量を持つ1608タイプの
チップコンデンサを使用した。
FIG. 2 shows a circuit used in the embodiment. The circuit board uses a four-layer board with an interlayer thickness of 0.4 mm, and the wiring between the bypass capacitor 9 and the semiconductor element power terminals 11 and 12 is 2 m wide.
m and length 10 mm. For the semiconductor device, 74AC541 (SOP) 10 used for the bus buffer is used, and 10
Clock 14 with 50% duty ratio of MHz was given. A capacitance of 10 pF was connected as the dummy load 13. As the bypass capacitor 9, a 1608 type chip capacitor having a capacitance of 0.1 μF was used.

【0013】半導体素子電源端子とバイパスコンデンサ
間の配線に並列に接続する直列共振回路8は、リードタ
イプのセラミックスコンデンサ19を3個並列に接続した
図3に示す回路図の様な並列接続の直列共振回路を用い
た。尚、この回路の端子間17−18のインピーダンスは図
4に示すような周波数特性のを持つ。
The series resonance circuit 8 connected in parallel to the wiring between the power supply terminal of the semiconductor element and the bypass capacitor has a series connection of three lead-type ceramic capacitors 19 connected in parallel as shown in the circuit diagram of FIG. A resonant circuit was used. The impedance between the terminals 17-18 of this circuit has a frequency characteristic as shown in FIG.

【0014】比較例として、直列共振回路を接続しない
場合には、半導体素子電源端子11−12間の電位変動の波
形は、図5の様になり、電位変動の幅20は781mVであっ
た。
As a comparative example, when the series resonance circuit was not connected, the waveform of the potential fluctuation between the semiconductor element power supply terminals 11 and 12 was as shown in FIG. 5, and the width 20 of the potential fluctuation was 781 mV.

【0015】直列共振回路を接続した本実施例では、図
6のような波形となり、電位変動の幅21は455mVとなっ
た。よって、比較例に比べ、電位変動の幅を40%低減す
る効果があった。
In the present embodiment in which a series resonance circuit is connected, the waveform is as shown in FIG. 6, and the potential fluctuation width 21 is 455 mV. Therefore, there is an effect that the width of the potential fluctuation is reduced by 40% as compared with the comparative example.

【0016】本実施例では、直列共振回路に、リードタ
イプのセラミックコンデンサを用いたが、チップコンデ
ンサでもよいし、コンデンサとインダクタにより直列共
振回路を形成してもよい。また、パターンで形成したキ
ャパシタンス、パターンで形成したインダクタンス等で
もよい。更に、これらを組み合わせて、直列共振回路を
形成してもよい。
In this embodiment, a lead type ceramic capacitor is used for the series resonance circuit. However, a chip capacitor may be used, or a series resonance circuit may be formed by a capacitor and an inductor. Further, a capacitance formed by a pattern, an inductance formed by a pattern, or the like may be used. Further, these may be combined to form a series resonance circuit.

【0017】[0017]

【発明の効果】以上説明した様に、半導体素子電源端子
とバイパスコンデンサ間の配線に直列共振回路を並列に
接続することにより、選択的な周波数での配線のインピ
ーダンスを非常に小さくすることができ、半導体素子電
源端子の電位変動をバイパスコンデンサで効果的に低減
できる。また、半導体電源端子とバイパスコンデンサの
配線が長くなっても、バイパスコンデンサにより電位変
動を効果的に抑制することができる。
As described above, by connecting the series resonance circuit in parallel to the wiring between the power supply terminal of the semiconductor element and the bypass capacitor, the impedance of the wiring at a selective frequency can be made very small. In addition, the fluctuation in the potential of the semiconductor element power supply terminal can be effectively reduced by the bypass capacitor. Further, even if the wiring between the semiconductor power supply terminal and the bypass capacitor becomes long, the potential fluctuation can be effectively suppressed by the bypass capacitor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を説明する回路図。FIG. 1 is a circuit diagram illustrating the present invention.

【図2】実施例に用いた回路を示す回路図。FIG. 2 is a circuit diagram showing a circuit used in the embodiment.

【図3】実施例に用いた直列共振回路の回路図。FIG. 3 is a circuit diagram of a series resonance circuit used in the embodiment.

【図4】実施例に用いた直列共振回路のインピーダンス
の周波数特性図。
FIG. 4 is a frequency characteristic diagram of impedance of a series resonance circuit used in an example.

【図5】比較例の電位変動波形図。FIG. 5 is a potential fluctuation waveform diagram of a comparative example.

【図6】実施例の電位変動波形図。FIG. 6 is a potential fluctuation waveform diagram of the embodiment.

【符号の説明】[Explanation of symbols]

1…直列共振回路、2…キャパシタンス、3…インダクタ
ンス、4…バイパスコンデンサ、5…配線インピーダン
ス、6…半導体素子、7…電源、8…直列共振回路、9…バ
イパスコンデンサ、10…半導体素子74AC541(SOP)、11,1
2…半導体素子電源端子、13…擬似負荷、14…クロック
信号、15…キャパシタンス、16…等価インダクタンス、
17、18…端子、19…リードタイプセラミックスコンデン
サ、20…比較例電位変動幅、21…実施例電位変動幅。
1 ... series resonance circuit, 2 ... capacitance, 3 ... inductance, 4 ... bypass capacitor, 5 ... wiring impedance, 6 ... semiconductor element, 7 ... power supply, 8 ... series resonance circuit, 9 ... bypass capacitor, 10 ... semiconductor element 74AC541 ( SOP), 11,1
2 ... Semiconductor element power supply terminal, 13 ... Pseudo load, 14 ... Clock signal, 15 ... Capacitance, 16 ... Equivalent inductance,
17, 18… Terminal, 19… Lead type ceramic capacitor, 20… Comparative potential fluctuation width, 21… Example potential fluctuation width.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載した回路基板におい
て、該半導体素子電源端子と接続されたバイパスコンデ
ンサ間の配線に少なくとも1つ以上の直列共振回路を並
列に接続したことを特徴とする回路基板。
1. A circuit board on which a semiconductor element is mounted, wherein at least one or more series resonance circuits are connected in parallel to a wiring between a bypass capacitor connected to the semiconductor element power supply terminal.
JP2000273532A 2000-09-05 2000-09-05 Circuit board for reducing power supply voltage fluctuation Pending JP2002083920A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000273532A JP2002083920A (en) 2000-09-05 2000-09-05 Circuit board for reducing power supply voltage fluctuation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000273532A JP2002083920A (en) 2000-09-05 2000-09-05 Circuit board for reducing power supply voltage fluctuation

Publications (1)

Publication Number Publication Date
JP2002083920A true JP2002083920A (en) 2002-03-22

Family

ID=18759452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000273532A Pending JP2002083920A (en) 2000-09-05 2000-09-05 Circuit board for reducing power supply voltage fluctuation

Country Status (1)

Country Link
JP (1) JP2002083920A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8085548B2 (en) 2006-09-01 2011-12-27 Hitachi, Ltd. Circuit for suppressing electromagnetic interference, implementation structure and electronic apparatus implementing the same
US8278998B2 (en) 2004-09-30 2012-10-02 Nec Corporation Power supply noise reduction circuit and power supply noise reduction method
JP2013207699A (en) * 2012-03-29 2013-10-07 Auto Network Gijutsu Kenkyusho:Kk Reduction device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8278998B2 (en) 2004-09-30 2012-10-02 Nec Corporation Power supply noise reduction circuit and power supply noise reduction method
US8085548B2 (en) 2006-09-01 2011-12-27 Hitachi, Ltd. Circuit for suppressing electromagnetic interference, implementation structure and electronic apparatus implementing the same
JP2013207699A (en) * 2012-03-29 2013-10-07 Auto Network Gijutsu Kenkyusho:Kk Reduction device

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