JP2001338977A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor capable of preventing a short circuit due to voids in an interlayer insulation film between the wirings of the aspect ratio of 2.5 or more. SOLUTION: A contact hole 8 is opened between gate electrodes 3a, 3b. Then, the void 7 is exposed on the side wall in the contact 8. Thereafter the thin insulation film 11 of about 10-60 nm is formed so as to block the void 7 on the whole face, etch back is performed on the whole face, and a side wall 12 comprising the thin film 11 is formed on only the side wall of the contact holes 8, 8a, 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact portion having a high aspect ratio formed between wirings.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, it is indispensable to embed an interlayer insulating film and form a contact hole in a fine and deep portion having a high aspect ratio.

FIGS. 6 and 7 are process sectional views showing a conventional method of forming a contact portion. FIGS. 6A and 6B
(C) FIGS. 7 (a) and 7 (b) are cross-sectional views in a direction perpendicular to the gate electrode, and FIGS. 6 (d) (e) and 7 (c) (d) show directions parallel to the gate electrode. It is sectional drawing in the AA 'line. The description will be made sequentially according to the drawings.

First, as shown in FIG. 6A, a gate insulating film 2 and a conductive film are sequentially laminated on a silicon substrate 1 and a gate insulating film 2 and a conductive film are formed using a hard mask 4 made of a silicon nitride film. Are sequentially etched to form gate electrodes 3a and 3b as first wirings. Then, after forming a sidewall 5 made of an insulating film on the side walls of the hard mask 4 and the gate electrodes 3a and 3b, an interlayer insulating film 6 made of BPTEOS is formed on the entire surface.

At this time, with the miniaturization of the semiconductor element, the aspect ratio between the gate electrodes 3a and 3b has a very high aspect ratio of 2.5 or more. Therefore, at the time of embedding the interlayer insulating film 6, FIG.
As shown in FIG. 3D, voids 7 are formed between the gate electrodes 3a and 3b in parallel with the gate electrodes 3a and 3b.

Next, as shown in FIGS. 6C and 6E, the gate electrode 3 is formed on the interlayer insulating film 6 by using a resist mask.
A contact hole 8 is opened between a and 3b. At this time,
As shown in FIG. 6E, a plurality of contact holes 8 (8a, 8b) are formed.

Next, as shown in FIGS. 7A and 7C, a conductive film 9 such as a polycrystalline silicon film, a W film and a TiN film is formed on the entire surface including the insides of the contact holes 8, 8a and 8b. At this time, as shown in FIG. 7C, the conductive film 9 naturally enters the void 7 as well.

Next, as shown in FIGS. 7B and 7D, the entire conductive film 9 is etched back or etched using a resist mask to complete a plug 10 as a second wiring. At this time, as shown in FIG. 7D, the plugs 10a, 1 formed in the plurality of contact holes 8a, 8b are formed.
Ob is connected by the conductive film 9 that has entered the void 7.

[0009]

Since the conventional method for forming a contact hole is as described above, FIGS.
As shown in (1), when the interlayer insulating film 6 is formed, there is a problem that voids 7 are easily generated between the gate electrodes 3a and 3b having a high aspect ratio.

Further, the interlayer insulating film 6 having the voids 7 formed therein
When the plug 10 is formed by etching the contact hole 8 and burying the conductive film 9, there is a problem that the conductive film 9 enters the void 7 and short-circuits between the plugs 10 a and 10 b. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a method of manufacturing a semiconductor device which can prevent a short circuit between wirings due to a void in an interlayer insulating film. And

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a contact hole after forming a contact hole and before forming a second wiring; Forming a thin insulating film on the entire surface including the insulating film, and performing anisotropic etching to remove the thin insulating film on the interlayer insulating film and at the bottom of the contact hole, and to form the thin insulating film only on the side wall in the contact hole. And a step of leaving the film.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, the step of embedding the interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more includes forming the first interlayer insulating film. Thereafter, a step of performing a first heat treatment, and forming a second interlayer insulating film thicker than the first interlayer insulating film on the first interlayer insulating film, and then lowering the temperature to a lower temperature than the first heat treatment. Performing a second heat treatment.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the first heat treatment temperature is set to 600 ° C. or more and 900 ° C. or less.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, the step of embedding the interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more includes the step of embedding the first interlayer insulating film having low viscosity. Forming, performing a high-pressure treatment on the first interlayer insulating film, and then performing a heat treatment; and forming a second interlayer insulating film on the first interlayer insulating film. It is prepared for.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device, the high-pressure processing is performed at a pressure of five times or more the atmospheric pressure.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the heat treatment temperature is 300 ° C. or higher.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, the low-viscosity insulating film is an SOG film.

In the method of manufacturing a semiconductor device according to claim 8 of the present invention, the step of forming the second wiring by burying the conductive film is performed by using the anisotropic film forming method over the entire surface including the inside of the contact hole. Forming a second conductive film on the entire surface of the first conductive film, and embedding the first and second conductive films in the contact holes to form the second conductive film. And a step of forming a wiring.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, the anisotropic film forming method is a sputter film forming method.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 and 2 are process sectional views showing a method for forming a contact portion according to the first embodiment of the present invention.

FIGS. 1 (a) and 1 (b) FIGS. 2 (a) (b) (c)
FIG. 1D is a cross-sectional view in a direction perpendicular to the gate electrode, and FIG.
(C) FIGS. 2 (e), (f), (g) and (h) are cross-sectional views in the direction parallel to the gate electrode, that is, the line AA ′. The description will be made sequentially according to the drawings.

First, as shown in FIG. 1A, a gate insulating film 2 and a conductive film are sequentially stacked on a silicon substrate 1 and a gate insulating film 2 and a conductive film are formed using a hard mask 4 made of a silicon nitride film. Are sequentially etched to form gate electrodes 3a and 3b as first wirings. Then, after forming a sidewall 5 made of an insulating film on the side walls of the hard mask 4 and the gate electrodes 3a and 3b, an interlayer insulating film 6 made of BPTEOS is formed on the entire surface.

At this time, with the miniaturization of the semiconductor element, the aspect ratio between the gate electrodes 3a and 3b has a very high aspect ratio of 2.5 or more. Therefore, when the interlayer insulating film 6 is buried, FIG.
As shown in (c), voids 7 which are vacancies due to poor embedding of the interlayer insulating film 6 are formed between the gate electrodes 3a and 3b in parallel with the gate electrodes 3a and 3b.

Next, as shown in FIGS. 2A and 2E, the gate electrode 3 is formed on the interlayer insulating film 6 by using a resist mask.
A contact hole 8 is opened between a and 3b. At this time,
The void 7 is exposed on the side wall in the contact hole 8. As shown in FIG. 2E, a plurality of contact holes 8 (8a, 8b) are formed.

Next, as shown in FIGS. 2B and 2F, about 10 to 10
A thin insulating film 11 of about 60 nm is formed.

Next, as shown in FIGS. 2C and 2G, etch back is performed by dry etching to remove the thin insulating film 11 on the interlayer insulating film 6 and the bottoms of the contact holes 8, 8a, 8b. , Contact holes 8, 8a, 8
Side wall 1 made of thin insulating film 11 on the side wall in b
Form 2 As a result, the contact holes 8, 8a,
The void 7 exposed in the side wall 8b
2 covered.

Next, as shown in FIGS. 2D and 2H, after a conductive film 9 such as a polycrystalline silicon film, a W film, and a TiN film is formed on the entire surface including the inside of the contact hole 8, the entire surface is etched back. Alternatively, etching using a resist mask is performed to complete the plug 10 as the second wiring.

At this time, as shown in FIG. 2H, since the voids 7 are covered with the sidewalls 12, the conductive film 9 can be prevented from entering the voids 7 and a plurality of contact holes can be formed. It is possible to prevent the plugs 10a and 10b formed in 8a and 8b from being connected and short-circuited.

Embodiment 2 FIG. FIG. 3 is a process sectional view showing a method for forming a contact portion according to the second embodiment of the present invention. 3A, 3B, 3C, and 3D are cross-sectional views in a direction perpendicular to the gate electrode, and FIG. 3E is a cross-sectional view in a direction parallel to the gate electrode, that is, a line AA '. is there. The description will be made sequentially according to the drawings.

First, as shown in FIG. 3A, a gate insulating film 2 and a conductive film are sequentially stacked on a silicon substrate 1 and a gate insulating film 2 and a conductive film are formed using a hard mask 4 made of a silicon nitride film. Are sequentially etched to form gate electrodes 3a and 3b as first wirings. Thereafter, sidewalls 5 made of an insulating film are formed on the side walls of the hard mask 4 and the gate electrodes 3a and 3b.

At this time, with the miniaturization of the semiconductor element, the aspect ratio between the gate electrodes 3a and 3b has a very high aspect ratio of 2.5 or more. Thereafter, a thin interlayer insulating film 13 as a first interlayer insulating film made of BPTEOS having a thickness of about 10 to 60 nm is formed on the entire surface. Thereby, the aspect ratio between the gate electrodes 3a and 3b can be reduced. However, in this state, the overhang portion 14 which is considered to be caused by the formation of the void is formed.

In order to solve this problem, as shown in FIG. 3B, a first heat treatment at a temperature of 600 ° C. or more and 900 ° C. or less is performed to reflow the overhang portion 14 so that the gate electrode 3a, 3b To the forward tapered thin interlayer insulating film 13
a is formed. Thus, the aspect ratio between the gate electrodes 3a and 3b can be reduced, and the gate electrodes 3a and 3b can be reduced.
The opening between the layers 3b is formed in a forward tapered shape so that the film to be formed next can be easily embedded.

Next, as shown in FIG. 3C, a second layer of BPTEOS of about 500 nm is formed on the thin interlayer insulating film 13a.
Is formed as a thick interlayer insulating film 15. Thereafter, the second heat treatment is performed at a temperature lower than that of the first heat treatment and at about 600 ° C.
Is performed to bury the interlayer insulating films 13a and 15 between the gate electrodes 3a and 3b.

Next, as shown in FIGS. 3D and 3E, a contact hole 8 is formed between the gate electrodes 3a and 3b on the interlayer insulating film 15 using a resist mask. At this time, as shown in FIG. 3E, a plurality of contact holes 8 (8a, 8b) are formed.

Thereafter, a conductive film such as a polycrystalline silicon film, a W film, and a TiN film is formed on the entire surface including the insides of the contact holes 8, 8a, and 8b. The plugs 10, 10a, and 10b, which are wirings of No. 2, are completed.

As described above, the interlayer insulating film is formed in two layers of the thin interlayer insulating film and the thick interlayer insulating film, and the first heat treatment temperature is set to the second heat treatment temperature so as not to affect the already formed elements. Since the burying characteristic of the interlayer insulating film is improved by setting the temperature higher than the heat treatment temperature, it is possible to prevent the formation of voids when burying the interlayer insulating film. Therefore, the plugs 10a and 10
Short circuit between b can be prevented.

Embodiment 3 FIG. 4 is a process sectional view showing a method for forming a contact portion according to the second embodiment of the present invention. 4A, 4B, 4C, and 4D are cross-sectional views in a direction perpendicular to the gate electrode, and FIG. 4E is a cross-sectional view in a direction parallel to the gate electrode, that is, a line AA '. is there. The description will be made sequentially according to the drawings.

First, as shown in FIG. 4A, a gate insulating film 2 and a conductive film are sequentially laminated on a silicon substrate 1 and a gate insulating film 2 and a conductive film are formed using a hard mask 4 made of a silicon nitride film. Are sequentially etched to form gate electrodes 3a and 3b as first wirings. Thereafter, sidewalls 5 made of an insulating film are formed on the side walls of the hard mask 4 and the gate electrodes 3a and 3b.

At this time, with the miniaturization of the semiconductor element, the aspect ratio between the gate electrodes 3a and 3b has a very high aspect ratio of 2.5 or more. Thereafter, a low-viscosity interlayer insulating film 16 such as, for example, a liquid SOG film is buried as a first interlayer insulating film up to the position of the hard mask 4. Many voids 7 are formed by bubbles in the low-viscosity interlayer insulating film 16.

Next, as shown in FIG. 4B, after applying a high pressure of at least 5 times the atmospheric pressure to the low-viscosity interlayer insulating film 16, a heat treatment at a temperature of 300 ° C. or more is performed to thereby lower the viscosity. The voids 7 caused by bubbles are eliminated from the interlayer insulating film 16 to form an interlayer insulating film 16a having increased viscosity.

Next, as shown in FIG. 4C, an interlayer insulating film 17 made of BPTEOS or the like as a second interlayer insulating film is formed on the interlayer insulating film 16a. Next, as shown in FIGS. 4D and 4E, a contact hole 8 is formed between the gate electrodes 3a and 3b on the interlayer insulating film 17 using a resist mask. At this time, as shown in FIG. 3E, a plurality of contact holes 8 (8a, 8b) are formed.

Thereafter, after a conductive film such as a polycrystalline silicon film, a W film, and a TiN film is formed on the entire surface including the insides of the contact holes 8, 8a and 8b, the entire surface is etched back or etched by a resist mask to perform a first etching. The plugs 10, 10a, and 10b, which are wirings of No. 2, are completed.

As described above, by using a low-viscosity insulating film as the first interlayer insulating film, the embedding characteristics can be improved,
Voids resulting from low viscosity are eliminated by high pressure and the viscosity is increased by heat treatment. Furthermore, the first
The aspect ratio between the gate electrodes is reduced by the interlayer insulating film to improve the burying characteristics of the second interlayer insulating film and to prevent voids from being formed in the interlayer insulating film. Therefore, it is possible to prevent a short circuit between the plugs due to the void.

Embodiment 4 In the first embodiment, the case where the side wall inside the contact hole is protected with a thin insulating film to cover the void is described. Here, the case where the void is covered with the conductive film will be described.

FIG. 5 is a process sectional view showing a method for forming a contact portion according to the fourth embodiment of the present invention. FIG. 5 (a)
(B), (c) and (d) are cross-sectional views in a direction perpendicular to the gate electrode, and FIGS. 5 (e), (f), (g) and (h) show directions parallel to the gate electrode, that is, line AA ′. FIG. The description will be made sequentially according to the drawings.

First, the interlayer insulating film 6 is buried in the same manner as in the first embodiment. This corresponds to the first embodiment.
1 (a) and 1 (b), and a detailed description thereof will be omitted. At this time, a void 7 which is a hole due to a poor embedding of the interlayer insulating film 6 is formed between the gate electrodes 3a and 3b in parallel with the gate electrodes 3a and 3b.

Next, as shown in FIGS. 5A and 5E, the gate electrode 3 is formed on the interlayer insulating film 6 by using a resist mask.
A contact hole 8 is opened between a and 3b. At this time,
The void 7 is exposed on the side wall in the contact hole 8. Further, as shown in FIG. 2E, a plurality of contact holes 8 (8a, 8b) are formed.

Next, as shown in FIGS. 5 (b) and 5 (f), the first conductive film is formed by an anisotropic film forming method such as sputter deposition so as to cover the void 7 on the entire surface including the void 7. A film of TiN or the like is formed to a thickness of about 10 to 100 nm. The void 7 exposed in the contact holes 8, 8a, 8b is covered with the thin conductive film 18.

Next, as shown in FIGS. 5C and 5G, a conductive film 9 such as a polycrystalline silicon film, a W film, or a TiN film as a second conductive film is formed by an isotropic film forming method. It is formed on the entire surface including the inside.

Next, as shown in FIGS. 5D and 5H, the entire thin film conductive film 18 and conductive film 9 are etched back or etched using a resist mask to form a second wiring. The plug 10 is completed.

At this time, as shown in FIG. 5B, since the side wall of the void 7 is covered with the thin conductive film 18,
The conductive film 9 can be prevented from entering the void 7, and the plugs 10a and 10b formed in the plurality of contact holes 8a and 8b can be prevented from being short-circuited due to connection.

This arrangement has the same effect as that of the first embodiment, and is also effective when a plug made of metal having poor adhesion to the insulating film is formed. Further, in the first embodiment, the etching for exposing the bottom of the contact hole is performed twice, but here, the etching may be performed once, and the damage to the silicon substrate may be reduced.

[0054]

As described above, according to the present invention, a thin insulating film is formed on the entire surface including the inside of the contact hole after the step of forming the contact hole and before the step of forming the second wiring. And a step of performing anisotropic etching to remove the thin insulating film on the interlayer insulating film and at the bottom of the contact hole to leave the thin insulating film only on the side wall in the contact hole. Therefore, the voids exposed on the inner wall of the contact hole can be closed before the formation of the conductive film. As a result, it is possible to prevent the conductive film from entering the void, and to prevent short-circuit due to connection of plugs formed in the plurality of contact holes.

Further, the step of embedding the interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more includes the step of forming a first interlayer insulating film and then performing a first heat treatment. Forming a second interlayer insulating film thicker than the first interlayer insulating film on the first interlayer insulating film, and then performing a second heat treatment at a lower temperature than the first heat treatment. So
The embedding characteristics of the interlayer insulating film can be improved, and the formation of voids in the interlayer insulating film can be prevented.

Further, the first heat treatment temperature is 600 ° C. or more and 9
Since the temperature is set to 00 ° C. or lower, the overhang portion can be reflowed to form a forward tapered thin interlayer insulating film between the gate electrodes, thereby facilitating the embedding of the next film to be formed. it can.

Further, the step of embedding the interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more includes the step of forming the first interlayer insulating film having low viscosity and the step of forming the first interlayer insulating film. , A step of performing a heat treatment after performing a high-pressure treatment, and a step of forming a second interlayer insulating film on the first interlayer insulating film, so that voids are formed in the interlayer insulating film. It is possible to prevent the short circuit between the plugs due to the voids.

Since the high-pressure treatment is performed at a pressure of 5 times or more the atmospheric pressure, voids due to bubbles can be eliminated from the low-viscosity interlayer insulating film.

Further, since the heat treatment temperature is set to 300 ° C. or more, the viscosity of the low-viscosity interlayer insulating film can be increased, and the contact hole can be easily formed in a later step.

Since the low-viscosity insulating film is an SOG film, it can be easily formed.

Further, the step of forming the second wiring by embedding the conductive film includes the step of forming the first conductive film on the entire surface including the inside of the contact hole by using the anisotropic film-forming method. Forming a second conductive film over the entire surface of the conductive film and forming the second wiring by embedding the first and second conductive films in the contact holes. The first conductive film can close a void exposed on the inner wall of the contact hole. The second conductive film can be prevented from entering the void, and short-circuit due to connection of plugs formed in the plurality of contact holes can be prevented.

Further, since the anisotropic film forming method is a sputter film forming method, the conductive film can be formed only on the surface of the void, and it is possible to prevent the conductive film from entering the void.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for forming a contact portion according to Embodiment 1 of the present invention;

FIG. 2 is a process sectional view illustrating a method for forming a contact portion according to the first embodiment of the present invention.

FIG. 3 is a process sectional view illustrating a method for forming a contact portion according to the second embodiment of the present invention.

FIG. 4 is a process sectional view illustrating a method for forming a contact portion according to a third embodiment of the present invention.

FIG. 5 is a process sectional view illustrating a method for forming a contact portion according to a fourth embodiment of the present invention.

FIG. 6 is a process sectional view showing a conventional method of forming a contact portion.

FIG. 7 is a process sectional view showing a conventional method of forming a contact portion.

[Explanation of symbols]

1 silicon substrate, 3a, 3b gate electrode, 6,1
3,13a, 15,16,16a, 17 interlayer insulating film,
7 void, 8, 8a, 8b contact hole, 9,
18 conductive film, 10, 10a, 10b plug, 11
Thin insulating film, 12 sidewalls, 14 overhangs.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB18 BB30 CC01 DD04 DD06 DD16 DD19 DD22 DD28 DD37 EE12 FF16 FF21 GG14 5F033 HH04 HH19 HH33 NN01 NN06 NN07 NN29 PP15 QQ31 QQ37 QQ74 TT04 WW09 WW05

Claims (9)

[Claims] A step of forming a plurality of first wirings on a silicon substrate; a step of embedding an interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more; A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole between the first wirings by etching; and a step of forming a second wiring by burying a conductive film in the contact hole. After the step of forming the hole and before the step of forming the second wiring, a step of forming a thin insulating film on the entire surface including the inside of the contact hole, and performing anisotropic etching to form a film on the interlayer insulating film And removing the thin insulating film at the bottom of the contact hole to leave the thin insulating film only on the side wall in the contact hole. Production method. A step of forming a plurality of first wirings on a silicon substrate; a step of embedding an interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more; The method for manufacturing a semiconductor device, comprising: a step of forming a contact hole between the first wirings by etching; and a step of forming a second wiring by burying a conductive film in the contact hole. The step of embedding an interlayer insulating film between the first wirings having a ratio of 2.5 or more includes forming the first interlayer insulating film after forming the first interlayer insulating film.
Performing a first heat treatment, forming a second interlayer insulating film thicker than the first interlayer insulating film on the first interlayer insulating film, and then forming a second heat treatment at a lower temperature than the first heat treatment. And a step of performing a heat treatment of the semiconductor device. 3. The first heat treatment temperature is 600 ° C. or more and 900 ° C.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the temperature is lower than or equal to ° C. 4. A step of forming a plurality of first wirings on a silicon substrate; a step of embedding an interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more; The method for manufacturing a semiconductor device, comprising: a step of forming a contact hole between the first wirings by etching; and a step of forming a second wiring by burying a conductive film in the contact hole. The step of embedding the interlayer insulating film between the first wirings having a ratio of 2.5 or more includes the step of forming a low-viscosity first interlayer insulating film and the step of performing high-pressure treatment on the first interlayer insulating film. A method of manufacturing a semiconductor device, comprising: a step of performing a heat treatment after the application; and a step of forming a second interlayer insulating film on the first interlayer insulating film. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the high-pressure processing is processing at a pressure of 5 times or more of the atmospheric pressure. 6. The method according to claim 4, wherein the heat treatment temperature is 300 ° C. or higher. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the first interlayer insulating film having low viscosity is an SOG film. 8. A step of forming a plurality of first wirings on a silicon substrate; a step of embedding an interlayer insulating film between the first wirings having an aspect ratio of 2.5 or more; A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole between the first wirings by etching; and a step of forming a second wiring by burying a conductive film in the contact hole. The step of forming the second wiring by embedding the film includes the step of forming a first conductive film on the entire surface including the inside of the contact hole by using an anisotropic film forming method, and the step of forming an entire surface on the first conductive film. Forming a second conductive film in the contact hole and burying the first and second conductive films in the contact hole to form the second wiring. Manufacturing method. 9. The method according to claim 8, wherein the anisotropic film forming method is a sputter film forming method.