JP2001319802A - Chip laminated thermistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress resistance deviation of a chip laminated thermistor which is constituted by laminating internal electrodes upon another through a thermistor layer by reducing the variation of the overlapped area between the internal electrodes. SOLUTION: This chip laminated thermistor is constituted by arranging a first internal electrode 8 having a pull-out section at one end of the thermistor layer 2, and a second internal electrode 9 having a pull-out section at the other end of the thermistor layer 2 in parallel with each other on the same surface of the thermistor layer 2, by changing the positions of the electrodes 8 and 9 arranged in parallel with each other through the thermistor layer 2. Then resistance variation of the thermistor can be reduced by reducing the variation of the overlapped area between the electrodes 8 and 9, even when an internal electrode layer 1 is laminated in a deviated state through the thermistor layer 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type multilayer thermistor for surface mounting used for temperature sensors, temperature compensation, and the like.

[0002]

2. Description of the Related Art FIG. 15 is a plan sectional view of a conventional chip type thermistor, FIG. 16 is a sectional view taken along line JJ in FIG.
FIG. 17 is a plan sectional view for explaining the problem of the conventional example.

[0005] In FIGS. 15 to 17, reference numeral 51 denotes a laminate, which is formed by alternately laminating rectangular internal electrodes 53, 54 so as to overlap each other with a thermistor layer 52 interposed therebetween. One end and the other end of the laminate 51 are drawn out, and are electrically connected to external electrodes 55 and 56 formed on opposing end faces of the laminate 51. The chip-type laminated thermistor obtains a desired resistance value by changing the thickness of the thermistor layer 52 between the internal electrodes 53 and 54 and the overlapping area between the internal electrodes 53 and 54, or by changing the number of effective layers. It is.

[0004]

However, in the above-mentioned conventional chip-type multilayer thermistor, the internal electrodes 53, 54 are misaligned due to overlapping displacement at the time of lamination.
There is a problem in that the overlapping area between the 54 changes and the resistance value varies.

FIG. 17 shows the displacement of the first internal electrode 53 and the second internal electrode 54 in a conventional chip type thermistor. When the first internal electrode 53 and the second internal electrode 54 are accurately laminated without being shifted, the overlapping area between the internal electrodes 53 and 54 becomes a desired value and a desired resistance value is obtained. In FIG. 17, the second internal electrode 54 is amm in the L (length) direction.
The overlapping area between the internal electrodes changes from a desired value, and the specified value of the resistance cannot be obtained.

The present invention solves the above-mentioned problem. Even if the internal electrodes 53 and 54 stacked via the thermistor layer 52 are shifted in position, the overlapping area between the internal electrodes 53 and 54 changes. An object of the present invention is to provide a chip-type laminated thermistor having a difficult structure and capable of reducing variation in resistance value.

[0007]

Means for Solving the Problems To achieve the above object, the present invention has the following arrangement.

According to a first aspect of the present invention, there is provided a chip having a laminated body formed by laminating an internal electrode layer and a thermistor layer, and having an external electrode connected to the internal electrode on an outer surface of the laminated body. In the laminated thermistor, a first internal electrode having a lead portion formed at one end of the thermistor layer on the same surface of the thermistor layer, and a second internal electrode having a lead portion formed at the other end of the thermistor layer. The first internal electrode and the second internal electrode are arranged side by side, and the first internal electrode and the second internal electrode are overlapped by replacing the juxtaposed positions of the first internal electrode and the second internal electrode via the thermistor layer. Even if the first internal electrode and the second internal electrode are displaced in the direction of one end or the other end of the thermistor layer and stacked, the overlapping area between the first and second internal electrodes is reduced. Because it can be kept constant Kone does not change, it has the effect of suppressing the variation in the resistance value.

According to a second aspect of the present invention, the width of one of the first internal electrode and the second internal electrode overlapping via the thermistor layer is formed smaller than the width of the other. A chip-type laminated thermistor, whereby even if the first and second internal electrodes are laminated with a slight displacement in the width direction of the internal electrodes, the end of the width of the one internal electrode is changed to the other internal electrode; Since the overlapping area between the internal electrodes can be kept constant within a range that does not protrude from the width end, the resistance value does not change and has an effect of suppressing variation in the resistance value.

According to a third aspect of the present invention, an even number of first internal electrode layers and second internal electrode layers are alternately arranged on the same surface of the thermistor layer. The first and second internal electrodes are displaced in the direction of one end or the other end of the thermistor layer, and the overlapping area between the first and second internal electrodes is reduced. Since the resistance value can be kept constant, the resistance value does not change, has an effect of suppressing the variation of the resistance value, and further, the resistance value can be increased by increasing the number of the even-numbered pairs, so that the thickness of the ceramic layer and the like can be increased. There is an effect that various resistance values can be configured without changing the shape of each internal electrode.

According to a fourth aspect of the present invention, there is provided the chip-type multilayer thermistor according to the first aspect, wherein a plurality of internal electrode layers and thermistor layers are laminated to form a laminate. Said first internal electrode in the direction of the edge,
Even if the second internal electrodes are displaced in position and stacked, the overlapping area between the first and second internal electrodes can be kept constant, so that the resistance value does not change, and the effect of suppressing the variation in the resistance value is reduced. Further, since the resistance value can be decreased by increasing the number of the laminations, it is possible to configure various resistance values without changing the thickness of the ceramic layer and the shape of each internal electrode, and particularly small. This has the effect that a chip-type laminated thermistor having a resistance value can be easily obtained with reduced variation.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, the first embodiment of the present invention will be described with reference to the first embodiment.

FIG. 1 is a plan sectional view of a chip-type laminated thermistor according to Embodiment 1 of the present invention, FIG. 2 is a sectional view of the chip-type laminated thermistor of Embodiment 1 taken along the line AA in FIG. 1, and FIG. FIG. 4 is a cross-sectional view of the chip-type multilayer thermistor according to the first embodiment taken along line BB in FIG. 1, FIG. 4 is an external perspective view of the chip-type multilayer thermistor according to the first embodiment, and FIG. It is an exploded perspective view in a manufacturing process of a lamination thermistor.

1 to 5, reference numeral 1 denotes an internal electrode layer;
Is a thermistor layer made of a semiconductor porcelain of manganese-cobalt or the like and having a negative resistance temperature characteristic. These layers are laminated to form a laminate 3, and the outer surface of the laminate 3 is connected to the internal electrode layer 1. A pair of external electrodes 4 and 5 are formed. The internal electrode layer 1 includes a first internal electrode 8 having a lead portion 6 formed at one end of the thermistor layer 2 and a second internal electrode 9 having a lead portion 7 formed at the other end of the thermistor layer 2. The first internal electrode 8 and the second internal electrode 9 are replaced by replacing the positions of the first internal electrode 8 and the second internal electrode 9 in the juxtaposition direction with the thermistor layer 2 interposed therebetween. 9 are overlapped with each other.

Thus, even if the mutual positions of the upper and lower internal electrode layers 1 are shifted in the L direction via the ceramic layer 2, the overlapping area between the first internal electrode 8 and the second internal electrode 9 is kept constant. Since the resistance value can be maintained, the resistance value does not change, and has an effect of suppressing variation in the resistance value.

The manufacturing method of the chip-type laminated thermistor configured as described above will be described below.

First, a material powder composed of, for example, a manganese-cobalt system is prepared, and a binder composition is mixed with the material powder, and a thermistor green sheet 30 having a thickness of 30 μm is prepared using a molding machine.

Next, on the same surface of the thermistor green sheet 30, the first internal electrode 7 and the second internal electrode 8
The conductive paste is printed in a desired shape so that a plurality of
The internal electrode 8 and the second internal electrode 9 are rewritten at the juxtaposed positions and stacked so as to overlap each other, and a plurality of thermistor green sheets 31 are stacked and pressed on the upper and lower sides so as to have a required thickness. Obtain a green sheet laminate. Then, the obtained green sheet laminate is cut and fired at a temperature of 1200 ° C. for 2 hours to obtain the laminate 3.

Next, a conductive paste is applied to both end surfaces of the laminate 3 and baked to form a pair of external electrodes 4 and 5 to form a pair of external electrodes 4.
A 608 type chip laminated thermistor was manufactured.

Next, the resistance value of the obtained chip type laminated thermistor of the 1608 type was measured in an oil bath at 25 ° C., and the results are shown in Table 1 as a first embodiment as compared with a conventional example. Show. The variation is represented by a coefficient of variation (standard deviation / average value).

[0021]

[Table 1]

As shown in Table 1, the chip type thermistor of the present invention can reduce the variation in resistance value as compared with the conventional chip type thermistor.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to Embodiment 2. The basic configuration and the manufacturing method are described in Embodiment 1.
Here, a detailed description is omitted here, and a characteristic portion will be described.

FIG. 6 is a plan sectional view of a chip type thermistor according to a second embodiment of the present invention, FIG. 7 is a sectional view taken along the line CC of FIG. 6 of the second embodiment, and FIG. It is -D sectional drawing.

6 to 8, reference numeral 10 denotes a first internal electrode, 11 denotes a second internal electrode, and the width 18 of the first internal electrode 10 is larger than the width 19 of the second internal electrode 11. It is formed narrow.

As a result, the variation in the overlapping area between the first internal electrode 10 and the second internal electrode 11 can be suppressed, so that the variation in resistance can be reduced.

Next, a 1608 type chip-type laminated thermistor having the above configuration is formed by using the same manufacturing method as that of the first embodiment, and the resistance value is measured in an oil bath at 25 ° C. The results are shown in Table 1 as Embodiment 2. The variation of the resistance value is represented by a coefficient of variation (standard deviation / average value).

As shown in Table 1, the chip-type multilayer thermistor of the present invention can reduce the variation in resistance value as compared with the conventional chip-type multilayer thermistor.

(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to Embodiment 3. The basic configuration and the manufacturing method are described in Embodiment 1.
Here, a detailed description is omitted here, and a characteristic portion will be described.

FIG. 9 is a plan sectional view of a chip type thermistor according to a third embodiment of the present invention, FIG. 10 is a sectional view taken along the line EE in FIG. 9 of the third embodiment, and FIG. -F
It is sectional drawing.

9 to 11, reference numerals 12 and 13 denote the first.
Are internal electrodes 14 and 15, which are second internal electrodes. The even internal electrodes are composed of two sets of first internal electrodes 12, 13 and second internal electrodes 14, 15 alternately on the same surface of the thermistor layer 2. The pairs are formed side by side.

As a result, the overlapping area between the internal electrodes can be kept constant, so that the resistance value does not change and has the effect of suppressing variations.

Next, a 1608 type chip-type laminated thermistor having the above structure is formed by using the same manufacturing method as that of the first embodiment, and the resistance value is measured in a 25 ° C. oil bath. The results are shown in Table 1 as Embodiment 3. The variation of the resistance value is represented by a coefficient of variation (standard deviation / average value).

As shown in Table 1, the chip-type multilayer thermistor of the present invention can reduce the variation in resistance value as compared with the conventional chip-type multilayer thermistor.

(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to Embodiment 4. The basic configuration and the manufacturing method are described in Embodiment 1.
Here, a detailed description is omitted here, and a characteristic portion will be described.

FIG. 12 is a plan sectional view of a chip type thermistor according to a fourth embodiment of the present invention, FIG. 13 is a sectional view taken along line GG of FIG. 12 of the fourth embodiment, and FIG. It is -H sectional drawing.

In FIGS. 12 to 14, reference numeral 16 denotes a first internal electrode, and 17 denotes a second internal electrode.
The first internal electrode 16 having a lead portion formed at one end of the thermistor layer 2 on the same surface of the thermistor layer 2;
Are arranged side by side with the second internal electrodes 17 each having a lead-out portion formed at the other end thereof.
And 17 constitute a chip-type laminated thermistor having three thermistor layers (effective layers).

As a result, the overlapping area between the internal electrodes can be kept constant, so that the resistance value does not change and has the effect of suppressing variations.

Next, a 1608 type chip-type laminated thermistor having the above configuration is formed using the same manufacturing method as in the first embodiment, and the resistance value is measured in a 25 ° C. oil bath. The results are shown in Table 1 as Embodiment 4. The variation of the resistance value is represented by a coefficient of variation (standard deviation / average value).

As shown in Table 1, the chip type thermistor according to the fourth embodiment of the present invention can reduce the variation in the resistance value as compared with the conventional chip type thermistor.

[0041]

As described above, according to the present invention, even if the internal electrodes are shifted and laminated, the variation in the overlapping area between the internal electrodes can be reduced, and the variation in the resistance value can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional plan view of a chip-type laminated thermistor according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view of the chip-type laminated thermistor according to the first embodiment taken along line AA in FIG. 1;

FIG. 3 is a sectional view of the chip-type laminated thermistor according to the first embodiment taken along line BB in FIG. 1;

FIG. 4 is an external perspective view of the chip-type laminated thermistor of the first embodiment.

FIG. 5 is an exploded perspective view in a manufacturing process of the chip-type laminated thermistor of the first embodiment.

FIG. 6 is a plan sectional view of the chip-type laminated thermistor of the second embodiment.

FIG. 7 is a cross-sectional view of the chip-type laminated thermistor according to the second embodiment taken along line CC in FIG. 6;

FIG. 8 is a sectional view of the chip-type laminated thermistor according to the second embodiment taken along line DD in FIG. 6;

FIG. 9 is a plan sectional view of the chip-type laminated thermistor of the third embodiment.

FIG. 10 is a sectional view of the chip-type laminated thermistor according to the third embodiment taken along line EE in FIG. 9;

FIG. 11 is a sectional view of the chip-type laminated thermistor according to the third embodiment taken along line FF in FIG. 9;

FIG. 12 is a plan sectional view of the chip-type laminated thermistor of the fourth embodiment.

FIG. 13 is a sectional view of the chip-type laminated thermistor according to the fourth embodiment taken along line GG in FIG.

FIG. 14 is a sectional view taken along the line HH in FIG. 12 of the chip-type laminated thermistor according to the fourth embodiment;

FIG. 15 is a plan sectional view of a conventional chip-type laminated thermistor.

FIG. 16 is a sectional view of the conventional chip-type laminated thermistor taken along the line JJ in FIG.

FIG. 17 is a cross-sectional plan view illustrating the problem of the conventional chip-type laminated thermistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal electrode layer 2 Thermistor layer 3 Laminated body 4,5 External electrode 6,7 Leader 8,10,12,13,16 1st internal electrode 9,11,14,15,17 2nd internal electrode 18, 19 Electrode width

Claims (4)

[Claims] 1. A chip-type laminated thermistor having a laminated body formed by laminating an internal electrode layer and a thermistor layer, and having an external electrode connected to the internal electrode on the outer surface of the laminated body, wherein the same thermistor layer is used. A first internal electrode having a lead portion formed at one end of the thermistor layer and a second internal electrode having a lead portion formed at the other end of the thermistor layer are provided side by side on the surface, and the other end of the thermistor layer is provided through the thermistor layer. A chip-type multilayer thermistor in which the first internal electrode and the second internal electrode are overlapped by replacing the juxtaposed positions of the first internal electrode and the second internal electrode. 2. The chip-type multilayer thermistor according to claim 1, wherein the width of one of the first internal electrode and the second internal electrode overlapping via the thermistor layer is smaller than the other. 3. An even number of first internal electrodes and second internal electrodes alternately arranged on the same surface of the thermistor layer.
The chip-type laminated thermistor according to 1. 4. The chip-type multilayer thermistor according to claim 1, wherein a plurality of internal electrode layers and thermistor layers are laminated to form a laminate.