JP2001358105A - Forming method of embedded wiring, cmp device, and semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming embedded wiring of flat surface by preventing dishing at chemical-mechanical polishing, independently of layout, such as wiring width, density level of wiring or the like. SOLUTION: The method includes a first process, where a channel for embedded wiring, is formed at a flat interlayer insulating film 4 formed on a silicon substrate 1, a second process where a barrier metal 6 and Cu films 7 and 7a which are to be a main wiring, a third process where an unwanted Cu film on the interlayer insulating film 4 is removed, with a thin skin left out, by a first chemical-mechanical polishing, a fourth process where only the pellicle- state Cu film is removed by etching until the barrier metal 6 is exposed, and a fifth process where an unwanted barrier metal is removed by a second chemical-mechanical polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a buried wiring using a CMP (Chemical Mechanical Polishing) method, a CMP apparatus used for the method for forming a buried wiring, a semiconductor device, and a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, as a method of forming an embedded wiring by using CMP, for example, there is a method disclosed in Japanese Patent Application Laid-Open No. 6-120219. In this conventional example, as shown in FIGS. 8 and 9, for example, a silicon oxide film composed of a thermal oxide film 27, a nitride film 28 and an interlayer insulating film 29 on a silicon substrate 26 is first subjected to a photolithographic dry etching process. A groove for wiring is processed, then a barrier metal 30 and Cu films 31, 31a are buried in the groove, and finally, an unnecessary Cu film and barrier metal are removed by CMP to form a buried wiring.

As another conventional example, for example, Japanese Patent Application Laid-Open No. 2000-12543 and Japanese Patent Application Laid-Open No. 9-32639.
There is one disclosed in Japanese Patent Laid-Open No. 2 (Kokai) Publication. In this conventional example, CM
The wiring / plug formation by P is divided into two steps. In the first step, the target metal film is roughly removed under the condition of a high polishing rate, and in the second step, the processing is performed under the condition of a low polishing rate. This is to reduce the recess of the wiring / plug.

However, the above-mentioned conventional method for forming an embedded wiring has the following problems. First, the method disclosed in Japanese Patent Application Laid-Open No. HEI 6-120219 is a basic flow of forming an embedded wiring, but in reality, as shown in FIGS. there were.

That is, FIG. 8 shows a case where the polishing rate of the Cu film is high but the polishing rate of the barrier metal is low.
This indicates that dishing occurs when the polishing rate of the film and the barrier metal is high but the polishing rate of the oxide film is low. This is a slurry (abrasive) used for CMP
However, although the Cu film is polished quickly, the barrier metal or the oxide film is controlled in composition so that it is difficult to polish.
This is because, when a different kind of film other than the u film is exposed on the substrate surface, only the Cu film is selectively polished and the wiring is dented. This depression is caused by the deformation of the polishing cloth acting on the wafer. The larger the wiring width, the larger the amount of deformation of the polishing cloth, and therefore the greater the dishing amount.

Further, the methods disclosed in Japanese Patent Application Laid-Open Nos. 2000-12543 and 9-326392 disclose CMs in order to substantially solve the problems of the conventional example.
The formation of wiring and plugs by P is divided into two steps, and it is possible to reduce the amount of wiring and plugs after polishing by devising the slurry. There is a problem that dents cannot be avoided.

The present invention is directed to a method of forming a buried wiring having a flat surface, a CMP apparatus, a semiconductor device, and a method of manufacturing the same by preventing dishing by CMP irrespective of a layout such as a wiring width and a wiring density. The purpose is to provide.

[0007]

According to a first aspect of the present invention, there is provided a method of forming a buried wiring, comprising: forming a groove for a buried wiring in a flat interlayer insulating film formed on a semiconductor substrate; A second step of forming a barrier metal and a Cu film serving as a main wiring in the trench, and removing unnecessary Cu on the interlayer insulating film;
A third step of removing the film by a first chemical mechanical polishing until a thin film remains, and a fourth step of removing only the Cu film in the thin film state by etching until the barrier metal is exposed, And a fifth step of removing unnecessary barrier metal by the second chemical mechanical polishing.

According to a second aspect of the present invention, in the method of the first aspect, the barrier metal is a material containing Ta or TaN, and the etching of the Cu film has a hydrogen ion concentration. This is performed using a chemical solution of an acidic solution having a pH of 6 or less and in which the barrier metal is not easily etched.

According to a third aspect of the present invention, in the method of the first aspect, the barrier metal is a material containing Ta or TaN, and the etching of the Cu film is performed with the Cu film. Gas phase etching is performed using a gas that is a chemical reaction active gas and is difficult to etch the barrier metal.

According to a fourth aspect of the present invention, in the method of forming a buried interconnect according to any one of the first to third aspects, the etching of the Cu film is performed in a cleaning unit in a CMP apparatus, so that the first etching is performed. From the chemical mechanical polishing (Cu film polishing) to the end of the second chemical mechanical polishing (barrier metal polishing) in one CMP apparatus.

According to a fifth aspect of the present invention, there is provided a method of forming a buried interconnect according to any one of the first to fourth aspects, wherein a change in the wafer surface of the semiconductor substrate is detected by light detection when the Cu film is etched. And the end point of the etching is applied by the exposure of the barrier metal.

According to a sixth aspect of the present invention, there is provided a method of forming a buried interconnect according to the third aspect of the present invention, wherein an end point of etching is applied when the barrier metal is exposed by detecting the Ta emission spectrum. .

According to a seventh aspect of the present invention, there is provided a method of forming an embedded wiring according to any one of the first to sixth aspects, wherein
Using a sputter etch by ions, Cu
This is to remove the film.

According to a ninth aspect of the present invention, in the method of any one of the first to seventh aspects, the second chemical mechanical polishing is performed such that the thickness of the barrier metal is reduced from the surface of the semiconductor substrate. Etching is performed until the Cu film is recessed by an amount, and the polishing is performed using a polishing agent or polishing conditions for selectively polishing only the barrier metal.

According to a ninth aspect of the present invention, in the method of any one of the first to eighth aspects, the second chemical mechanical polishing is performed by removing a polishing rate of the Cu film and the interlayer insulating film. And the polishing is performed using a polishing agent or polishing conditions in which only the polishing rate of the barrier metal is increased to both of them.

According to a tenth aspect of the present invention, there is provided a CMP apparatus comprising: a barrier metal filling a trench for an embedded wiring formed in an interlayer insulating film on a semiconductor substrate;
A first polishing unit for polishing the Cu film until a thin layer remains, a first cleaning unit for cleaning a required amount of the Cu film, and a second polishing unit for removing unnecessary portions of the barrier metal And a second cleaning unit for cleaning the abrasive adhered to the semiconductor substrate.

An CMP apparatus according to an eleventh aspect of the present invention is the CMP apparatus according to the tenth aspect, further comprising light detecting means for detecting a change in the wafer surface of the semiconductor substrate and detecting an end point of the etching when the barrier metal is exposed. It is a thing.

According to a twelfth aspect of the present invention, there is provided a semiconductor device having a Cu film serving as a barrier metal and a main wiring formed in a trench for a buried wiring provided in a flat interlayer insulating film on a semiconductor substrate. It has a flat embedded wiring.

According to a thirteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a trench for buried wiring in a flat interlayer insulating film formed on a semiconductor substrate; A second step of forming a Cu film serving as a main wiring, a third step of removing the unnecessary Cu film on the interlayer insulating film by a first chemical mechanical polishing until a thin skin is left, and A buried wiring is formed using a fourth step of removing only the Cu film in a state by etching until the barrier metal is exposed and a fifth step of removing unnecessary barrier metal by a second chemical mechanical polishing. At least.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. Embodiment 1 FIG. FIGS. 1 and 2 are process diagrams showing Embodiment 1 of the present invention. With reference to FIGS. 1 and 2, a method of forming a buried wiring in which dishing is suppressed will be described. Here, the structure below the embedded wiring is omitted. First, as shown in FIG. 1A, on a silicon substrate 1 as a semiconductor substrate, a thermal oxide film 2 is formed to a thickness of 300 nm, a nitride film 3 is formed to a thickness of 60 nm, and an interlayer insulating film 4 is formed to a thickness of 400 nm. Next, as shown in FIG. 1B, the interlayer insulating film 4 is processed by a photolinography step and an anisotropic etching step to form a groove for an embedded wiring. At this time, the nitride film 3 is used as an etching stopper layer of the interlayer insulating film 4.

Next, as shown in FIG. 1 (c), a Ta film serving as a barrier metal 6 is formed on the pattern by sputtering.
N (tantalum nitride) is 35 nm and a plating seed layer, ie, a Cu film (a Cu thin film serving as a seed at the start of electrolytic plating) 7
Is deposited to a thickness of 200 nm. Note that Ta (tantalum) may be used instead of TaN as the material of the barrier metal 6. Then, a Cu film 7a is formed to a thickness of 600 nm on the silicon substrate 1 by using an electrolytic plating method.

Next, as shown in FIG. 2 (a), the Cu films 7 and 7a on the silicon substrate 1 are polished by a CMP method (chemical mechanical polishing) to remove about 90% of the original film thickness. Stop polishing with. Since the Cu films 7 and 7a are left on the entire surface of the silicon substrate 1 and the barrier metal 6 is not yet exposed, dishing does not occur and a flat surface is obtained.

Next, as shown in FIG. 2 (b), the silicon substrate 1 is treated with a chemical solution of an acidic solution having a hydrogen ion concentration of pH 6 or less and the barrier metal 6 is difficult to be etched, such as sulfuric acid having a concentration of 5% or less. Etching is performed using sulfuric acid + hydrogen peroxide or the like. Since TaN is very difficult to etch with sulfuric acid, only the Cu film is selectively etched.
The etching is stopped, and the etching is stopped when the barrier metal 6 is exposed on the entire wafer.

Then, as shown in FIG.
Using MP, all unnecessary barrier metal 6 on the silicon substrate 1 is removed, and a flat embedded wiring is formed. The slurry (abrasive) used at this time is T
The polishing rate ratio of aN is 1 or more (TaN is more easily polished).

As for the method of selectively removing only the Cu film from the time point of FIG. 2A, in addition to the wet etching by etching of the Cu film, the method of removing C
gas phase etching using gas having high reactivity with u film, A
Physical sputter etching using r ions can also be considered. In the vapor phase etching, an end point (end point) of the etching can be applied by detecting an emission spectrum of Ta. Although the above description is about single embedding, the same can be applied to formation of dual embedding.

FIG. 3 is a configuration diagram showing a CMP apparatus having a plurality of polishing units and a cleaning unit used in the first embodiment. In the figure, 8 is a wafer cassette, 9 and 1
Reference numeral 0 denotes a rotary platen, 11 and 12 denote polishing heads, 13 denotes a transfer robot, and 14, 14a and 14b denote cleaning units.

FIG. 4 shows the polishing unit or polishing head 11 and the rotary platen 9 shown in FIG.
FIG. 2 is a schematic view showing a specific example of a portion of a rotary platen 2.
In the figure, 15 is a polishing head, 16 is a nozzle, 17 is a slurry, 18 is a polishing cloth, and 19 is a rotary platen.

FIG. 5 shows a cleaning unit for cleaning the polished wafer, that is, the cleaning units 14 and 14 in FIG.
It is the schematic which shows the specific example of 14a and 14b. In the figure,
20 is a sponge brush, 21 is a silicon substrate, 22 is a chemical liquid nozzle, and 23 is a pure water nozzle. When such a CMP apparatus is used, all of the above-described processing can be performed in the CMP apparatus by putting a chemical for etching the Cu film into one of the cleaning units.

FIG. 6 schematically shows the flow of a wafer when the above processing is performed. First, the Cu film is polished by one polishing unit so as to have the shape shown in FIG. 2A (FIG. 6A). Next, in one of the cleaning units, C
The required amount of the u film is wet-etched,
Create the shape of (b). Unnecessary barrier metal is removed in the second polishing unit to form the shape shown in FIG. In other words, in the second chemical mechanical polishing in the second polishing unit, etching is performed from the surface of the silicon substrate 21 until the Cu film is recessed by the thickness of the barrier metal, and only the barrier metal is selectively polished. This is performed using an abrasive or polishing conditions. Thereafter, the slurry attached to the wafer is washed by the remaining washing unit, and the wafer is returned to the cassette.

The second chemical mechanical polishing is performed by using a polishing agent or polishing conditions in which the polishing rate of the Cu film and the interlayer insulating film is the same, and only the polishing rate of the barrier metal is increased to both. Is also good.

FIG. 7 is a view showing an example of installation of an optical sensor for detecting that a barrier metal is exposed when a Cu film is wet-etched. In the figure, 24,
24a is an optical sensor as optical detection means, 25 is a silicon substrate, and 26 is a chemical liquid nozzle. Silicon substrate 2
Irradiating light from the optical sensor 24 onto the wafer surface on
The reflected light is received by the optical sensor 24a, the change in the film type on the surface is read, and the end point is detected. By using a CMP apparatus provided with such a system, it becomes possible to form an embedded wiring in one CMP apparatus.

In the above embodiment, the present invention has been described with respect to the case where an embedded wiring is formed. However, it is needless to say that the present invention can be similarly applied to a semiconductor device including the embedded wiring and its manufacture.

[0033]

As described above, according to the first aspect of the present invention, a first step of forming a trench for buried wiring in a flat interlayer insulating film formed on a semiconductor substrate, and a step of forming a barrier in the trench. A second step of forming a metal and a Cu film serving as a main wiring, a third step of removing the unnecessary Cu film on the interlayer insulating film by a first chemical mechanical polishing until a thin film remains, and Since there is a fourth step of removing only the thin film of the Cu film by etching until the barrier metal is exposed, and a fifth step of removing unnecessary barrier metal by the second chemical mechanical polishing, wiring is provided. Irrespective of the layout such as the width and the density of wiring, dishing due to chemical mechanical polishing can be prevented, and an embedded wiring having a flat surface can be obtained.

According to the second aspect of the present invention, the barrier metal is a material containing Ta or TaN, and the etching of the Cu film has a hydrogen ion concentration of pH 6 or less, so that the barrier metal is hardly etched. Since the treatment is performed using the chemical solution of the acidic solution, there is an effect that only the Cu film in a thin skin state can be reliably removed.

According to the third aspect of the present invention, the barrier metal is a material containing Ta or TaN, and the etching of the Cu film is performed by using a gas in which a chemical reaction with the Cu film is active. Since the gas phase etching is performed using a gas in which the metal is not easily etched, there is an effect that only the thin Cu film can be reliably removed.

According to the fourth aspect of the present invention, the Cu
By performing the film etching in the cleaning unit in the CMP apparatus, one CMP process is performed from the first chemical mechanical polishing (Cu film polishing) to the completion of the second chemical mechanical polishing (barrier metal polishing). Since it is closed in the apparatus, there is an effect that all processes can be performed in one CMP apparatus.

According to the fifth aspect of the present invention, the Cu
At the time of film etching, a change in the wafer surface of the semiconductor substrate is detected by a light detection means, and an etching end point is applied by exposing the barrier metal, so that an accurate embedded wiring can be formed. There is.

According to the invention of claim 6, the Ta
Since the end point of etching is set by exposing the barrier metal by detecting the emission spectrum of the above, there is an effect that it is possible to form an embedded wiring with high accuracy.

According to the seventh aspect of the present invention, since the thin Cu film is removed by sputtering using Ar ions, there is an effect that only the thin Cu film can be reliably removed.

According to the invention of claim 8, in the second chemical mechanical polishing, etching is performed from the surface of the semiconductor substrate by a thickness of the barrier metal until the Cu film is recessed, and Since the polishing is performed using a polishing agent or a polishing condition for selectively polishing only the metal, there is an effect that it is possible to contribute to the efficiency of formation of the embedded wiring and the miniaturization of the device.

According to the ninth aspect of the present invention, in the second chemical mechanical polishing, the polishing rates of the Cu film and the interlayer insulating film are the same, and only the polishing rate of the barrier metal is set to a value higher than the both. Since the polishing is performed using the increased polishing agent or polishing conditions, there is an effect that the efficiency of forming the embedded wiring can be improved and the device can be downsized.

Further, according to the tenth aspect of the present invention, of the Cu film to be the main wiring and the barrier metal filling the trench for the buried wiring formed in the interlayer insulating film on the semiconductor substrate, A first polishing unit for polishing until a thin skin remains, a first cleaning unit for cleaning a required amount of the Cu film, a second polishing unit for removing unnecessary portions of the barrier metal, and the semiconductor Since the second cleaning unit for cleaning the abrasive adhered to the substrate is provided, there is an effect that all the processing can be performed in one CMP apparatus.

According to the eleventh aspect of the present invention, there is provided light detecting means for detecting a change in the wafer surface of the semiconductor substrate and detecting the end point of the etching when the barrier metal is exposed, so that the embedding is performed with high accuracy. This has the effect of contributing to the formation of wiring.

According to the twelfth aspect of the present invention, the semiconductor device has a Cu film serving as a barrier metal and a main wiring formed in a trench for a buried wiring provided in a flat interlayer insulating film on a semiconductor substrate. Is provided with a flat buried interconnect, so that there is an effect that a semiconductor device having excellent quality can be obtained.

According to the thirteenth aspect of the present invention, a first step of forming a groove for an embedded wiring in a flat interlayer insulating film formed on a semiconductor substrate, and a step of forming a barrier metal and a main wiring in the groove. A second step of forming a Cu film, a third step of removing the unnecessary Cu film on the interlayer insulating film by a first chemical mechanical polishing until the Cu film remains, and a Cu step of removing the Cu film in the thin film state. A processing step of forming a buried interconnect using a fourth step of removing only the film by etching until the barrier metal is exposed and a fifth step of removing unnecessary barrier metal by a second chemical mechanical polishing At least, an excellent quality semiconductor device having a buried wiring with a flat surface can be obtained, which contributes to an improvement in manufacturing yield.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method of forming an embedded wiring according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for forming an embedded wiring according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a CMP apparatus having a plurality of polishing units and a cleaning unit according to Embodiment 1 of the present invention.

FIG. 4 is a schematic diagram showing a specific example of the polishing unit of FIG. 3;

FIG. 5 is a schematic view showing a specific example of the cleaning unit of FIG. 3;

FIG. 6 is a diagram schematically showing a flow of a wafer when performing the processing of FIGS. 1 and 2;

FIG. 7 is a diagram showing an installation example of an optical sensor for detecting that a barrier metal is exposed according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a state in which dishing has occurred in a conventional example.

FIG. 9 is a diagram showing a state in which dishing occurs in a conventional example.

[Explanation of symbols]

1,2,25 silicon substrate, 4 interlayer insulating film,
6 barrier metal, 7 Cu film, 9, 10, 19 rotating platen, 11, 12, 15 polishing head, 14, 14
a, 14b Cleaning unit, 17 Slurry (abrasive), 24, 24a Optical sensor.

Continued on the front page F term (reference) 5F004 CB02 DA00 DA23 DB08 FA08 5F033 HH11 HH21 HH32 MM01 MM02 MM12 MM13 PP15 PP27 PP33 QQ11 QQ14 QQ16 QQ19 QQ25 QQ48 QQ50 RR04 RR06 XX01 5F043 AA16 BB18 DD

Claims (13)

[Claims] A first step of forming a trench for a buried interconnect in a flat interlayer insulating film formed on a semiconductor substrate; and a second step of forming a barrier metal and a Cu film serving as a main interconnect in the trench. A third step of removing the unnecessary Cu film on the interlayer insulating film by a first chemical-mechanical polishing to leave a thin skin, and exposing only the Cu film in the thin skin state to the barrier metal. And a fifth step of removing unnecessary barrier metal by a second chemical-mechanical polishing. 2. The method according to claim 1, wherein the barrier metal is a material containing Ta or TaN, and the etching of the Cu film is performed using a chemical solution of an acidic solution having a hydrogen ion concentration of pH 6 or less and hardly etching the barrier metal. 2. The method for forming a buried wiring according to claim 1, wherein: 3. The method according to claim 1, wherein the barrier metal is a material containing Ta or TaN, and the etching of the Cu film is performed by using a gas that has an active chemical reaction with the Cu film and is difficult to etch the barrier metal. 2. The method according to claim 1, wherein the method is vapor phase etching. 4. The etching of the Cu film is performed in a cleaning unit in a CMP apparatus to complete the second chemical mechanical polishing (barrier metal polishing) from the first chemical mechanical polishing (Cu film polishing). 4. The method according to claim 1, wherein the steps (a) to (c) are closed in a single CMP apparatus. 5. The method according to claim 1, wherein, when etching the Cu film, a change in the wafer surface of the semiconductor substrate is detected by a light detecting means, and an end point of the etching is applied when the barrier metal is exposed. 5. The method for forming a buried interconnect according to any one of items 1 to 4. 6. The method for forming a buried interconnect according to claim 3, wherein an end point of etching is applied when the barrier metal is exposed by detecting the emission spectrum of Ta. 7. The method for forming a buried interconnect according to claim 1, wherein the thin Cu film is removed by sputtering using Ar ions. 8. The second chemical-mechanical polishing is performed by the same amount as the thickness of the barrier metal from the surface of the semiconductor substrate.
8. The method according to claim 1, wherein etching is performed until the u film is recessed, and the etching is performed using a polishing agent or polishing conditions for selectively polishing only the barrier metal. Method. 9. The method according to claim 6, wherein the second chemical mechanical polishing is performed using the Cu
The polishing rate of the film and the interlayer insulating film are the same, and the polishing is performed using a polishing agent or polishing conditions in which only the polishing rate of the barrier metal is increased to both or more.
9. The method for forming a buried interconnect according to any of 8. 10. A polishing method for polishing a Cu film, which is a barrier metal filling a trench for an embedded wiring formed in an interlayer insulating film on a semiconductor substrate and a Cu film serving as a main wiring, until a thin film remains. A polishing unit, a first cleaning unit for cleaning a required amount of the Cu film, a second polishing unit for removing unnecessary portions of the barrier metal, and cleaning a polishing agent attached to the semiconductor substrate. A CMP apparatus comprising: a second cleaning unit. 11. A light detecting means for detecting a change in a wafer surface of the semiconductor substrate and detecting an end point of etching when the barrier metal is exposed.
0. The CPM device according to 0. 12. A buried wiring formed in a trench for a buried wiring provided in a flat interlayer insulating film on a semiconductor substrate, having a Cu film serving as a barrier metal and a main wiring, and having a buried wiring having a flat surface. A semiconductor device characterized by the above-mentioned. 13. A first step of forming a buried wiring groove in a flat interlayer insulating film formed on a semiconductor substrate, and a second step of forming a barrier metal and a Cu film to be a main wiring in the groove. A third step of removing the unnecessary Cu film on the interlayer insulating film by a first chemical-mechanical polishing to leave a thin skin, and exposing only the Cu film in the thin skin state to the barrier metal. A semiconductor process characterized by including at least a processing step of forming a buried interconnect by using a fourth step of removing the unnecessary barrier metal by etching until a second step of removing the unnecessary barrier metal by chemical mechanical polishing. Device manufacturing method.