JP2000340544A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate generation of film separation by a method, wherein after forming a hydrophobic protective film on an exposed part of a silicon substrate, dry etching process is conducted with a photoresist film as a mask and then removing the photoresist film, using an amine acid-base treatment. SOLUTION: An O3TEOS film with a self-planarity which will become an interlayer insulating film is formed and then is polished by CMP process to expose the part of the silicon surface 5 in the edge of a wafer. On the exposed part of the Si surface 5, a hydrophobic protective film 6 made of SiOx is formed. Next, a photoresist 8 is spin coated and then is exposed to light and developed, to be turned into a prescribed pattern. Thereafter, the O3TEOS film 4 is dry etched with the photoresist 8 as a mask to form a through-hole 12. Using an amine acid based treatment liquid, chief component of which is monoethanol amine, the photoresist 8 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor having a step of using an amine acid-based resist stripper.

[0002]

2. Description of the Related Art In a manufacturing process of a semiconductor manufacturing apparatus,
An etching process and an ion implantation process using the photoresist film as a mask are repeatedly performed. After the completion of these processes, the unnecessary photoresist film is removed from the semiconductor substrate. It is common to use oxygen plasma to remove the photoresist film. However, finer wiring and multi-layering have been advanced due to higher integration of semiconductor devices, and through-holes provided in interlayer insulating films have also been miniaturized. As the diameter of through-holes becomes smaller, the through-hole opening technology is used. The adhesion of the aluminum alloy filling the through-hole is degraded by the reaction product generated on the through-hole wall during dry etching, and the disconnection is more likely to occur.

[0003] Therefore, as a method for efficiently removing the reaction product adhering to the inside of the through-hole, a method using an amine acid-based stripper containing monoethanolamine (C2H7NO) as a main component is adopted. Since the acid-based stripping solution can also remove the photoresist, use a wet stripping method in which the photoresist is stripped with an amine acid-based stripping solution instead of the conventional method of removing the photoresist film using oxygen plasma. Is the mainstream.

On the other hand, as a method of flattening an interlayer insulating film, plasma CVD (Chemical Vapor Deposit) having self-flatness is used.
ion) method for O3TEOS (Tetra EthoxyOrtho Silicat)
e) The film is generally used, but it is difficult to obtain a completely flat surface when the wiring interval is large. In such a case, a so-called etch-back method in which a photoresist, an organic resin film, or the like is applied on an interlayer insulating film formed by a method using O3TEOS, and these films and the interlayer insulating film are etched at the same rate. Often used together. However, it is difficult to etch two different materials at the same rate, and it is difficult to obtain complete planarization.

[0005] Further, as the integration of semiconductor devices becomes higher and the wiring becomes finer and multilayered, flattening of the interlayer insulating film is required.

In order to solve these problems, a planarization method by polishing, that is, chemical mechanical polishing (Chemical Mechanical Polishing) has been proposed.
Polishinig, hereinafter referred to as CMP).

Next, FIGS. 2A to 2F are cross-sectional views in the order of steps showing a conventional method of manufacturing a semiconductor device including a step of flattening an insulating film by a CMP process. FIG. 2A is a schematic cross-sectional view of the vicinity of a wafer edge after metal wiring processing. A BPSG (Boro Phospho Silicate Glass) film 2 which is an oxide film containing boron or phosphorus is formed on a silicon substrate 1 by a CVD method at a thickness of 1300 nm, and then a metal wiring 3 such as an Al wiring is formed.

FIG. 2B shows a plasma C on the metal wiring 3.
The O3TEOS film 4 having self-flatness is
This shows a state where 00 nm is deposited.

FIG. 2 (c) shows that the above-mentioned O3TEOS film 4 is polished by 1400 nm to a thickness of 1100 nm by a CMP process to be globally flattened from the viewpoint of the whole wafer. The thickness calculation amount here is obtained by measuring the thickness value of the interlayer insulating film in a portion other than the wiring portion using an optical measuring instrument such as Ellipso. During the CMP process, the Si surface 5 at the wafer edge is exposed.

FIG. 3 shows a state in which the polishing pad 10 is in contact with the surface of the wafer 16 on the vacuum chuck table 15 during the CMP process. In the CMP apparatus, a vacuum chuck table 15 for holding a wafer 16 is set on the lower side, and the polishing pad 10 is set on an upper surface facing the vacuum chuck table 15 as shown in FIG. Wafer 1 is placed on the edge of vacuum chuck table 15
A retainer ring 9 is attached as a stopper for holding the polishing pad 6 at the time of polishing. At the same time, a diamond 17 is attached to the retainer ring 9 so as to remove debris and the like of the polishing pad 10 attached to the polishing pad 10 generated during polishing. It also plays the role of removal.

The processing conditions of the CMP are as follows: the rotational speed of the upper polishing pad 10 is 50 rpm, and the rotational speed of the stage 18 on which the vacuum chuck table 15 is mounted is 7 rpm, and the polishing pad 10 rotates in the same direction. Is 350 gf / cm2. In addition, a silica-based slurry is used as an abrasive.

Since the surface area of the chuck table 15 is larger than the surface area of the wafer 16 by 2 mm so that the transfer of the wafer 16 can be carried out smoothly, the polishing cloth bending portion 11 is generated by the height of the retainer ring 9. (A) shows a state diagram when the height of the retainer ring 9 is low, and (b) shows a state diagram of the polishing cloth bending portion 11 when the height of the retainer ring 9 is high. Depending on the height of the retainer ring 9, the position of the polishing cloth bending portion 11 moves inward and outward when viewed from the center of the wafer 16.

FIG. 4 shows the relationship between the height of the retainer ring 9 and the position of the polishing cloth flexure 11 in terms of the relationship between the distance from the edge of the wafer 16 and the polishing rate (分 / min) at that location. . The contact pressure on the surface of the wafer 16 locally increases at the location where the polishing cloth bending portion 11 occurs, and the polishing rate increases in this portion, and the Si surface 5
Is exposed.

FIG. 2D shows a state after the formation of the through hole 12 after the etching process. Opening is performed by dry etching using the photoresist 8 as a mask. At the time of this dry etching, carbon-based or oxide-based reaction products 7 adhere to the openings of the through holes 12, and these reaction products 7 are Ar
Is not sufficiently removed by reverse sputtering using, and the resistance in the through hole 12 is increased and the disconnection is caused, thereby deteriorating the reliability. Therefore, carbon-based deposits are removed by O2 plasma treatment, and oxide-based deposits are removed by a fluorine-based compound containing dimethylformamide as a main component (about 70%).

In this case, the water in the fluorine-based compound is S
When the resist remains on the i-surface 5, when the resist is stripped with an amine acid-based resist stripping solution, the stripping solution reacts with water to form an oxide film-based reaction product 20 having low adhesion. For example, FIG. 2E shows a photoresist 8 serving as a mask during dry etching for forming the through hole 12.
Is removed at a temperature of about 90 ° C. at which the Al wiring does not dissolve, by removing an amine-acid-based resist stripping solution containing monoethanolamine (C2H7NO) as a main component (about 70%). Have been.

[0016]

As described above, after the CMP process for improving the flatness of the interlayer insulating film,
The Si substrate at the wafer edge may be exposed. While the exposed Si substrate is not covered at all and proceeds to the photoresist stripping step after the formation of the through-hole as it is, moisture remains on the Si substrate if a treatment with a solution containing any moisture is performed. As a method of removing the residual moisture, there is a method of removing the residual moisture by low-power plasma etching using only oxygen gas as disclosed in Japanese Patent Application Laid-Open No. 10-12590.

However, even if the residual moisture is completely removed, reattachment of the moisture may occur if the standing time is prolonged.

If this moisture exists in the Si substrate,
It reacts with monoethanolamine (C2H7NO) of the amine-acid-based organic stripping solution used in the photoresist stripping step as follows to form an alkaline solution.

C2H7NO + 2H2O → C2H5OH +
(NH4 +) + (OH-) + (1/2) O2 Then, an oxide film-based reaction product 20 is generated when the exposed Si is etched. This production reaction film 20
Is an oxide film type having a weak bonding force with O2 and Si and a weak adhesion to the Si surface, so that the reaction product film 20 does not peel off during the cleaning treatment with an amine acid-based organic stripping solution. The peeling of the film occurs continuously in a film forming process, an etching process, and the like after that process.

The reaction product film 20 peeled off by this phenomenon
Is re-adhered to the wafer and becomes particles, which causes a reduction in yield.

Accordingly, an object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device by introducing a process in which film peeling does not occur even when a treatment is performed with an amine-based stripping solution. It is.

[0022]

According to the present invention, in a step of flattening an interlayer insulating film, a hydrophobic protective film is formed on an exposed silicon substrate by performing a chemical mechanical polishing process, and then the photoresist film is masked. Wherein the dry etching is performed and the photoresist film is removed by an amine acid treatment.

Further, the present invention is a method of manufacturing a semiconductor device, wherein the protective film is formed to a thickness of 2 nm or more.

Further, the present invention is a method of manufacturing a semiconductor device, wherein the protective film is formed by a plasma treatment using oxygen gas.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings. 1A to 1F are cross-sectional views of a wafer in main steps for describing an example of the present invention.

First, as shown in FIG. 1A, after a CVD film 2 containing boron or phosphorus is formed on a silicon substrate 1, a photoresist is spin-coated, exposed and developed to form a photoresist of a predetermined pattern. Cross-sectional view of the vicinity of a wafer edge portion formed by patterning a CVD film 2 by performing a dry etching process by sputtering or the like using a photoresist film as a mask and then stripping the resist film after patterning, followed by metal wiring processing. Is shown.

Next, as shown in FIG. 1 (b), an O3TEOS film 4 having a
Coat 0 nm.

Next, as shown in FIG. 1C, the O3TEO is subjected to a CMP process to improve the flatness of the interlayer insulating film.
The S film 4 is polished to 1100 nm. During this process, the Si surface 5 at the wafer edge is exposed.

FIG. 1D is a cross-sectional view after forming a protective film 6 on the exposed portion of the Si surface 5. SiOx (x = 1, 2, 3, 4,...)
(The same applies hereinafter.) A film is formed. This SiOx film has hydrophobicity and does not retain moisture on the film surface. If the film thickness is at least 2 nm or more, it is difficult to peel off. It is necessary that the protective film 6 does not peel off during the amine-acid-based peeling treatment. Specifically, the following film forming conditions are used.

Apparatus: Plasma CVD temperature: 380 ° C. RF power: 200 W Gas used: O 3 and TEOS Pressure: 8.5 Torr In addition, the protective film 6 is hydrophobic and is coated with an organic acid-based organic liquid. Any film that does not peel off can be used,
A SiN film or a SiON film may be used. By depositing this hydrophobic film, it is difficult for moisture to adhere to the protective film 6 deposited on the exposed portion of the Si surface 5, so that it does not change with the alkaline solution generated by the reaction with the aminic acid-based organic liquid. Is unlikely to occur.

Further, besides the plasma CVD method, for example, by performing O2 plasma treatment under the following conditions,
An iOx film can be formed. According to this method, a thin SiOx of about 2 to 5 nm is used as compared with the plasma CVD method.
The formation of the film becomes easy. The conditions of the O2 plasma treatment are shown below.

Power: 1200 W O 2: 500 sccm Pressure: 0.6 Torr FIG. 1E is a cross-sectional view after forming a through hole. The photoresist 8 is spin-coated, exposed and developed to form a photoresist 8 having a predetermined pattern. afterwards,
The O3TEOS film 4 is subjected to dry etching using the photoresist 8 as a mask to open a through hole 12. During this dry etching, the through hole 1
2 Carbon-based or oxide-based reaction product 7 adheres to the opening, but this carbon-based reaction product 7 is removed by O2 plasma treatment, and oxide-based reaction product 7 is mainly composed of dimethylformamide. (About 70%) and is removed by wet etching with a solution containing a trace amount of a fluorine-based compound.

FIG. 1F is a cross-sectional view after the photoresist 8 serving as a mask at the time of etching for forming the through hole 12 has been removed. Aminic acid-based treatment liquid containing monoethanolamine as a main component (about 70%) (about 90%)
C.) to remove the photoresist 8. At this time, as the protective film 6 shown in FIG.
Since Si is protected by the x film, it is possible to prevent the generation of oxide film-based reaction products 7 even if the wafer contains residual moisture before the treatment with the amine acid-based treatment solution.
Therefore, even in the subsequent processes, generation of particles due to peeling of the film itself can be prevented.

FIG. 5 shows the yields when the conventional semiconductor manufacturing method and the semiconductor manufacturing method according to the present invention are used, respectively.

[0035]

According to the present invention, C in the interlayer insulating film forming step is
By forming a film that is hydrophobic and is not peeled off from the Si surface even when a liquid of an amino acid-based organic solvent is applied as a protective film on the Si surface exposed by the MP process, the film is removed with an amine-based organic solvent in the subsequent steps. Generation of a reaction product with residual moisture on the Si surface is suppressed, and furthermore, it is possible to prevent occurrence of peeling of a formed film in a subsequent step, which is caused by the reaction product as a starting point, resulting in a stable yield. Can be obtained.

FIG. 5 shows the improvement of the yield by introducing the present invention.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining an embodiment of the present invention.

FIG. 2 is a sectional view in the order of steps for explaining a conventional example.

FIG. 3 is a contact cross-sectional view of a polishing cloth and a wafer surface during polishing.

FIG. 4 is a correlation graph of a height of a retainer ring and a bent portion of a polishing cloth.

FIG. 5 is a graph comparing yields of a conventional process and a process of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 CVD film 3 Metal wiring 4 O3TEOS film 5 Si surface 6 Protective film 7 Reaction product 8 Photoresist 9 Retaining ring 10 Polishing cloth 11 Polishing cloth bending part 12 Through hole 20 Reaction generation film 16 Wafer 17 Diamond 15 Chuck table 18 stages

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F004 BD01 DA26 DB03 EA11 EB01 EB03 FA08 5F043 BB30 CC16 5F046 MA02 MA18

Claims (3)

[Claims] In a flattening step of an interlayer insulating film, a hydrophobic protective film is formed on an exposed silicon substrate by performing a chemical mechanical polishing treatment, and then dry etching is performed by using a photoresist film as a mask to perform an amine acid-based etching process. A method for manufacturing a semiconductor device, comprising removing the photoresist film by a treatment. 2. The method according to claim 1, wherein said protective film is formed to a thickness of 2 nm or more. 3. The method according to claim 1, wherein said protective film is formed by plasma processing using oxygen gas.