JP2001291766A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable semiconductor device having a multilayer wiring structure for connecting its upper and lower-layer wiring layers via a plug, by preventing its side-etch from occurring in the interface between its upper-layer wiring layer of a border-less portion and the plug in the case of the etching performed when patterning its upper-layer wiring layer. SOLUTION: By the burying of a connection hole 14 provided in an interlayer insulation film 13, a metallic film for a plug is formed. Then, after covering with a resist mask having its size somewhat larger than the size of the connection hole 14 the region to form therein the connection hole 14, the metallic film for a plug is so etched to its predetermined thickness by an anisotropic etching as to obtain the metallic film having a partially protruded portion thereon and extinguish naturally the resist mask. Thereafter, by the expansive etchback of the metallic film, a plug 15 protruded in the form of a dome from the surface of the interlayer insulation film 13 is formed. As a result, the film thickness of an upper-layer wiring layer 17 is made small above the region to form the plug 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to an electrode structure of a multilayer wiring.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having a multilayer wiring structure, a lower wiring layer is formed on a semiconductor substrate in which elements are formed, an interlayer insulating film is formed thereon, and the lower wiring layer is formed on the interlayer insulating film. After forming a connection hole for making a connection with the upper wiring layer, a film is formed so as to embed a plug metal film in the connection hole, and the metal film is left only in the connection hole by etch-back so that a plug is formed. To form Thereafter, an upper wiring layer is formed, and a multilayer wiring structure including upper and lower wiring layers connected via plugs is obtained. A conventional method for forming a multilayer wiring structure will be described below with reference to FIGS. First, a semiconductor substrate 1 (hereinafter referred to as a substrate
A TiN film 2a to be a barrier metal
Is formed to a thickness of about 100 nm, and an AlCu film 2 is formed thereon.
b is formed to a thickness of about 400 nm, and a TiN film 2c serving as an antireflection film is formed thereon to a thickness of about 30 nm. Subsequently, using a resist mask, the TiN film 2c, AlCu
The film 2b and the TiN film 2a are sequentially dry-etched to form the lower wiring layer 2 having a laminated structure composed of the TiN film 2c / AlCu film 2b / TiN film 2a. Next, an interlayer insulating film 3 made of, for example, a high-density plasma CVD oxide film is formed to a thickness of about 1.2 μm on the entire surface so as to cover the lower wiring layer 2 and then polished by a CMP method to form a lower wiring. Layer 2
A flattening process is performed so that the thickness of the upper interlayer insulating film 3 becomes about 750 nm. Then, the lower wiring layer 2 is formed on the interlayer insulating film 3.
Is formed with a hole diameter of about 0.28 μm (FIG. 14A).

Next, a TiN film 5 serving as a barrier metal is formed to a thickness of about 100 nm by, for example, a sputtering method on the entire surface of the interlayer insulating film 3 so as to fill the connection hole 4. Next, a tungsten film 6a as a plug metal film is formed to a thickness of about 400 nm by, for example, thermal CVD (FIG. 14B). Next, a plug 6 is formed by etching back the entire surface of the tungsten film 6a and leaving it only in the connection hole 4. In this case, the interlayer insulating film 3
An example in which a TiN film 5 is left as a barrier metal of an upper wiring layer thereon is shown. At this time, over-etching is performed to some extent so that the residue of the tungsten film 6a does not occur on the TiN film 5. Thereby, the plug 6 is connected to the connection hole 4.
(In this case, the upper surface of the TiN film 5), and a recess 7 of about 100 to 200 nm is generated to fill the connection hole 4 (FIG. 14C).

Then, an AlCu film 8a is formed on the entire surface,
After forming a film with a thickness of about 400 nm at about 40 ° C.,
A reflow process is performed at about 0 ° C. to improve the filling property inside the recess 7. Subsequently, a TiN film 8b serving as an anti-reflection film is formed on the entire surface of the AlCu film 8a to a thickness of about 30 nm. Next, a photoresist film 9 is formed on the entire surface and is patterned using a photolithography technique (FIG. 15).
(A)) Using the resist pattern 9 as a mask, the underlying TiN film 8b, AlCu film 8a and TiN film 5 are sequentially dry-etched to obtain a TiN film 8b / AlCu film 8
An upper wiring layer 8 having a laminated structure composed of a / TiN film 5 is formed (FIG. 15B).

[0005]

Since the conventional multilayer wiring structure is formed as described above, the plug 6 buried in the connection hole 4 retreats from the opening surface and is recessed.
Therefore, the AlC of the upper wiring layer 8
The thickness of the u film 8a is large in the plug formation region. That is, as shown in FIG.
The film thickness t2 of the film 8a in the plug formation region is larger than the film thickness t1 in the other regions. As a result, when the upper wiring layer 8 is patterned into a borderless structure as shown in FIG. 15B due to misalignment of the mask or the like, the following problems occur. At the end of the dry etching for patterning the upper wiring layer 8, the AlCu film 8a remains only on the plug 6, and the remaining AlCu film 8a remains at the over-etching stage which has already been removed by etching in other regions. In contrast, the side wall protection effect is extremely lower than during the main etching. This is because during the main etch, the supply of the degradation products of the photoresist film 9, the supply of the reaction products of AlCu film 8a and the etching gas Cl _2, there are such further supply of products to which they are polymerized, in overetching This is because most is limited to the supply of the decomposition product of the photoresist film 9. However, during over-etching,
Since the etchant is almost consumed and in excess,
The sidewall protective film is easily broken, and as shown in the figure, AlCu
The side etch 10 easily occurs at the interface between the film 8a and the plug 6. When such a side etch 10 occurs,
The contact resistance between the plug 6 and the upper wiring layer 8 is increased, and hillocks may be generated due to heat generated by a local increase in current density, which significantly reduces the characteristics and reliability of the semiconductor device. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. In a multilayer wiring structure in which upper and lower wiring layers are connected via plugs, an etching for patterning an upper wiring layer is performed. To prevent a side etch from occurring at the interface between the upper wiring layer and the plug at the borderless portion, reduce the contact resistance between the upper wiring layer and the plug, and obtain a highly reliable semiconductor device With the goal.

[0007]

Means for Solving the Problems Claim 1 according to the present invention.
The semiconductor device according to the present invention has a device configuration having upper and lower wiring layers stacked on a semiconductor substrate via an insulating layer and connected to each other by plugs filled in connection holes provided in the insulating layer, The plug is made of a conductive material different from that of the upper wiring layer, and an upper portion thereof is projected from the surface of the insulating layer as a dome-shaped or tapered projection.

According to a second aspect of the present invention, the semiconductor device is stacked on a semiconductor substrate with an insulating layer interposed therebetween, and is connected to each other by a plug filled in a connection hole provided in the insulating layer. A device configuration having upper and lower wiring layers, wherein the thickness of the insulating layer is increased only in the peripheral portion of the connection hole, and the opening surface of the connection hole is formed higher than the surface of the insulating layer.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the thickness of the upper wiring layer formed on the insulating layer is reduced in the plug formation region.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, a first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate is provided, and the lower wiring is formed on the insulating layer. A second step of opening a connection hole reaching the layer, a third step of filling the connection hole and forming a plug metal film on the entire surface of the insulating layer, The connection hole forming region is covered with a resist mask slightly larger than the hole size, and is selectively etched and removed to a predetermined thickness. Thereafter, the entire surface is etched back, whereby a plug is formed in the connection hole, and the upper portion thereof is dome-shaped or tapered. A fourth step of protruding from the surface of the insulating layer to form a protruding portion having a shape, and forming an upper wiring layer made of a conductive material different from the plug on the insulating layer so as to be in contact with the plug. It is intended to include a fifth step.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, in the fourth step, the selective etching using a resist mask employs anisotropic etching. The mask is designed to disappear naturally.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, in the fourth step, isotropic etching is used in the selective etching using a resist mask. The resist mask is removed later.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate; and connecting to the lower wiring layer. Forming a resist mask slightly larger than the connection hole size on the insulating layer so as to cover a region where the connection hole is to be formed, and selectively removing the insulating layer by isotropic etching to a predetermined thickness; Process and
A third step of opening the region where the connection hole is to be formed in the insulating layer and forming the connection hole so that the thickness of the insulating layer is increased only around the opening; and forming a plug in the connection hole. And a fifth step of forming an upper wiring layer made of a conductive material different from the plug on the insulating layer so as to be in contact with the plug.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate; and forming the lower wiring on the insulating layer. A second step of opening a connection hole reaching the layer, a resist slightly larger than the connection hole size is formed on the insulating layer by filling the connection hole, and isotropic etching using the resist mask, A third step of selectively removing the insulating layer by etching to a predetermined thickness so as to increase the thickness only at a portion around the connection hole, a fourth step of burying a plug in the connection hole, Forming an upper wiring layer made of a conductive material different from that of the plug so as to be in contact with the plug.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh or eighth aspect, when the insulating layer is selectively isotropically etched, the height of the surface of the insulating layer after the etching is increased. However, the etching thickness is set so as to be lower than the height of the plug surface formed in a later step.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. In the figure, reference numeral 11 denotes a semiconductor substrate (hereinafter referred to as a
Reference numeral 12 denotes a lower wiring layer formed on the substrate 11, and a TiN film 12 a serving as a barrier metal and an AlCu film 1.
2b and a laminated structure composed of a TiN film 12c serving as an antireflection film. Reference numeral 13 denotes an interlayer insulating film as an insulating layer formed to cover the lower wiring layer, reference numeral 14 denotes a connection hole provided in the interlayer insulating film 13, reference numeral 15 denotes a connection hole 14 in which a TiN film 16 serving as a barrier metal is formed. A plug made of a tungsten film filled and interposed therebetween. Reference numeral 17 denotes an upper wiring layer formed on the interlayer insulating film 13 so as to be in contact with the plug 15, and includes a TiN film 16, an AlCu film 17a, and a TiN film serving as an anti-reflection film. 17b.
For convenience, only the wiring structure of the semiconductor device is shown in FIG.
Here, a case where the upper wiring layer 17 has a borderless structure due to misalignment of a mask or the like is shown.

As shown in FIG.
The plug 15 is filled and formed to connect the upper and lower wiring layers 12 and 17. The plug 15 filled in the connection hole 14 via the TiN film 16 in this manner has a protruding dome-shaped upper part. The opening surface (in this case, T
(the upper surface position of the iN film 16). For this reason, the AlC of the upper wiring layer 17 in contact with the plug 15
The thickness of the u film 17a is small in the region where the plug 15 is formed.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS. First, the T as a barrier metal is formed on the entire surface of the substrate 11 on which the elements are formed.
An iN film 12a is formed with a thickness of about 100 nm, an AlCu film 12b is formed thereon with a thickness of about 400 nm, and a TiN film 12c serving as an antireflection film is formed thereon with a thickness of about 30 nm. . Subsequently, using a resist mask, TiN
The film 12c, the AlCu film 12b, and the TiN film 12a are sequentially dry-etched to form the lower wiring layer 12 having a multilayer structure including the TiN film 12c / AlCu film 12b / TiN film 12a. Next, for example, high density plasma C
An interlayer insulating film 13 made of a VD oxide film is
After forming a film with a thickness of about 1.2 μm on the entire surface
The interlayer insulating film 1 on the lower wiring layer 12 is polished by the P method.
The flattening process is performed so that the film thickness of No. 3 becomes about 750 nm. Thereafter, a connection hole 14 reaching the lower wiring layer 12 is formed in the interlayer insulating film 13 with a hole diameter of about 0.28 μm. Next, a TiN film 16 serving as a barrier metal is formed to a thickness of about 100 nm by, for example, a sputtering method on the entire surface of the interlayer insulating film 13 so as to fill the connection hole 14, and a plug Tungsten film 1 as a metal film
5b is formed to a thickness of about 400 nm by, for example, a thermal CVD method. Thereafter, a photoresist film 18 is formed on the entire surface, and is patterned using a photolithography technique.
Resist pattern 1 slightly larger than the size of connection hole 14
8 are formed so as to cover the connection hole 14 formation region (FIG. 2).
(A)).

Next, using the resist pattern 18 as a mask, the underlying tungsten film 15b
Etching is removed by anisotropic etching at a thickness T ₁ of nm, and the tungsten film 15 b is made to protrude in the connection hole 14 formation region. At the time of this etching, the resist pattern 18 naturally disappears. This can be achieved by forming the photoresist film 18 to a thickness suitable for natural disappearance at the time of forming the photoresist film 18 in the previous step. For example, when using an anisotropic etching condition in which the selectivity of the tungsten film 15b to the photoresist is 0.6, the film thickness when the resist pattern 18 is formed is about 250 / 0.6 (μm). Further, since the etching rate of the resist pattern 18 is higher at the corners than at the flat parts, the tungsten film 15b protrudes in a dome-shaped protruding shape (FIG. 2B).

Next, the entire surface of the tungsten film 15b is etched back by isotropic etching, and the tungsten film 15b is left in the connection hole 14 to form a plug 15. In this case, an example in which the TiN film 16 on the interlayer insulating film 13 is left as a barrier metal of the upper wiring layer 17 is shown. At this time, the TiN film 16
Over-etching is performed to some extent so that a residue of the tungsten film 15b is not formed thereon. By etching back the entire surface of the tungsten film 15b protruding in the region where the connection hole 14 is formed, the upper portion of the plug 15 rises in a dome shape from the opening surface of the connection hole 14 (in this case, the upper surface of the TiN film 16). About 120nm
It has a projection 15a having a thickness of In this case, the thickness of the protruding portion 15a is formed of a tungsten film 15b in the previous step from the thickness T ₁ which projects by etching using a resist mask 18 and minus the amount of over-etching (FIGS. 3 (a) ).

Next, an AlCu film 17a is formed on the entire surface by, for example, a sputtering method at about 140 ° C. to a thickness of about 400 nm, and then a reflow process is performed at about 450 ° C. for about 2 minutes. Subsequently, a TiN film 17b serving as an antireflection film is formed on the entire surface of the AlCu film 17a to a thickness of about 30 nm. Next, a photoresist film 19 is formed on the entire surface and is patterned using a photolithography technique (FIG. 3).
(B)) Using the resist pattern 19 as a mask, the underlying TiN film 17b, AlCu film 17a and TiN film 16 are sequentially dry-etched to obtain a TiN film 17b / A
An upper wiring layer 17 having a laminated structure composed of the lCu film 17a / TiN film 16 is formed (see FIG. 1). Thereafter, predetermined processing is performed to complete the semiconductor device.

In the semiconductor device formed as described above,
The plug 15 to be filled in the connection hole 14 is formed so as to protrude in a dome shape from the opening surface of the connection hole 14. For this reason,
Al of upper wiring layer 17 formed in contact with plug 15
The Cu film 17a is formed to be thinner in the plug 15 formation region than in other regions. That is, the AlCu film 1
The film thickness t2 in the plug formation region 7a is smaller than the film thickness t1 in the other regions (see FIG. 3B). Thus, even when the upper wiring layer 17 is patterned, even if the borderless structure as shown in FIG. This will be described in detail below.

In the dry etching for patterning the upper wiring layer 17, even if the plug protruding portion 15a starts to be exposed, AlC
The u film 17a remains. As described above, the etching of the AlCu film 17a in the plug formation region is a process during the main etching before over-etching is performed in other regions. Therefore, the AlCu film 17a and the plug 1
To the interface between the 5, supply of the degradation products of the photoresist film 19, as they sidewall protective film due supply of feed, further product they are polymerized reaction products of AlCu film 17a and the etching gas Cl ₂ Adhere to. further,
During the main etching, the etchant is consumed in the etching reaction with the AlCu film 17a other than the plug protrusion 15a and the TiN film 16 therebelow, so that the etchant does not become excessive and the attack on the sidewall protection film is suppressed. You. In this manner, the protrusion 15a is formed on the plug 15, and the AlC of the upper wiring layer 17 is formed at that portion.
Since the thickness of the u film 17a is reduced, the protection effect of the sidewall protection film formed at the interface with the plug 15 is improved during dry etching during patterning of the upper wiring layer 17, thereby reducing the occurrence of side etching. Can be prevented.

As described above, at the time of patterning the upper wiring layer 17, the occurrence of side etching at the interface between the upper wiring layer 17 and the plug 15 in the borderless structure can be prevented. The contact resistance between the semiconductor device and the semiconductor device can be stably reduced, and hillocks do not occur due to heat generation due to a local increase in current density, so that the characteristics and reliability of the semiconductor device can be improved.
In addition, since the contact between the plug 15 and the upper wiring layer 17 is made at the plug protrusion 15a, the effect of reducing the contact resistance by increasing the contact area and the effect of reducing the alignment accuracy in the borderless structure are obtained. Properties can be further improved.

In this embodiment, when forming the plug 15, the tungsten film 15b is covered with a resist mask 18 slightly larger than the size of the connection hole so as to cover the region where the connection hole 14 is formed, so that the resist mask 18 naturally disappears. after thickness anisotropic etching by T ₁ of, for the entire surface is etched back, the shape of the protrusion 15a is one raised in a dome shape. Usually, when a film is formed on a base having a protruding portion, the coverage tends to be poor. However, since the plug protruding portion 15a is formed in a dome shape, the upper wiring layer 1 is formed.
The formation of the AlCu film 17a of No. 7 can cover the region of the protruding portion 15a with good coverage by the reflow treatment, and the reliability is further improved. In addition, since the resist mask 10 is naturally eliminated, the number of steps can be reduced, and
The protruding portion 15a can be easily formed in a dome shape by anisotropic etching. Further, since the resist removal step usually performed by ashing in an oxygen atmosphere can be omitted, the tungsten film 15b is not exposed to oxygen, and the contact resistance with the upper wiring layer caused by the altered layer formed by the surface oxidation can be reduced. Adverse effects can be prevented and reliability is improved.

The thickness of the plug protruding portion 15a protruding from the opening surface of the connection hole 14 is desirably formed to be approximately the same as or slightly larger than the depth of the recess 7 formed by a conventional one that does not protrude. Further, in this embodiment, the resist mask 18 used in the anisotropic etching at the time of forming the plug 15 is made to disappear spontaneously. However, the resist mask 18 can be left and removed by ashing.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.
Here, for convenience, only the wiring structure of the semiconductor device is shown, and a case where the upper wiring layer 17 has a borderless structure due to misalignment of a mask or the like is shown. Embodiment 1
In this embodiment, the plug 15 filled in the connection hole 14 has the dome-shaped protruding portion 15a. However, in the second embodiment, as shown in FIG. Is formed.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS. First, as in the first embodiment, the TiN film 12c / AlCu film 12b / TiN film 12
After forming the lower wiring layer 12 of the laminated structure composed of a and forming the interlayer insulating film 13, a planarization process is performed by the CMP method. Thereafter, a connection hole 14 is formed in the interlayer insulating film 13, a TiN film 16 is formed on the entire surface so as to fill the connection hole 14, and a tungsten film 20b as a plug metal film is formed on the entire surface. Thereafter, a photoresist film 21 is formed on the entire surface, and is patterned using photolithography to form a resist pattern 21 slightly larger than the size of the connection hole 14 so as to cover the connection hole 14 formation region. The width and thickness of the resist pattern 21 formed here are larger than those of the resist pattern 18 used in Embodiment 1 and which disappears naturally during etching in a later step (FIG. 5A). ).

Next, using the resist pattern 21 as a mask, the underlying tungsten film 20b is, for example,
Etching is removed by isotropic etching with a thickness T ₂ of nm (FIG. 5B), and thereafter, the resist pattern 21 is removed, and the tungsten film 20 b is tapered out in the connection hole 14 formation region. Next, in the same manner as in the first embodiment, the entire surface of the tungsten film 20b is etched back by isotropic etching, and the plug 20 is formed while remaining in the connection hole 14. 1
4 (in this case, the upper surface of the TiN film 16), and is formed to have a protrusion 20a having a thickness of about 120 nm (FIG. 6A). After that, as in the first embodiment, an AlCu film 17a is formed on the entire surface, a reflow process is performed, a TiN film 17b is formed thereon, and a resist pattern 19 is formed (FIG. 6).
(B)), the upper wiring layer 17 is formed by dry etching using the resist pattern 19 as a mask (FIG. 4).
reference). Thereafter, predetermined processing is performed to complete the semiconductor device.

In the semiconductor device formed as described above,
The plug 20 to be filled and formed in the connection hole 14 is formed so as to project in a tapered shape from the opening surface of the connection hole 14. For this reason,
As in the first embodiment, the thickness (t2) of the AlCu film 17a formed in contact with the plug 20 in the region where the plug 20 is formed is smaller than the thickness (t1) in the other regions. (See FIG. 6B). Thereby, even when the upper wiring layer 17 is patterned to have a borderless structure as shown in FIG. 4 due to misalignment of the mask or the like, it is possible to prevent the occurrence of side etching at the interface between the upper wiring layer 17 and the plug 20. And the plug 20 and the upper wiring layer 1
7 can be stably reduced, and
Hillocks are not generated by heat generation due to a local increase in current density, and characteristics and reliability of the semiconductor device can be improved. In addition, since the contact between the plug 20 and the upper wiring layer 17 is made at the plug protruding portion 20a, the effect of reducing the contact resistance by increasing the contact area and the effect of reducing the alignment accuracy in the borderless structure are obtained. Can be further improved.

Further, in this embodiment, when the plug 20 is formed, the tungsten film 20b is isotropically etched by covering the connection hole 14 formation region with the resist mask 21 slightly larger than the connection hole size. As shown in FIG. 7 (b), the tungsten film 20b is etched from the lateral direction of the resist mask 21 to the lower layer, and is projected in a tapered shape at that portion. Thereafter, the entire surface is etched back, and the shape of the projected portion 20a becomes tapered. . Therefore, the formation of the AlCu film 17a of the upper wiring layer 17 can cover the region of the protruding portion 20a with good coverage by the reflow process,
Reliability is further improved.

Embodiment 3 FIG. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
Here, for convenience, only the wiring structure of the semiconductor device is shown, and a case where the upper wiring layer 17 has a borderless structure due to misalignment of a mask or the like is shown. As shown in the figure,
Connection hole 14 provided in interlayer insulating film 22 as an insulating layer
A plug 23 is filled and formed in the upper and lower wiring layers 12 and 17.
In this case, the thickness of the interlayer insulating film 22 is increased only in the peripheral portion 22a of the connection hole, and the opening surface of the connection hole 14 is formed higher than the surface of the interlayer insulating film 22 other than the peripheral portion 22a of the connection hole.

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIGS. First, as in the first embodiment, the entire surface of the substrate
After forming the lower wiring layer 12 having a laminated structure composed of the TiN film 12c / AlCu film 12b / TiN film 12a and forming the interlayer insulating film 22, a flattening process is performed by the CMP method. Thereafter, a photoresist film 24 is formed on the entire surface, and is patterned by using a photolithography technique, so that a resist pattern 24 slightly larger than the size of the connection hole 14 to be formed in a later step is formed so as to cover a region where the connection hole 14 is to be formed. (FIG. 8 (a)). Next, using the resist pattern 24 as a mask, the underlying interlayer insulating film 22 is, for example,
Etching is removed by isotropic etching at a thickness T ₃ of 0 nm. As a result, the interlayer insulating film 22 is etched from the lateral direction of the resist mask 24 to the lower layer, and the peripheral portion 22 including the region where the connection hole 14 is to be formed is etched.
a has a protruding shape (FIG. 8B).

After that, the resist pattern 24 is removed,
Again, a resist pattern 25 for forming the connection hole 14 is formed on the interlayer insulating film 22 (FIG. 9A), and the underlying interlayer insulating film 22 is removed by dry etching using the resist pattern 25 as a mask. A connection hole 14 reaching the lower wiring layer 12 is opened. As a result, only the interlayer insulating film 22a around the opening is thick, and the connection hole 14 whose opening surface is formed higher than the surface of the other interlayer insulating film 22 is opened (FIG. 9B). Next, the resist pattern 25 is removed, and the connection hole 1 is formed in the same manner as in the first embodiment.
4, a TiN film 16 is formed on the entire surface, and a tungsten film 23 as a plug metal film is formed on the entire surface thereof.
a is formed (FIG. 10A).

Next, the entire surface of the tungsten film 23a is etched back by isotropic etching, and the tungsten film 23a is left in the connection hole 14 to form a plug 23. Also in this case, an example is shown in which the TiN film 16 on the interlayer insulating film 22 is left as a barrier metal of the upper wiring layer 17. At this time, the TiN film 1
6 so that no residue of the tungsten film 23a is formed on
Perform some over-etching. This allows
The plug 23 is connected to the opening surface of the connection hole 14 (in this case, TiN
The recess 26 recedes from the upper surface of the film 16 and forms a recess 26 of about 120 nm to fill the connection hole 14 (FIG. 10).
(B)). Thereafter, as in the first embodiment, an AlCu film 17a is formed on the entire surface, a reflow process is performed, a TiN film 17b is formed thereon, and a resist pattern 19 is formed (FIG. 11). , This resist pattern 19
Wiring layer 17 by dry etching using
Is formed (see FIG. 7). Thereafter, predetermined processing is performed to complete the semiconductor device.

In the semiconductor device formed as described above,
Prior to the formation of the connection hole 14, the peripheral portion 22 a including the region where the connection hole 14 is to be formed is projected by isotropic etching of the interlayer insulating film 22 using a resist mask 24 slightly larger than the size of the connection hole 14, Then the connection hole 14
Is formed, the opening surface of the connection hole 14 is formed higher than the surface of the interlayer insulating film 22 other than the connection hole peripheral portion 22a. For this reason, the plug 2 filled and formed in the connection hole 14 is formed.
Reference numeral 3 denotes a recess having a recess 26 which is recessed from the opening surface.
In this case, the film thickness (t2) in the region where the plug 23 is formed is about 130 times smaller than the film thickness (t1) in the other region.
nm (= 250 nm-120 nm). here,
Resist etching thickness T ₃ by isotropic etching of the interlayer using a mask 24 insulating film 22 is set larger than the depth of the recess 26 of the plug 23 to be formed in a later step. In other words, the height of the surface of the plug 23 is
2a except the surface of the interlayer insulating film 22 (in this case, the TiN film 1
7b surface). This difference in height is desirably about the same as or slightly greater than the depth of the recess 26. This allows the thickness (t2) of the AlCu film 17a in the region where the plug 23 is formed to be reduced in the other regions. It can be made thinner than the thickness (t1) (see FIG. 11).

As a result, even when the upper wiring layer 17 is patterned into a borderless structure as shown in FIG. 7 due to misalignment of the mask during patterning, the upper wiring layer 17 and the plug 23 are Can be prevented from occurring at the interface of the semiconductor device, the contact resistance between the plug 23 and the upper wiring layer 17 can be stably reduced, and hillocks can be generated due to heat generation due to a local increase in current density. The characteristics and reliability of the semiconductor device can be improved without occurrence.

The etching thickness T _{3 of} the interlayer insulating film 22 isotropically etched using the resist mask 24.
Is smaller than the depth of the recess 26 of the plug 23 formed in a later step, A
The thickness (t2) of the lCu film 17a is slightly thicker than the thickness (t1) in other regions, but the difference is as follows.
Those which are reduced by the etching thickness T ₃ in comparison with the prior art. For this reason, the protection effect of the sidewall protective film formed at the interface with the plug 23 is improved at the time of dry etching at the time of patterning the upper wiring layer 17 as compared with the conventional one, and the occurrence of side etching is suppressed. effective.

Embodiment 4 Next, a fourth embodiment of the present invention will be described with reference to the drawings. In this embodiment, another example of the manufacturing method of the semiconductor device shown in FIG. 7 of the third embodiment will be described below with reference to FIGS. First, as in the first embodiment, the TiN film 12c / AlCu film 1
After forming the lower wiring layer 12 having a laminated structure composed of the 2b / TiN film 12a and forming the interlayer insulating film 22, CMP is performed.
A flattening process is performed by a method. Thereafter, a resist pattern 27 for forming a connection hole is formed on the interlayer insulating film 22 (FIG. 1).
2 (a)), using the resist pattern 27 as a mask, the underlying interlayer insulating film 22 is removed by dry etching to open a connection hole 14 reaching the lower wiring layer 12 (FIG. 12 (b)).

Next, a photoresist film 28 is formed on the entire surface of the interlayer insulating film 22 so as to fill the connection holes 14, and is patterned by photolithography to form a resist pattern 28 slightly larger than the size of the connection holes 14. Are formed so as to cover the connection hole 14 formation region (FIG. 13).
(A)). Next, using the resist pattern 28 as a mask, the underlying interlayer insulating film 22 is removed by, for example, isotropic etching with a thickness T ₄ of about 250 nm. As a result, the interlayer insulating film 22 is etched from the lateral direction of the resist mask 28 to the lower layer so that the peripheral portion 22a of the connection hole is projected (FIG. 13).
(B)).

Thereafter, similarly to the third embodiment, the resist pattern 28 is removed, and a TiN film 16 and a tungsten film 23a are sequentially formed (see FIG. 10A). A plug 23 is filled and formed in 14 (see FIG. 10B). After this, Al
A Cu film 17a is formed, a reflow process is performed, a TiN film 17b is formed thereon, a resist pattern 19 is formed (see FIG. 11), and an upper wiring is formed by dry etching using the resist pattern 19 as a mask. The layer 17 is formed (see FIG. 7). Thereafter, predetermined processing is performed to complete the semiconductor device.

In this embodiment, after opening the connection hole 14, a resist pattern 28 slightly larger than the size of the connection hole 14 is formed so as to cover the region where the connection hole 14 is formed, and the isotropic formation of the interlayer insulating film 22 is performed. Etching is performed. Thus, similarly to the third embodiment, the opening surface of the connection hole 14 can be formed higher than the surface of the interlayer insulating film 22 other than the connection hole peripheral portion 22a, and the same effect as the third embodiment can be obtained. Further, in this case, since the resist mask 28 used for isotropic etching of the interlayer insulating film 22 is formed by burying the connection hole 14, it is necessary to remove the inside of the connection hole 14 when removing the resist mask 28 (FIG. 13), since there is no step in the interlayer insulating film 22 underlying the resist pattern 27 when the connection hole 14 is opened, the resist pattern abnormality due to halation due to the step hardly occurs, and the connection hole 14 can be formed with high reliability (FIG. 12). reference).

[0043]

As described above, according to the semiconductor device of the first aspect of the present invention, a plug is stacked on a semiconductor substrate via an insulating layer, and is filled in a connection hole provided in the insulating layer. Wherein the plug is made of a conductive material different from that of the upper wiring layer, and the upper portion of the insulating layer is formed as a dome-shaped or tapered projection. Because it protrudes from the surface, the upper wiring layer can be formed with good coverage,
During the patterning of the upper wiring layer, the occurrence of side etching at the interface between the upper wiring layer and the plug in the borderless structure can be prevented, the contact resistance between the plug and the upper wiring layer can be reduced stably, and the occurrence of hillocks is also prevented. As a result, the characteristics and reliability of the semiconductor device are improved. Further, there is an effect of reducing the contact resistance by increasing the contact area between the plug and the upper wiring layer, and an effect of relaxing the alignment accuracy in the borderless structure, so that the reliability is further improved.

According to a second aspect of the present invention, the semiconductor device is stacked on the semiconductor substrate via an insulating layer, and is connected to each other by a plug filled in a connection hole provided in the insulating layer. In the device configuration having upper and lower wiring layers, the thickness of the insulating layer is increased only in the peripheral portion of the connection hole so that the opening surface of the connection hole is formed higher than the surface of the insulating layer. The generation of side etch at the interface between the upper wiring layer and the plug in the structure can be prevented, the contact resistance between the plug and the upper wiring layer can be reduced stably, and the occurrence of hillocks can also be prevented. The performance is improved.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the thickness of the upper wiring layer formed on the insulating layer is reduced in the plug formation region. In patterning, the effect of preventing the occurrence of side etching at the interface between the upper wiring layer and the plug of the borderless structure is reliably obtained, and the characteristics and reliability of the semiconductor device are improved.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate; and forming the lower wiring on the insulating layer. A second step of opening a connection hole reaching the layer, a third step of filling the connection hole and forming a plug metal film on the entire surface of the insulating layer, The connection hole forming region is covered with a resist mask slightly larger than the hole size, and is selectively etched and removed to a predetermined thickness. Thereafter, the entire surface is etched back, whereby a plug is formed in the connection hole, and the upper portion thereof is dome-shaped or tapered. A fourth step of protruding from the surface of the insulating layer to form a protruding portion having a shape, and forming an upper wiring layer made of a conductive material different from the plug on the insulating layer so as to be in contact with the plug. Since the fifth step is included, the upper wiring layer can be formed with good coverage, and at the time of patterning the upper wiring layer, side etching can be prevented from occurring at the interface between the upper wiring layer and the plug in the borderless structure. The contact resistance between the semiconductor device and the upper wiring layer can be stably reduced, hillocks can be prevented from occurring, and the characteristics and reliability of the semiconductor device can be improved. It also has the effect of reducing the contact resistance by increasing the contact area between the plug and the upper wiring layer, and the effect of reducing the alignment accuracy in the borderless structure.
Reliability is further improved.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the selective etching using a resist mask uses anisotropic etching in the fourth step. Since the mask naturally disappears, the plug protrusion can be easily formed in a dome shape, and the number of steps can be reduced.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, in the fourth step, isotropic etching is used in the selective etching using a resist mask. Since the resist mask is removed later, the plug protrusion can be easily formed in a tapered shape.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, a first step of forming an insulating layer covering the lower wiring layer formed on the semiconductor substrate, and connecting to the lower wiring layer Forming a resist mask slightly larger than the connection hole size on the insulating layer so as to cover a region where the connection hole is to be formed, and selectively removing the insulating layer by isotropic etching to a predetermined thickness; Process and
A third step of opening the region where the connection hole is to be formed in the insulating layer and forming the connection hole so that the thickness of the insulating layer is increased only around the opening; and forming a plug in the connection hole. And a fifth step of forming an upper wiring layer made of a conductive material different from that of the plug on the insulating layer so as to be in contact with the plug. The generation of side etch at the interface between the upper wiring layer and the plug in the structure can be prevented, the contact resistance between the plug and the upper wiring layer can be reduced stably, and the occurrence of hillocks can also be prevented. The performance is improved.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate; and forming the lower wiring on the insulating layer. A second step of opening a connection hole reaching the layer, a resist slightly larger than the connection hole size is formed on the insulating layer by filling the connection hole, and isotropic etching using the resist mask, A third step of selectively removing the insulating layer by etching to a predetermined thickness so as to increase the thickness only at a portion around the connection hole, a fourth step of burying a plug in the connection hole, Forming an upper wiring layer made of a conductive material different from that of the plug so as to be in contact with the plug, so that when the upper wiring layer is patterned, the upper wiring layer in the borderless structure is formed. Occurrence of side etching at the interface between the plug can be prevented, can stably reduce the contact resistance between the plug and the upper wiring layer, also prevents the occurrence of hillocks, characteristics and reliability of the semiconductor device is improved.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh or eighth aspect, when the insulating layer is selectively isotropically etched, the height of the surface of the insulating layer after the etching is selected. However, since the etching thickness is set so as to be lower than the height of the plug surface formed in a later step, side etching occurs at the interface between the upper wiring layer and the plug in the borderless structure during patterning of the upper wiring layer. As a result, the characteristics and reliability of the semiconductor device are improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional view illustrating a manufacturing step of a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

FIG. 7 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;

FIG. 8 is a sectional view illustrating a manufacturing step of a semiconductor device according to a third embodiment of the present invention;

FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor device according to the third embodiment of the present invention;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor device according to the third embodiment of the present invention;

FIG. 11 is a sectional view illustrating a manufacturing step of the semiconductor device according to the third embodiment of the present invention;

FIG. 12 is a sectional view illustrating a manufacturing step of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 13 is a sectional view illustrating a manufacturing step of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 14 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 11 semiconductor substrate, 12 lower wiring layer, 13 interlayer insulating film as insulating layer, 14 connection hole, 15 plug, 15
a protruding portion, 15b tungsten film as a plug metal film, 17 upper wiring layer, 17a AlCu film constituting upper wiring layer, 18 resist pattern, 20 plug, 20a protruding portion, 20b tungsten film as plug metal film, Reference Signs List 21 resist pattern, 22 interlayer insulating film as insulating layer, 22a connection hole peripheral portion, 23
Plug, 23a Tungsten film as metal film for plug, 24, 28 Resist pattern.

Claims (9)

[Claims] 1. A semiconductor device having an upper and lower wiring layers stacked on a semiconductor substrate via an insulating layer and connected to each other by plugs filled in connection holes provided in the insulating layer, A semiconductor device comprising a conductive material different from the upper wiring layer, the upper portion of which is projected from the surface of the insulating layer as a dome-shaped or tapered projection. 2. A semiconductor device comprising an upper and lower wiring layers stacked on a semiconductor substrate via an insulating layer and connected to each other by plugs filled in connection holes provided in the insulating layer. A semiconductor device, wherein the thickness of the contact hole is increased only in the peripheral portion of the connection hole, and the opening surface of the connection hole is formed higher than the surface of the insulating layer. 3. The semiconductor device according to claim 1, wherein the thickness of the upper wiring layer formed on the insulating layer is reduced in the plug formation region. 4. A first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate, and a second step of opening a connection hole reaching the lower wiring layer in the insulating layer.
A third step of burying the connection hole and forming a plug metal film on the entire surface of the insulating layer; and covering the plug metal film with a resist mask slightly larger than the connection hole size. By selectively etching and removing the plug to a predetermined thickness and then etching back the entire surface, a plug is formed in the connection hole by projecting from the surface of the insulating layer as a dome-shaped or tapered projection at the top. A method of manufacturing a semiconductor device, comprising: a fourth step; and a fifth step of forming an upper wiring layer made of a conductive material different from the plug on the insulating layer so as to be in contact with the plug. . 5. The semiconductor according to claim 4, wherein, in the fourth step, anisotropic etching is used in the selective etching using the resist mask, so that the resist mask disappears spontaneously. Device manufacturing method. 6. The semiconductor device according to claim 4, wherein, in the fourth step, isotropic etching is used in the selective etching using the resist mask, and the resist mask is removed after the etching. Manufacturing method. 7. A first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate, and forming the insulating layer on the insulating layer so as to cover a region where a connection hole to be connected to the lower wiring layer is to be formed. A second step of forming a resist mask slightly larger than the connection hole size, and selectively removing the insulating layer by isotropic etching to a predetermined thickness, and forming the connection hole formation region of the insulating layer. A third step of forming the connection hole such that the insulation layer is thickened only in a portion surrounding the opening, a fourth step of burying a plug in the connection hole, Forming a upper wiring layer made of a conductive material different from that of the plug so as to be in contact with the plug. 8. A first step of forming an insulating layer covering a lower wiring layer formed on a semiconductor substrate, and a second step of opening a connection hole reaching the lower wiring layer in the insulating layer.
A resist slightly larger than the connection hole size is formed on the insulating layer by filling the connection hole, and the insulating layer is selected by isotropic etching using the resist mask so that only the portion around the connection hole is thickened. A third step of selectively etching and removing the plug to a predetermined thickness, a fourth step of burying a plug in the connection hole, and forming an upper wiring layer made of a conductive material different from the plug on the insulating layer. And a fifth step of forming the semiconductor device so as to be in contact with the semiconductor device. 9. When the insulating layer is selectively isotropically etched, the etching thickness is set so that the height of the surface of the insulating layer after the etching is lower than the height of the surface of a plug formed in a later step. 9. The method for manufacturing a semiconductor device according to claim 7, wherein: