TWI512894B - Metal interconnect structure and process thereof - Google Patents

Description

Metal interconnect structure and its process

The invention relates to a metal interconnect structure and a process thereof.

Metal interconnects can be used to connect different components and play a very important role in semiconductor manufacturing. As electronic products continue to be miniaturized, the required component sizes are getting smaller and smaller. However, limited by the critical dimensions of existing exposure machines, small critical size via openings are not easy to fabricate. Moreover, since the size of the opening of the via window is small, the filled oxide layer easily forms voids in the oxide layer, causing a problem of lateral conduction of the subsequently formed via window. On the other hand, although the deposition of yttrium oxide by high-density plasma deposition helps ruthenium oxide to be smoothly filled in the opening of the via window, the deposition of yttrium oxide by high-density plasma deposition is easy to cause the interlayer. The corner of the window opening is cut, so that the critical dimension of the opening of the window opening is uncontrollable, and even the subsequent metal interconnection (such as a bit line) formed in the opening of the via window and the adjacent metal interconnection are caused. A problem with a short circuit (for example, a bit line).

The invention provides a metal interconnect structure and a manufacturing process thereof, which can save the process steps, increase the process margin, improve the coupling problem between the gate conductors, overcome the limit of the critical dimension of the lithography, improve the margin of the stack, and lower the product. the cost of.

Embodiments of the present invention provide a metal interconnect process including providing a substrate on which a first dielectric layer has been formed and a conductor plug has been formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and a via opening is formed in the second dielectric layer. A liner is formed on the surface of the second dielectric layer and the sidewalls and bottom of the via opening. A filling layer is filled in the opening of the via window. A third dielectric layer is formed on the liner. Forming a self-aligned dual damascene structure, self-aligning the dual damascene structure through the third dielectric layer and the filling layer and the liner in the via opening, and electrically connecting with the conductor plug.

Embodiments of the present invention also provide a metal interconnect structure including a substrate, a first dielectric layer, a conductor plug, a second dielectric layer, a third dielectric layer, a self-aligned dual damascene structure, and a liner. The first dielectric layer is on the substrate. The conductor plug is located in the first dielectric layer. The second dielectric layer is on the first dielectric layer. The third dielectric layer is on the second dielectric layer. The self-aligned dual damascene structure is electrically connected to the conductor plug through the third dielectric layer and the second dielectric layer. The liner is between the self-aligned dual damascene structure and the second dielectric layer and between the third dielectric layer and the second dielectric layer.

The above described features and advantages of the present invention will be more apparent from the following description.

10‧‧‧Base

11‧‧‧Conducting area

12, 16, ‧ ‧ dielectric layer

14‧‧‧ Conductor plug

18‧‧‧stop layer

20‧‧‧ bottom anti-reflection layer

22‧‧‧ Cover layer

24, 38‧‧‧Open trench pattern

26, 43‧‧ ‧ through window opening

28‧‧‧ lining

30‧‧‧Filling material layer

30a‧‧‧fill layer

32‧‧‧ pores

36‧‧‧hard mask layer

40, 41‧‧‧ Ditch

42‧‧‧ Self-aligning double metal inlay openings

44‧‧‧ wire

45‧‧‧Conductor layer

46‧‧‧ Self-aligning double damascene structure

1A to 1I are cross-sectional views showing a manufacturing process of an embedded memory device according to a first embodiment of the present invention.

1A to 1I are cross-sectional views showing a manufacturing process of an embedded memory device according to a first embodiment of the present invention.

Referring to Figure 1A, a substrate 10 is provided. Substrate 10 can be a semiconductor or a semiconductor compound such as germanium or germanium. The substrate 10 may also be a layer of germanium (SOI) on the insulating layer. The substrate 10 has a conductive region 11 therein. The conductive region 11 is, for example, a doped region or a conductive layer.

A dielectric layer 12 is formed on the substrate 10. The material of the dielectric layer 12 is, for example, ruthenium oxide, and the formation method is, for example, chemical vapor deposition. The thickness of the dielectric layer 12 is, for example, 4000 Å to 5000 Å. A conductor plug 14 is formed in the dielectric layer 12. The material of the conductor plug 14 may be a metal such as tungsten. The conductor plug 14 is, for example, a bit line contact window.

Next, a dielectric layer 16 is formed over the dielectric layer 12. The material of the dielectric layer 16 is, for example, ruthenium oxide, and the formation method is, for example, chemical vapor deposition. The thickness of the dielectric layer 16 is, for example, 1000 angstroms to 2000 angstroms. Thereafter, a stop layer 18 is formed on the dielectric layer 16. The material of the stop layer 18 is different from the material of the dielectric layer 16. Stop layer 18 material For example, tantalum nitride is formed by, for example, using methane as a reactive gas and depositing by chemical vapor deposition, for example, from 100 angstroms to 600 angstroms. Thereafter, a mask layer 22 is formed on the stop layer 18. The mask layer 22 has an opening pattern 24 corresponding to the conductor plug 14. The material of the mask layer 22 is, for example, a photoresist. A bottom anti-reflective (BARC) layer 20 may be formed on the stop layer 18 prior to forming the mask layer 22. The material of the bottom anti-reflection layer 20 is, for example, an organic polymer or carbon/niobium oxynitride, and is formed by, for example, a liquid spin coating method having a thickness of, for example, 200 angstroms to 400 angstroms.

Referring to FIG. 1B, with the mask layer 22 (FIG. 1A) as a mask, the stop layer 18 and the dielectric layer 16 are etched away to form a via opening 26 to expose the conductor plug 14. The mask layer 22 and the bottom anti-reflective layer 20 are then removed. The method of etching the removal of the stop layer 18 and the dielectric layer 16 may be an anisotropic etch, such as a reactive ion etch. Then, the mask layer 22 and the bottom anti-reflection layer 20 are removed by plasma ionization.

Thereafter, a liner 28 is formed over the dielectric layer 16 to cover the sidewalls and bottom of the stop layer 18 and the via opening 26. The material of the liner 28 is different from the dielectric layer 16. The material of the liner 28 can be the same as the stop layer 18. The material of the underlayer 28 is, for example, tantalum nitride, and is formed by, for example, atomic layer deposition, and has a thickness of, for example, 50 Å to 150 Å. The liner 28 can be used to reduce the size of the via opening 26 and to protect the sidewalls of the via opening 26 during subsequent formation of the self-aligned dual damascene opening.

Referring to FIG. 1C, a fill material layer 30 is then formed on the liner 28 and through the via openings 26. The material of the filler layer 30 is different from the liner 28. The material of the filling material layer 30 is, for example, cerium oxide, and the method of formation is, for example, chemical vapor deposition. The size of the via opening 26 is reduced by the liner 28, which may result in a filler The layer 30 cannot fill the via opening 26 to form the apertures 32. However, since the sidewalls of each via opening 26 are surrounded by a liner 28 of a different material, the apertures 32 in each via opening 26 are not in communication with each other and are also due to liners during subsequent etching processes. The difference between the material of 28 and the dielectric layer 16 avoids lateral communication.

Thereafter, referring to FIG. 1D, the fill material layer 30 over the liner 28 is removed leaving a fill layer 30a in the via opening 26. The method of removing the layer of filler material 30 on the liner 28 is, for example, using the liner 28 as a polishing stop layer, which is removed by chemical mechanical polishing. The liner 28 above the stop layer 18 can also be selectively removed after the fill layer 30 is removed over the liner 28.

Thereafter, a dielectric layer 34 is formed over the liner 28 and the fill layer 30a. The material of the dielectric layer 34 is, for example, ruthenium oxide or a low dielectric constant material such as tantalum carbide, and the formation method is, for example, chemical vapor deposition. The thickness of the dielectric layer 34 is, for example, 500 angstroms to 2,500 angstroms.

Thereafter. A hard mask layer 36 is formed on the dielectric layer 34. The hard mask layer 36 has a plurality of open trench patterns 38 with an open trench pattern 38 over the via opening 26 and corresponding to the via opening 26. The material of the hard mask layer 36 is, for example, polycrystalline germanium, carbon or bismuth oxynitride. The formation method of polycrystalline germanium is, for example, chemical vapor deposition, XX or XX. The method of forming the open trench pattern 38 can be performed through a lithography and etching process.

Next, referring to FIG. 1G, an etching process is performed using the hard mask layer 36 as a mask to form the trench 40 and the self-aligned dual damascene opening 42. ditch 40 passes through dielectric layer 34, liner 28, and stop layer 18. The self-aligned dual damascene opening 42 passes through the dielectric layer 34 and the fill layer 30a and the liner 28 in the via opening 26, exposing the conductor plug 14. The etching process employed can be an anisotropic etch process, such as a reactive ion etch process.

Referring to FIG. 1E, in an embodiment, the trench 40 and the self-aligned dual damascene opening 42 may be first covered with a hard mask layer 36, and the liner 28 is used as an etch stop layer to select a dielectric layer. The layer 34/liner 28 or the first etch condition etch-removal dielectric layer 34 having a high etch selectivity to the dielectric layer 34/stop layer 18 forms the trench 40 and the trench 41. When etching under the first etching condition, since the first etching condition has a high etching selectivity ratio for the dielectric layer 34/liner 28 or for the dielectric layer 34/stop layer 18, the liner is etched during the etching process. The 28 and stop layer 18 can serve as an etch stop layer to protect the surface of the dielectric layer 16.

Next, referring to FIG. 1F, with the hard mask layer 36 as the mask, the liner layer 28 is the stop layer, and the etching conditions are changed to select high etching for the filling layer 30a/liner 28 or for the filling layer 30a/stop layer 18. The filling layer 30a is etched away by selecting a second etching condition to form a via opening 43. Since the filling layer 30a has the pores 32 therein, the material of the filling layer 30a in the via opening 43 is small in volume and can be completely removed more quickly, so that the consumption of the hard mask layer 36 can be reduced. A hard mask layer 36 that is too thick is not required to avoid being exhausted during the etching process. In addition, when the etching is performed under the second etching condition, since the filling layer 30a/liner 28 or the filling layer 30a/stop layer 18 has a high etching selectivity, the liner 28 can serve as a protective layer to protect the dielectric layer 16. Side walls and surfaces to self-align to remove via openings 26 The layer 30a is filled without damaging the sidewalls of the dielectric layer 16. Moreover, when etching under the second etching condition, the liner 28 or the stop layer 18 under the trench 40 can serve as a stop layer to protect the surface of the dielectric layer 16.

Thereafter, referring to FIG. 1G, a third etching condition having a high etching selectivity for the liner 28/dielectric layer 16 or the stop layer 18/dielectric layer 16 is selected to etch the liner 28 and the stop layer 18 below the trench 40. And a liner 28 below the via opening 43. When etching with the third etch condition, the third etch condition has a high etch selectivity for lining 28/dielectric layer 16 or for stop layer 18/dielectric layer 16, thus continuing to etch away trench 40 and self-aligning When the liner 28 and the stop layer 18 at the recess 42 are recessed, the dielectric layer 16 underneath is not overetched. The trench 41 and the via opening 43 form a self-aligned dual damascene opening 42. Since the self-aligned self-aligned dual damascene opening 42 can be formed, there is a good overlap margin between the self-aligned dual damascene opening 42 and the underlying via opening 26 and the conductor plug 14.

Thereafter, referring to FIG. 1H, the hard mask layer 36 is removed. Thereafter, a conductor layer 45 is formed over the dielectric layer 34 to fill the trench 40 and self-align the dual damascene opening 42. The material of the conductor layer 45 is, for example, tungsten or copper. In one embodiment, the conductor layer 45 is a tungsten metal layer, and an adhesion layer (not shown) is formed in the trench 40 and the self-aligned dual damascene opening 42 prior to forming the tungsten metal layer. The material of the adhesive layer is, for example, titanium nitride. In another embodiment, the conductor layer 45 is a copper metal layer, and a barrier layer is formed in the trench 40 and the self-aligned dual damascene opening 42 prior to forming the copper metal layer. The material of the barrier layer is, for example, tantalum nitride.

Referring to FIG. 1I, the excess conductor layer 45 on the dielectric layer 34 is removed to form the wires 44 in the trench 40, and a self-aligned dual damascene structure 46 is formed in the self-aligned dual damascene opening 42 to The conductor plug 14 is electrically connected. A method of removing the excess conductor layer 45 on the dielectric layer 34 is, for example, a chemical mechanical polishing method. In one embodiment, the self-aligned dual damascene structure 46 is used as a bit line. Since the liner 28 can protect the sidewalls of the via opening 26 such that the voids 32 in each via opening 26 are not in communication with each other, the self-aligned dual damascene structure is formed after forming the self-aligned dual damascene structure 46 There is also no problem that there is a short circuit between the two due to the aperture 32.

Referring to FIG. 1I, the metal interconnect structure of the embodiment of the present invention includes a substrate 10, a dielectric layer 12, a conductor plug 14, a dielectric layer 16, a dielectric layer 34, a self-aligned dual damascene structure 46, and a liner. Layer 28. The dielectric layer 12 is on the substrate 10. The conductor plug 14 is located in the dielectric layer 12. Dielectric layer 16 is on dielectric layer 12. Dielectric layer 34 is on dielectric layer 16. The self-aligned dual damascene structure 46 is electrically connected to the conductor plug 14 through the dielectric layer 34 and the dielectric layer 16. The liner 28 is between the self-aligned dual damascene structure 46 and the dielectric layer 16 and between the dielectric layer 34 and the dielectric layer 16. Furthermore, a stop layer 18 is included between the dielectric layer 16 and the liner 28. Moreover, in an embodiment, a fill layer 30a is further included between the liner 28 and the self-aligned dual damascene structure 46. In addition, the metal interconnect structure further includes wires 44 that pass through the dielectric layer 34, the liner 28, and the stop layer 18.

In this embodiment, the dielectric layer 16 is directly formed on the dielectric layer 12, and there is no other high-k material layer between the dielectric layer 16 and the dielectric layer 12, such as nitrogen. The phlegm can not only save the deposition step, but also improve the coupling between the bit line and the gate conductor.

Furthermore, a liner layer 28 is formed on the surface of the dielectric layer 16 and the sidewall of the via opening 26 to protect the sidewalls and corners of the via opening 26 to form a self-aligned self-aligned dual damascene opening 42. Overcoming the limitations of critical dimensions of lithography and corner damage caused by high density plasma (HDP) oxide layers.

In addition, since the sidewalls of the via opening 26 are covered by the liner 28, even if the fill layer 30a in the via opening 26 has apertures 32, it does not cause subsequent formation of the self-aligned dual damascene structure 46 laterally. The problem of conduction. Moreover, the fill layer 30a in the via opening 26 has apertures 32 which in turn help the fill layer 30a to be removed more quickly, thereby reducing the amount of hard mask layer consumed in the etching process.

Furthermore, since the self-aligned self-aligned double damascene opening 42 can be formed, there is a good overlap between the self-aligned double damascene opening 42 and the via window opening 26 and the conductor plug 14 below. degree. In addition, the example of the present invention replaces the single damascene process with a dual damascene process, and the cost of the product can be saved by 2 to 3%.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the lining of the present invention is defined by the scope of the appended claims.

10‧‧‧Base

11‧‧‧Conducting area

12, 16, ‧ ‧ dielectric layer

14‧‧‧ Conductor plug

18‧‧‧stop layer

26‧‧‧Interval window opening

28‧‧‧ lining

30a‧‧‧fill layer

40‧‧‧ Ditch

42‧‧‧ Self-aligning double metal inlay openings

44‧‧‧ wire

46‧‧‧ Self-aligning double damascene structure

Claims (13)

A metal interconnect process includes: providing a substrate, a first dielectric layer is formed on the substrate, and a conductor plug is formed in the first dielectric layer; and a first dielectric layer is formed on the first dielectric layer a second dielectric layer; a first via opening is formed in the second dielectric layer; a liner layer is formed on the surface of the second dielectric layer and the sidewall and the bottom of the first via opening; Forming a filling layer in the first via opening; forming a third dielectric layer on the liner; and forming a self-aligned dual damascene structure, the self-aligned dual damascene structure passing through the third The dielectric layer and the filling layer in the first via opening and the liner are electrically connected to the conductor plug. The metal interconnecting process of claim 1, wherein before forming a first via opening in the second dielectric layer, a stop layer is further formed on the second dielectric layer. The metal interconnect process of claim 2, further comprising forming a wire through the third dielectric layer, the liner, and the stop layer. The metal interconnect process of claim 3, wherein the method of forming the self-aligned dual damascene structure and the wire comprises: forming a hard mask layer on the third dielectric layer, the hard The mask layer has a plurality of opening patterns, one of the opening patterns being located above the first via opening; Etching the hard mask layer to form a first trench and a self-aligned double damascene opening, wherein the first trench passes through the third dielectric layer, the liner, and the stop a self-aligned dual damascene opening through the third dielectric layer and the fill layer in the first via opening and the liner to expose the conductor plug; and in the first trench The wire is formed and the self-aligned dual damascene structure is formed in the self-aligned dual damascene opening. The metal interconnect process of claim 2, wherein the liner is the same material as the stop layer. The metal interconnect process of claim 5, wherein the liner and the material of the stop layer comprise tantalum nitride, and the second dielectric layer and the material of the fill layer comprise tantalum oxide. The metal interconnect process as described in claim 6, wherein the method for forming the liner comprises an atomic layer deposition method. The metal interconnecting process of claim 4, wherein the method of forming the first trench and the self-aligning double damascene opening comprises: using the hard mask layer as a mask, the liner is etched Stopping the layer, etching the third dielectric layer by a first etching condition to form the first trench and a second trench in the third dielectric layer, wherein the second trench exposes the filling layer; The hard mask layer is a mask layer, the lining layer is an etch stop layer, and the filling layer is etched and removed by a second etching condition to form a second via opening communicating with the second trench; Using the hard mask layer as a mask, the liner layer under the trench and the underlayer and the underlayer under the opening of the second via window are removed by a third etching condition, the second trench and the second trench The second via opening constitutes the self-aligned dual damascene opening. A metal interconnect structure includes: a substrate; a first dielectric layer on the substrate, a conductor plug embedded in the first dielectric layer; and a second dielectric layer located in the first dielectric layer a third dielectric layer on the second dielectric layer; a self-aligned dual damascene structure through the third dielectric layer and the second dielectric layer, and the conductor plug An electrical connection; and a liner between the self-aligned dual damascene structure and the second dielectric layer and between the third dielectric layer and the second dielectric layer. The metal interconnect structure of claim 9, further comprising a stop layer between the second dielectric layer and the liner. The metal interconnect structure of claim 10, further comprising a filling layer between the liner and the self-aligned dual damascene structure. The metal interconnect structure of claim 11, wherein the liner is the same material as the stop layer. The metal interconnect structure of claim 10, wherein the liner and the material of the stop layer comprise tantalum nitride, and the second dielectric layer and the material of the fill layer comprise tantalum oxide.