JP2001274677A - Cross couple load type logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cross couple load type logic circuit that can be operated at high-speed. SOLUTION: The cross couple load type logic circuit is provided with a PMOS 1 that applies a high level Vc to each of dynamic nodes D1-D5 in response to a clock signal CLK, an NMOS circuit 2 that discharges any of the dynamic nodes D1-D5 set to the high level Vc in response to an input signal, and a load PMOS group 3 that applies the high level Vc to the dynamic nodes other than the discharged dynamic node in response to the level of the discharged dynamic node. Then the load PMOS group 3 is connected to each of the dynamic nodes D1-D5 via a resistor 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cross-coupled load type logic circuit.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a decoding circuit formed using a conventional cross-coupled load type logic circuit.
FIG. 13 is a circuit diagram showing a basic configuration of a conventional cross-coupled load type logic circuit.

The decoding circuit shown in FIG. 12 is configured by combining five cross-coupled load type logic circuits shown in FIG. This decode circuit is a circuit which receives an input signal and selects one of five outputs OUT (OUT1 to OUT5) by the logic of the NMOS circuit 102 (102-1 to 102-5). The operation will be described below.

When the clock signal CLK is at "LOW" level, it is a precharge period.

In the precharge period, the PMOS 101
(101-1 to 101-5) are turned on, and the high potential Vc is applied to each of the five dynamic nodes D (D1 to D5).
And each of these dynamic nodes D is
Precharge “HIGH” level. At this time, the output OU
The logic levels of T are all "LOW" levels. The load PMO controlled by the potential of the dynamic node D
The S group 103 is turned off.

When the clock signal CLK changes from "LOW" level to "HI"
When the level becomes “GH”, the period shifts from the precharge period to the determination period.

In the determination period, the input signal is applied to the NMOS circuit 1
02 respectively. These NMOS circuits 102
Is determined by the input signal, only one is selected, and only the dynamic node D connected to the selected NMOS circuit 102 is connected to the low potential Vs. As a result, only one selected dynamic node D is discharged, and changes from "HIGH" level to "LOW" level. At this time, the remaining four unselected dynamic nodes D are respectively connected to the load PMOS group 10.
3, it is connected to the high potential Vc and keeps the state of "HIGH" level.

The feature of this circuit is that, unlike a normal dynamic circuit, in response to the potential of the selected dynamic node D, the potentials of the remaining unselected dynamic nodes D are maintained at the "HIGH" level. That is.
Thus, for example, during the determination period, the situation where the unselected dynamic node D is in an electrically floating state can be eliminated, and excellent noise resistance can be obtained.

[0009]

However, in the conventional cross-coupled load type logic circuit, a load PMOS group 103 is connected to each of the dynamic nodes D1 to D5. That is, in addition to the wiring capacitance of the dynamic node D, the load PMOS group 10
The pn junction capacitance between the drain of No. 3 and the semiconductor substrate is further added.

In such a configuration, as the number of dynamic nodes D increases, the number of PMOSs forming the load PMOS group 103 increases, and the capacitance of the dynamic node D increases. As the capacity of the dynamic node D increases, the time required for charging and discharging the dynamic node increases. For this reason,
For example, in the decoding circuit shown in FIG. 12, the output inverter 105 (1
05-1 to 105-5), the time required for each of the outputs OUT to be determined increases, which hinders an increase in operation speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a cross-coupled load type logic circuit capable of achieving high-speed operation.

[0012]

In order to achieve the above object, a cross-coupled load type logic circuit according to the present invention comprises:
A transistor for supplying an initial potential to each of the plurality of dynamic nodes in response to the timing control signal;
A circuit that, in response to an input signal, selects one of the plurality of dynamic nodes set to the initial potential and causes the potential of the selected dynamic node to transition to a potential different from the initial potential; A load transistor group that supplies the initial potential to dynamic nodes other than the dynamic node transitioned to a potential different from the initial potential in response to the potential of the dynamic node transitioned to a potential different from the potential. , The load transistor group, each of the plurality of dynamic nodes,
It is characterized by being connected via a resistor.

In the cross-coupled load type logic circuit having the above configuration, the load transistor group is connected to each of the plurality of dynamic nodes via a resistor.
The capacity of the dynamic node can be reduced.
By reducing the capacity of the dynamic node, the time required for charging and discharging the dynamic node can be reduced. Therefore, it is possible to obtain a cross-coupled load type logic circuit capable of increasing the operation speed.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a decoding circuit formed by using a cross-coupled load type logic circuit according to a first embodiment of the present invention, and FIG. 1 is a circuit diagram illustrating a basic configuration of a cross-coupled load logic circuit according to one embodiment.

As shown in FIGS. 1 and 2, a PMOS 1 (1-1 to 1) is connected between a high potential power supply terminal supplied with the high potential Vc and a low potential power supply terminal supplied with the low potential Vs. -5) and the NMOS circuit 2 (2-1 to 2-5) are connected in series.

Each of the PMOSs 1 has a timing control signal for controlling the operation timing of the decode circuit.
A clock signal CLK is supplied. Each of the PMOSs 1 supplies a high potential Vc to each of connection nodes D (D1 to D5) between the PMOS 1 and the NMOS circuit 2 in response to a clock signal. In this specification, PMOS1 and NM
The connection node D with the OS circuit 2 is hereinafter referred to as a dynamic node.

An input signal is supplied to each of the NMOS circuits 2. The NMOS circuit 2 selects one of a plurality of dynamic nodes D in response to the input signals. As a result, a plurality of outputs OUT (OUT1 to OU
T5) is selected.

Each dynamic node D is cross-coupled to another dynamic node D via a load PMOS 3. Load PMOS
3 are connected between a high potential power supply terminal to which the high potential Vc is supplied and the common connection nodes SD (SD1 to SD5). In this specification, the common connection node SD is hereinafter referred to as a sub-dynamic node for convenience. Each of the sub-dynamic nodes SD is a dynamic node D
Each is provided correspondingly, and is connected to a corresponding dynamic node D via a resistor R (R1 to R5).
In this example, a dynamic node D is used as an example of the resistor R.
And a PMO connected between the sub-dynamic node
S4 (4-1 to 4-4) is shown. Also, the PMOS 4 of this example
Is a normally-on PMOS whose gate is connected to a low potential power supply terminal to which the low potential Vs is supplied.

Next, the operation will be described.

When the clock signal CLK is at the "LOW" level, it is a precharge period.

In the precharge period, the PMOS 1 is turned on, and the high potential Vc is supplied to each dynamic node D. Thereby, the dynamic node D
Are precharged to the “HIGH” level as initial potentials.

At this time, the output inverter 5 (5-1 to 5-)
5) The logic levels of the respective outputs OUT are all "LOW" levels because the dynamic nodes D are all "HIGH" levels. Further, all the load PMOSs 3 are off since the dynamic nodes D are all at the “HIGH” level.

When the clock signal CLK changes from "LOW" level to "HI
When the level becomes “GH”, the period shifts from the precharge period to the determination period.

In the determination period, the PMOS 1 is turned off. Further, an input signal is input to the NMOS circuit 2. The NMOS circuit 2 selects one of the dynamic nodes D in response to the input signal, and connects the selected dynamic node D to the low potential Vs. As a result, one selected dynamic node D is discharged from "HIGH" level to "LOW" level. After this,
The sub-dynamic node SD is discharged with a delay by the time passing through the resistance of the PMOS 4.

Thus, the output OU of the output inverter 5 having its input connected to the selected dynamic node D
For T only, its logic level changes from “LOW” level to “HIGH”
Level. Also, the selected dynamic node D
Is turned on, and the high-potential Vc is applied to the remaining unselected dynamic nodes D.
Is supplied via the sub dynamic node SD and the PMOS 4. As a result, the potentials of the remaining unselected dynamic nodes D maintain the “HIGH” level.

According to the first embodiment, the pn junction capacitance added to the dynamic node D is the pn junction capacitance between the p-type drain of the PMOS 4 and the n-type semiconductor substrate (or n-type well). Only. For this reason, the capacitance of the dynamic node D is reduced as compared with the conventional circuits shown in FIGS.

However, the time until the dynamic node D and the sub-dynamic node SD are completely discharged to the "LOW" level, respectively, is determined by completely changing the dynamic node D of the circuit shown in FIGS. 12 and 13 to the "LOW" level. It is not much different from the time to discharge.

However, since the capacitance of the dynamic node D is reduced, the potential of the dynamic node D is
The transition time from the “HIGH” level to the threshold level of the output inverter 5 is faster in the first embodiment.

Therefore, according to the first embodiment, it is possible to reduce the time from the transition from the precharge period to the determination period to the determination of the logic level of the output OUT, and to achieve a high-speed operation.

Further, since the capacity of the dynamic node D is reduced, the time required for precharging the dynamic node D to the initial potential can be reduced in the first embodiment. For this reason, the precharge period can be shortened.

As described above, according to the cross-coupled load type logic circuit according to the first embodiment, the dynamic node D
, The operation speed can be increased.

(Second Embodiment) FIG. 3 is a circuit diagram showing a basic configuration of a cross-coupled load logic circuit according to a second embodiment of the present invention.

As shown in FIG. 3, the second embodiment is the first embodiment.
The difference from this embodiment is that the PMOS 4 is controlled by a clock signal / CLK having a phase opposite to that of the clock signal CLK.

As described above, by controlling the PMOS 4 with the opposite-phase clock signal / CLK, the PMOS 4 can be kept off during the precharge period. Thereby, the dynamic node D is separated from the sub-dynamic node SD during the precharge period.

According to the second embodiment, the first embodiment
As in the embodiment, the capacitance of the dynamic node D can be reduced.

Further, the dynamic node D can be separated from the sub-dynamic node SD during the precharge period. For this reason, during the precharge period, the PMOS 1
It is sufficient to precharge almost only the dynamic node D.

Therefore, according to the second embodiment, there is obtained an advantage that the time until the dynamic node D is precharged to the “HIGH” level can be further reduced as compared with the first embodiment. Can be.

(Third Embodiment) FIG. 4 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to a third embodiment of the present invention.

As shown in FIG. 4, the third embodiment is the first embodiment.
The difference from this embodiment is that the PMOS 4 is controlled by a signal obtained by further delaying the clock signal / CLK of the opposite phase by the delay 6.

As described above, by controlling the PMOS 4 with a signal obtained by further delaying the clock signal / CLK of the opposite phase,
The PMOS 4 can be turned off even at least during a part of the determination period. Thus, the dynamic node D is separated from the sub-dynamic node SD during a part of the determination period.

According to the third embodiment, the first embodiment
As in the embodiment, the capacitance of the dynamic node D can be reduced.

Further, the dynamic node D can be separated from the sub-dynamic node SD during a part of the determination period. Therefore, during a part of the determination period, the NMO
The S circuit 2 only needs to discharge the dynamic node D alone.

Therefore, according to the third embodiment, the time required for the dynamic node D to be discharged to the threshold level of the output inverter 5 can be further reduced as compared with the first embodiment. Can be obtained.

(Fourth Embodiment) FIG. 5 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to a fourth embodiment of the present invention.

As shown in FIG. 5, the fourth embodiment is the first embodiment.
This embodiment is different from the embodiment of FIG.
Dynamic node D connected to OS 4 (D in the figure)
Except for 1), other dynamic nodes D (D in the figure)
2, D3,..., Dn).

As described above, the PMOS 4 is replaced with the PMOS 4
Is controlled by the logical product of the other dynamic nodes D excluding the dynamic node D connected to. During the determination period, all the dynamic nodes D other than the selected dynamic node D are at the “HIGH” level. Thus, with the circuit shown in FIG. 5, the PMOS 4 connected to the selected dynamic node D can be turned off during the determination period. As a result, the selected dynamic node D is almost completely separated from the sub-dynamic node SD1 during the determination period.

According to the fourth embodiment, the first embodiment
As in the embodiment, the capacitance of the dynamic node D can be reduced.

Further, the dynamic node D can be almost completely separated from the sub-dynamic node SD during the determination period. Therefore, during the determination period, the NMOS circuit 2 only needs to discharge only the dynamic node D.

Therefore, according to the fourth embodiment, the time required for the dynamic node D to be discharged to the threshold level of the output inverter 5 can be further reduced as compared with the first embodiment. Can be obtained.

(Fifth Embodiment) FIG. 6 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to a fifth embodiment of the present invention.

As shown in FIG. 6, the fifth embodiment is the first embodiment.
The difference from this embodiment is that the PMOS 4 is controlled by the logical product (AND) of all the dynamic nodes D (D1, D2,..., Dn in the figure).

As described above, the PMOS 4 is controlled by the logical product of all the dynamic nodes D. Also in such a circuit, the PM connected to the selected dynamic node D during the determination period, as in the circuit according to the fourth embodiment.
The OS 4 can be turned off. As a result, the selected dynamic node D is almost completely separated from the sub-dynamic node SD1 during the determination period.

According to the fifth embodiment, the first embodiment
As in the embodiment, the capacitance of the dynamic node D can be reduced.

Further, the dynamic node D can be almost completely separated from the sub-dynamic node SD during the determination period. Therefore, during the determination period, the NMOS circuit 2 only needs to discharge only the dynamic node D.

Therefore, according to the fifth embodiment, similarly to the fourth embodiment, the time required for discharging the dynamic node D to the threshold level of the output inverter 5 can be further reduced. Can be obtained.

Further, according to the fifth embodiment, since the control is performed by the logical product of all the dynamic nodes D, this logical product gate circuit can be commonly used by all the PMOSs 4. For this reason, compared with the fourth embodiment, it is possible to reduce the number of circuits and obtain an advantage that it is advantageous for high integration.

(Sixth Embodiment) FIG. 7 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to a sixth embodiment of the present invention.

As shown in FIG. 7, the sixth embodiment is the first embodiment.
The difference from this embodiment is that a PMOS 7 controlled by a clock signal CLK is further connected between the power supply terminal to which the high potential Vc is supplied and the sub-dynamic node SD.

By further connecting the PMOS 7 controlled by the clock signal CLK, the high potential Vc is supplied to the sub-dynamic node SD during the precharge period, and the sub-dynamic node SD is charged to the "HIGH" level. it can.

According to the sixth embodiment, the first embodiment
As in the embodiment, the capacitance of the dynamic node D can be reduced.

Further, in the sixth embodiment, the following advantages can be obtained.

The sub dynamic node SD has a load P
Since the MOS3 is connected, the capacitance is larger than the capacitance of the dynamic node D. For this reason, when the PMOS 4 is turned on while the dynamic node D is at the “HIGH” level and the sub-dynamic node SD is at the “LOW” level, the charge stored in the dynamic node D becomes
In some cases, the node moves to the sub-dynamic node SD, and the potential of the dynamic node D becomes “LOW” level. This is a phenomenon called charge sharing.

When such charge sharing occurs,
The dynamic node D temporarily changes from the “HIGH” level to the “LOW” level even though it is not selected. Such a decrease in potential, even if only temporarily, is faster in an integrated circuit.
This can contribute to malfunction.

In the sixth embodiment, during the precharge period, the sub-dynamic node SD
Can be solved by charging to “HIGH” level.

Note that the PMOS 4 shown in FIG.
What is necessary is just to control by any one of the control methods demonstrated by 5th Embodiment.

(Seventh Embodiment) FIG. 8 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to a seventh embodiment of the present invention.

As shown in FIG. 8, the seventh embodiment is the sixth embodiment.
The difference from the third embodiment is that a PMO is provided between the power supply terminal to which the high potential Vc is supplied and the sub dynamic node SD
Instead of S7, an NMOS 8 controlled by the opposite-phase clock signal / CLK is further connected.

In the seventh embodiment, as in the sixth embodiment, it is possible to suppress a decrease in the capacitance of the dynamic node D and a temporary decrease in the potential of the dynamic node D due to charge sharing. Can be.

Further, in the seventh embodiment, during the precharge period, the sub-dynamic node SD is connected to the high potential Vc
Is charged to a potential obtained by subtracting the threshold voltage of the NMOS 8, that is, an intermediate potential between the high potential Vc and the low potential Vs. For this reason, the precharge potential of the sub dynamic node SD can be suppressed lower than in the sixth embodiment.

As described above, in the seventh embodiment, the pre-charge potential of the sub-dynamic node SD is suppressed to be low, so that the selected dynamic node D can be set to the threshold of the output inverter 5 as compared with the sixth embodiment. There is an advantage that the time for transition to the value level is easily reduced.

Note that the PMOS 4 shown in FIG.
What is necessary is just to control by any one of the control methods demonstrated by 5th Embodiment.

(Eighth Embodiment) FIG. 9 is a circuit diagram showing a basic configuration of a cross-coupled load type logic circuit according to an eighth embodiment of the present invention.

As shown in FIG. 9, the eighth embodiment is the first embodiment.
The difference from this embodiment is that an NMOS 9 controlled by a clock signal / CLK having an opposite phase is further connected between the power supply terminal to which the low potential Vs is supplied and the sub-dynamic node SD.

In the eighth embodiment, as in the first embodiment, the capacitance of the dynamic node D can be reduced.

Further, in the eighth embodiment, during the precharge period, the sub dynamic node SD is connected to the PMOS 9
As a result, the battery can be discharged to the low potential Vs (“LOW” level). Therefore, when discharging the selected dynamic node D via the NMOS circuit 2, only the dynamic node D needs to be discharged. Therefore,
As compared with the first embodiment, there is an advantage that the time for discharging the output inverter 5 to the threshold level can be further reduced.

Note that the PMOS 4 shown in FIG.
What is necessary is just to control by any one of the control methods demonstrated by 5th Embodiment.

In the eighth embodiment, the sub-dynamic node SD is kept at the "LOW" level during the precharge period. Therefore, when the capacitance of the sub-dynamic node SD is larger than the capacitance of the dynamic node D, It is feared that the above-mentioned charge share becomes remarkable.

Therefore, in the eighth embodiment, for example, an integrated circuit in which a load PMOS group 3 and the like are formed on an SOI substrate and a pn junction between a p-type drain and an n-type semiconductor substrate (or an n-type well) is eliminated. Is preferably applied.

(Ninth Embodiment) FIG. 10 is a circuit diagram showing a decoding circuit constituted by using a cross-coupled load type logic circuit according to a ninth embodiment of the present invention, and FIG.
11 is a circuit diagram showing a basic configuration of the circuit shown in FIG.

As shown in FIGS. 10 and 11, the difference between the ninth embodiment and the first to eighth embodiments is that the load P
That is, the MOS group 3 is controlled by inverters 10-1 to 10-5 to which outputs OUT1 to OUT5 are input.

According to the ninth embodiment, the dynamic node D does not need to be connected to the gate of the load PMOS group 3, so that the dynamic node D is not connected to the dynamic node D as compared with the first to eighth embodiments. The capacity can be further reduced.

Thus, in the ninth embodiment, the first to eighth
The effect that the operation can be further speeded up as compared with the embodiment can be obtained.

The PMOS 4 shown in FIGS.
May be controlled by any of the control methods described in the first to fifth embodiments.

The ninth embodiment can be used together with all of the first to eighth embodiments.

As described above, the present invention has been described with reference to the first to ninth embodiments. However, the present invention is not limited to these embodiments, and can be variously modified without departing from the gist thereof. .

For example, in the cross-coupled load type logic circuits described in the first to ninth embodiments, one of the dynamic nodes D precharged to “HIGH” level is selected by the logic of the NMOS circuit 2 and selected. Only the changed dynamic node D is changed to the “LOW” level. Such a logic circuit is, for example, an AND circuit (AND, NAN)
D) can be used.

However, the present invention, on the other hand,
Dynamic node D precharged to W "level
Is selected, and only the selected dynamic node D is transited to the “HIGH” level. Such a logic circuit can be used, for example, for an OR circuit (OR, NOR).

When the present invention is applied to a logic circuit in which the dynamic node D is precharged to the “LOW” level and only the selected dynamic node D is changed to the “HIGH” level, the dynamic node D is set to the high level. The PMOS 1 that supplies the potential Vc is changed to an NMOS that supplies the low potential Vs to the dynamic node D, and the NMOS circuit 2 is changed to a PMOS circuit. Further, a load PMOS3 for supplying the high potential Vc to the sub-dynamic node SD is provided.
The PMOS 4 forming the resistor R is changed to a load NMOS that supplies the low potential Vs to the sub-dynamic node SD.
What is necessary is just to change to NMOS.

In the case of such a change, the AND gate circuits described in the fourth and fifth embodiments are changed to, for example, OR gate circuits.

[0091]

As described above, according to the present invention, it is possible to provide a cross-coupled load type logic circuit capable of increasing the operation speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a decoding circuit configured using a cross-coupled load type logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a cross-coupled load logic circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a cross-coupled load logic circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a cross-coupled load type logic circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a cross-coupled load type logic circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a cross-coupled load type logic circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a cross-coupled load logic circuit according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a cross-coupled load logic circuit according to a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing a cross-coupled load type logic circuit according to an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a decoding circuit configured using a cross-coupled load type logic circuit according to a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a cross-coupled load type logic circuit according to a ninth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a decoding circuit configured using a conventional cross-coupled load logic circuit.

FIG. 13 is a circuit diagram showing a conventional cross-coupled load logic circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... PMOS, 2 ... NMOS circuit, 3 ... Load PMOS group, 4 ... Resistance, 5 ... Output inverter, 6 ... Delay, 7 ... PMOS, 8 ... NMOS, 9 ... NMOS, 10 ... Inverter.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J042 BA02 BA19 CA09 CA12 CA22 CA27 DA03 5J055 AX02 AX54 AX64 BX10 CX01 DX22 DX44 DX83 DX88 EX07 EY21 EZ00 EZ19 EZ25 EZ38 FX35 GX01

Claims (10)

[Claims] A first transistor that supplies an initial potential to each of a plurality of dynamic nodes in response to a timing control signal; and a plurality of dynamic nodes that are set to an initial potential in response to an input signal. A circuit for selecting one of the potentials and transitioning the potential of the selected dynamic node to a potential different from the initial potential; and responding to the potential of the dynamic node transitioned to a potential different from the initial potential, Comprises a load transistor group that supplies the initial potential to a dynamic node other than the dynamic node transitioned to a different potential, and the load transistor group is connected to each of the plurality of dynamic nodes via a resistor. A cross-coupled load type logic circuit. 2. The logic circuit according to claim 1, wherein the resistor is a normally-on transistor. 3. The logic circuit according to claim 1, wherein the resistor is a transistor controlled by a timing control signal having a phase opposite to that of the timing control signal. 4. The cross-coupled load-type logic circuit according to claim 1, wherein the resistor is a transistor controlled by a signal obtained by delaying the timing control signal. 5. The cross-coupled load logic circuit according to claim 1, wherein said resistor is a transistor controlled in accordance with a potential of a dynamic node other than a dynamic node to which said resistor is connected. . 6. The cross-coupled load logic circuit according to claim 1, wherein said resistor is a transistor controlled according to the potential of all of said dynamic nodes. 7. The cross according to claim 1, further comprising a transistor that supplies the initial potential to a connection node between the resistor and the load transistor group. Couple load type logic circuit. 8. The cross-coupled load logic circuit according to claim 7, wherein the transistor for supplying the initial potential is an N-channel type. 9. The semiconductor device according to claim 1, further comprising: a transistor for supplying, to a connection node between the resistor and the load transistor group, the same potential as the discharged potential or the charged potential of the dynamic node. A cross-coupled load type logic circuit according to any one of claims 1 to 6. 10. The semiconductor device further comprising a buffer circuit connected to each of the plurality of dynamic nodes, wherein the load transistor group is connected to a potential of the buffer circuit connected to the dynamic node that has transitioned to a potential different from the initial potential 10. The cross according to any one of claims 1 to 9, wherein the initial potential is supplied to a dynamic node other than the dynamic node transitioned to a potential different from the initial potential in response to Couple load type logic circuit.