JP2001274348A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2001274348A JP2001274348A JP2000083827A JP2000083827A JP2001274348A JP 2001274348 A JP2001274348 A JP 2001274348A JP 2000083827 A JP2000083827 A JP 2000083827A JP 2000083827 A JP2000083827 A JP 2000083827A JP 2001274348 A JP2001274348 A JP 2001274348A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sro
- semiconductor device
- ruthenium
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 41
- 230000001681 protective effect Effects 0.000 claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000000354 decomposition reaction Methods 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 description 23
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 239000010410 layer Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 238000002441 X-ray diffraction Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 101000617550 Dictyostelium discoideum Presenilin-A Proteins 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- JFWLFXVBLPDVDZ-UHFFFAOYSA-N [Ru]=O.[Sr] Chemical compound [Ru]=O.[Sr] JFWLFXVBLPDVDZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- UFQXGXDIJMBKTC-UHFFFAOYSA-N oxostrontium Chemical compound [Sr]=O UFQXGXDIJMBKTC-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、より詳しくは、ルテニウムを含む導
電膜、例えばストロンチウム・ルテニウム酸化膜(SR
O膜)、ルテニウム(Ru)を有する半導体装置及びその
製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a conductive film containing ruthenium, for example, a strontium-ruthenium oxide film (SR).
O film), ruthenium (Ru), and a method for manufacturing the same.
【0002】[0002]
【従来の技術】(Ba,Sr)TiO3(BST)膜、SrTiO3(S
TO)膜、Ta2O5 膜等の誘電体膜を2つのSRO膜又は
Ru膜により挟んだ構造を有するキャパシタは、高い容量
と低いリーク電流を有することが知られている。これ
は、ギガビットDRAMのような新たな世代のメモリ素
子の要求に適している。2. Description of the Related Art (Ba, Sr) TiO 3 (BST) film, SrTiO 3 (S
A dielectric film such as a (TO) film, a Ta 2 O 5 film,
It is known that a capacitor having a structure sandwiched between Ru films has a high capacity and a low leakage current. This is suitable for the demand of a new generation memory device such as a gigabit DRAM.
【0003】そのSROは、トランジスタ特性を改善す
るための水素アニーリングの最中にルテニウム(Ru)と酸
化ストロンチウム(SrO) に分解することが知られてい
る。また、BST、STO等をベースにしたMIM(met
al-insulator-metal) キャパシタのリーク電流は、水素
アニーリングの後に増加するのが一般的である。そのよ
うなリーク電流の増加を防止するためには上部電極の水
素透過を防止することが好ましいので、キャパシタの上
部電極を保護膜によって覆う方法が採用されている。[0003] It is known that SRO decomposes into ruthenium (Ru) and strontium oxide (SrO) during hydrogen annealing to improve transistor characteristics. In addition, MIM (met
al-insulator-metal) The leakage current of a capacitor generally increases after hydrogen annealing. In order to prevent such an increase in leakage current, it is preferable to prevent hydrogen permeation through the upper electrode, and a method of covering the upper electrode of the capacitor with a protective film has been adopted.
【0004】アルミナ(Al2O3) は、プラチナ又はルテニ
ウムよりなる上部電極用の保護膜として適している。従
来のキャパシタの構造の断面を図1に示す。図1におい
て、シリコン基板1の上に形成された第一の絶縁膜2に
は、半導体基板1内の不純物拡散層3に繋がるコンタク
トホール2aが形成されている。そのコンタクトホール
2a内にはタングステンプラグ4aとバリアメタル4b
が順に埋め込まれ、そのバリアメタル4bと第一の絶縁
膜2の上には、キャパシタ5が形成されている。キャパ
シタ5は、第一のSRO膜からなる下部電極5aと、B
ST膜からなる誘電体膜5bと、第二のSRO膜からな
る上部電極5cとによって構成されている。Alumina (Al 2 O 3 ) is suitable as a protective film for the upper electrode made of platinum or ruthenium. FIG. 1 shows a cross section of the structure of a conventional capacitor. In FIG. 1, a contact hole 2a connected to an impurity diffusion layer 3 in a semiconductor substrate 1 is formed in a first insulating film 2 formed on a silicon substrate 1. In the contact hole 2a, a tungsten plug 4a and a barrier metal 4b are provided.
Are sequentially embedded, and a capacitor 5 is formed on the barrier metal 4b and the first insulating film 2. The capacitor 5 includes a lower electrode 5a made of a first SRO film,
It is composed of a dielectric film 5b made of an ST film and an upper electrode 5c made of a second SRO film.
【0005】そのようなキャパシタ5は、第二の絶縁膜
6によって覆われており、その第2の絶縁膜6に形成さ
れたホール6a内には上部電極5cに接続されるプラグ
7が形成されている。そのプラグ7は、ホール内にチタ
ン(Ti)7a、窒化チタン(TiN) 7b、タングステン
(W)7cが順に形成された多層構造を有している。[0005] Such a capacitor 5 is covered with a second insulating film 6, and a plug 7 connected to the upper electrode 5 c is formed in a hole 6 a formed in the second insulating film 6. ing. The plug 7 has a multilayer structure in which titanium (Ti) 7a, titanium nitride (TiN) 7b, and tungsten (W) 7c are sequentially formed in a hole.
【0006】[0006]
【発明が解決しようとする課題】そのような構造におい
て、水素アニーリングは、SROを分解するおそれがあ
るし、BST膜にも悪い影響を与え、これらは、SRO
/BST/SROを有するキャパシタの電気的特性を劣
化させる原因になる。そこで、第二のSRO膜7cをア
ルミナ膜によって覆うことも考えられるが、ギガビット
DRAMの実際の構造において、アルミナ膜を微細にパ
ターニングすることは難しい。In such a structure, hydrogen annealing can decompose the SRO and also adversely affect the BST film,
/ BST / SRO causes deterioration of the electrical characteristics of the capacitor. Therefore, it is conceivable to cover the second SRO film 7c with an alumina film, but it is difficult to finely pattern the alumina film in the actual structure of the gigabit DRAM.
【0007】また、上記したプラグ7のチタン7aとS
RO上部電極5cが反応して酸化チタン(TiOx ) が形成
されると、プラグ7と上部電極5cのコンタクト抵抗は
非常に高くなる。本発明の目的は、SRO分解とキャパ
シタ電気特性劣化を防止し、さらに、キャパシタの上部
電極とプラグの間のコンタクト抵抗を減らすことができ
る半導体装置及びその製造方法を提供することにある。Further, the titanium 7a of the plug 7 and S
When the RO upper electrode 5c reacts to form titanium oxide (TiO x ), the contact resistance between the plug 7 and the upper electrode 5c becomes extremely high. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can prevent SRO decomposition and deterioration of electric characteristics of a capacitor, and can reduce contact resistance between an upper electrode of a capacitor and a plug.
【0008】[0008]
【課題を解決するための手段】上記した課題は、半導体
基板上方に形成されたルテニウムを含む導電膜の上に、
下から順に酸化シリコンと窒化シリコンを積層してなる
二層構造膜と窒化チタン膜の少なくとも1つを保護膜と
して形成する工程と、前記保護膜の形成後に前記半導体
基板を還元雰囲気中で加熱する工程とを有する半導体装
置の製造方法によって解決される。SUMMARY OF THE INVENTION The above-mentioned problem is solved by forming a ruthenium-containing conductive film formed above a semiconductor substrate on a conductive film.
Forming at least one of a two-layer structure film formed by stacking silicon oxide and silicon nitride and a titanium nitride film in order from the bottom as a protective film, and heating the semiconductor substrate in a reducing atmosphere after the formation of the protective film. And a method of manufacturing a semiconductor device having the above steps.
【0009】その半導体装置の製造方法において、前記
ルテニウムを含む導電膜を形成する前に、前記半導体基
板の上に第一の絶縁膜を形成し、該第一の絶縁膜内に第
一のプラグを埋め込み、該第一のプラグに接続されるキ
ャパシタ下部電極を前記第一の絶縁膜上に形成し、キャ
パシタ下部電極の上にキャパシタ誘電体膜を形成した後
に、該キャパシタ誘電体膜の上に前記ルテニウムを含む
導電膜をキャパシタ上部電極として形成し、 さらに、
前記保護膜の上に第二の絶縁膜を形成し、該第二の絶縁
膜に、前記ルテニウムを含む導電膜に電気的に接続され
る第二のプラグを埋め込んでもよい。この場合、前記キ
ャパシタ誘電体膜は、BST、Ta2O5 、STO又はPZ
Tのいずれかであってもよい。また、前記第2のプラグ
は、前記ルテニウムを含む導電膜の上に、窒化チタン膜
を介して形成されたタングステン又はアルミニウムを含
む膜から構成されてもよい。In the method of manufacturing a semiconductor device, a first insulating film is formed on the semiconductor substrate before the conductive film containing ruthenium is formed, and a first plug is formed in the first insulating film. Embedded, a capacitor lower electrode connected to the first plug is formed on the first insulating film, a capacitor dielectric film is formed on the capacitor lower electrode, and then the capacitor dielectric film is formed on the capacitor dielectric film. Forming the conductive film containing ruthenium as a capacitor upper electrode;
A second insulating film may be formed over the protective film, and a second plug electrically connected to the conductive film containing ruthenium may be embedded in the second insulating film. In this case, the capacitor dielectric film is made of BST, Ta 2 O 5 , STO or PZ.
It may be any of T. Further, the second plug may be made of a film containing tungsten or aluminum formed on the conductive film containing ruthenium via a titanium nitride film.
【0010】また、上記した課題は、半導体基板上方に
形成されたルテニウムを含む導電膜と、前記ルテニウム
を含む導電膜の上に形成され、かつ、下から順に酸化シ
リコンと窒化シリコンを積層してなる二層構造膜と窒化
チタン膜の少なくとも1つからなる保護膜とを有するこ
とを特徴とする半導体装置によって解決される。上記し
た半導体装置において、前記二層構造膜を構成する前記
酸化シリコンは50nmよりも薄いことが好ましい。ま
た、前記窒化チタン膜は、20nmより薄いことが好ま
しい。Another object of the present invention is to form a conductive film containing ruthenium formed above a semiconductor substrate and a silicon oxide and a silicon nitride formed on the conductive film containing ruthenium in order from the bottom. The problem is solved by a semiconductor device having a two-layered structure film and a protective film made of at least one of a titanium nitride film. In the above-described semiconductor device, it is preferable that the silicon oxide forming the two-layer structure film is thinner than 50 nm. Preferably, the titanium nitride film is thinner than 20 nm.
【0011】次に、本発明の作用について説明する。本
発明によれば、ルテニウムを含む導電膜の上に形成され
る保護膜として、酸化シリコンと窒化シリコンからなる
二層構造膜と窒化チタン膜のうち少なくとも1つを選択
している。そのような保護膜によれば、基板を還元雰囲
気中でアニールしても、ルテニウムを含む導電膜、例え
ばSRO膜が分解、劣化することが防止され、しかも、
その導電膜とその上に形成されるプラグとのコンタクト
抵抗が殆ど上昇せず、保護膜に剥がれが生じることはな
い。Next, the operation of the present invention will be described. According to the present invention, as the protective film formed on the conductive film containing ruthenium, at least one of a two-layer structure film made of silicon oxide and silicon nitride and a titanium nitride film is selected. According to such a protective film, even if the substrate is annealed in a reducing atmosphere, the conductive film containing ruthenium, for example, an SRO film is prevented from being decomposed and deteriorated.
The contact resistance between the conductive film and the plug formed thereon hardly increases, and the protective film does not peel off.
【0012】[0012]
【発明の実施の形態】以下に本発明の実施形態を図面に
基づいて説明する。キャパシタの上部電極となるSRO
膜の上に形成される保護膜として、CVD法により成長
し、ギガビットDRAMの構造を実際にパターニングす
ることについて調べるために、複数の材料及び構造につ
いて試料を作成し、以下のような実験を行った。Embodiments of the present invention will be described below with reference to the drawings. SRO to be the upper electrode of the capacitor
As a protective film formed on the film, a sample was prepared for a plurality of materials and structures in order to investigate the fact that the structure of a gigabit DRAM was actually patterned by the CVD method, and the following experiment was performed. Was.
【0013】まず、SRO膜の上に保護膜を形成しない
構造を第1の試料とし、SRO膜を窒化シリコン(SiN
)で覆ったSiN /SRO構造を第2の試料とし、SR
O膜を酸化シリコン(SiO2)で覆ったSiO2/SRO構造
を第3の試料とし、SRO膜の上に酸化シリコン膜と窒
化シリコン膜を順に形成したSiN /SiO2/SRO構造を
第4の試料とし、SRO膜を窒化チタン(TiN )膜で覆
ったTiN /SRO構造を第5の試料とした。First, a structure in which a protective film is not formed on the SRO film is used as a first sample, and the SRO film is made of silicon nitride (SiN).
) Covered with SiN / SRO structure as the second sample
A third sample is an SiO 2 / SRO structure in which an O film is covered with silicon oxide (SiO 2 ), and a fourth sample is a SiN / SiO 2 / SRO structure in which a silicon oxide film and a silicon nitride film are sequentially formed on the SRO film. The fifth sample was a TiN / SRO structure in which the SRO film was covered with a titanium nitride (TiN) film.
【0014】そして、それら第1〜第5の試料を、フォ
ーミングガス雰囲気中で基板温度400℃、加熱時間6
0分でアニーリングしたところ、表1と以下の図に示す
ような結果が得られた。この場合、フォーミングガスと
して3%水素と窒素の混合ガスを用いた。Then, the first to fifth samples are placed in a forming gas atmosphere at a substrate temperature of 400 ° C. for a heating time of 6 hours.
Annealing at 0 minutes resulted in the results shown in Table 1 and the following figures. In this case, a mixed gas of 3% hydrogen and nitrogen was used as the forming gas.
【0015】[0015]
【表1】 [Table 1]
【0016】第1の試料 図2(a) は、SRO膜を形成した直後の試料1の断面を
示すSEM写真で、図2(b) は、その試料1を上記した
条件でアニールした後の断面を示すSEM写真である。
それらのSEM写真から明らかなように、SRO膜の上
に保護膜を形成しない状態でSRO膜をアニールする
と、SRO膜の表面に荒れが生じることがわかった。The first sample shown in FIG. 2 (a) is a SEM photograph showing a sample 1 of the section immediately after the formation of the SRO film, FIG. 2 (b), after annealing the sample 1 under the conditions described above It is a SEM photograph which shows a cross section.
As is clear from these SEM photographs, it was found that if the SRO film was annealed in a state where the protective film was not formed on the SRO film, the surface of the SRO film was roughened.
【0017】また、SRO膜についてアニール前と後の
X線回折パターンを見ると、表1に示すようにアニール
の後には、SRO膜の(121)面を示すピークが消滅
していた。また、SRO膜を露出したままでアニールす
ると、SRO膜は分解されてルテニウムが発生すること
がわかった。第2の試料 図3は、SiN /SRO構造を第2の試料を形成した直
後、即ちSRO膜の上にSiN 膜を形成した直後の断面を
示すSEM写真であり、荒れが発生している。When the X-ray diffraction patterns of the SRO film before and after annealing were observed, as shown in Table 1, after annealing, the peak indicating the (121) plane of the SRO film had disappeared. Further, it was found that when annealing was performed with the SRO film exposed, the SRO film was decomposed and ruthenium was generated. Second Sample FIG. 3 is an SEM photograph showing a cross section of the SiN / SRO structure immediately after forming the second sample, that is, immediately after forming the SiN film on the SRO film.
【0018】その第2の試料について、成膜直後のX線
回折パターンを見ると、表1に示すように、SRO膜の
(121)面を示すピークが始めから存在せず、ルテニ
ウムが発生していることがわかった。そのようにSRO
膜の上にSiN 膜を形成すると、SRO膜が劣化するの
は、SiN 成長の際に使用するガス、即ちシラン(SiH4)
ガスとアンモニア(NH3) ガスによってSRO膜が還元さ
れるからと考えられる。Looking at the X-ray diffraction pattern of the second sample immediately after film formation, as shown in Table 1, the peak indicating the (121) plane of the SRO film did not exist from the beginning, and ruthenium was generated. I understood that. Like that SRO
When a SiN film is formed on the film, the SRO film is deteriorated only by the gas used for growing the SiN, ie, silane (SiH 4 ).
It is considered that the SRO film is reduced by the gas and the ammonia (NH 3 ) gas.
【0019】以上のことから、SRO膜の上にSiN 膜を
形成している間にSRO膜は既に分解していることがわ
かり、第2の試料をアニールする意味が無くなってい
る。第3の試料 図4(a) は、SRO膜を酸化シリコン(SiO2)で覆った
直後の第3の試料の断面を示すSEM写真で、図4(b)
は、その第3の試料を上記した条件でアニールした後の
断面を示すSEM写真である。From the above, it can be seen that the SRO film has already been decomposed while the SiN film is being formed on the SRO film, and there is no point in annealing the second sample. The third sample view. 4 (a), SRO film silicon oxide by SEM photograph showing a third sample of the cross-section immediately covered with (SiO 2), FIG. 4 (b)
Is a SEM photograph showing a cross section of the third sample after annealing under the above conditions.
【0020】それらの写真から明らかなように、第3の
試料をアニールした後に、SRO膜は変質することが分
かった。アニール前と後のSRO膜のX線回折パターン
を見ると、表1に示すようにアニールの後には、SRO
膜の(121)面を示すピークがシフトしていた。しか
し、そのSRO膜は、ルテニウムのピークが現れるよう
な分解は発生しないことがわかった。As is apparent from these photographs, it was found that the SRO film deteriorated after annealing the third sample. Looking at the X-ray diffraction patterns of the SRO film before and after annealing, as shown in Table 1, after annealing, SRO film
The peak indicating the (121) plane of the film was shifted. However, it was found that the SRO film did not undergo decomposition such that a ruthenium peak appeared.
【0021】なお、第3の試料と次の第4の試料でのSi
O2膜の形成はTEOS(テトラエトキシシラン)を用い
たCVD法によって形成される。第4の試料 図5(a) は、第4の試料を作成した直後のSEM写真で
あり、図5(b) は、その第4の試料を上記条件でアニー
ルした後の断面を示すSEM写真である。In the third sample and the next fourth sample, the Si
The O 2 film is formed by a CVD method using TEOS (tetraethoxysilane). Fourth Sample FIG. 5 (a) is an SEM photograph immediately after the fourth sample was prepared, and FIG. 5 (b) is a SEM photograph showing a cross section of the fourth sample after annealing under the above conditions. It is.
【0022】それらの写真から明らかなように、第4の
試料をアニールした後に、SRO膜に変化は見られない
ことが分かった。アニール前と後のSRO膜のX線回折
パターンを見ると、表1に示すようにアニールの前と後
には、いずれもSRO膜の(121)面を示すピークが
存在し、ルテニウムのピークが現れていないことがわか
った。しかも、コンタクト抵抗を測定してもアニールの
前と後で殆ど変化が生じない。As is clear from the photographs, it was found that no change was observed in the SRO film after the fourth sample was annealed. Looking at the X-ray diffraction patterns of the SRO film before and after annealing, as shown in Table 1, before and after annealing, a peak indicating the (121) plane of the SRO film was present, and a ruthenium peak appeared. I knew it wasn't. Moreover, even if the contact resistance is measured, little change occurs before and after annealing.
【0023】したがって、SRO膜の上にSiO2膜を形成
し、そのSiO2膜の上にSiN 膜を形成した保護膜は安定で
あり、SRO膜の変質や分解を防止するのに有効である
ことがわかる。この場合、SiO2膜は50nm以下の厚さ
にすることが好ましい。第5の試料 図6は、基板温度を20℃以上で400℃より低い範囲
内に設定し、SRO膜の上に厚さ20nmのTiN 膜を形
成して作成された直後の第5の試料のSEM写真であ
る。この第5の試料を上記した条件でアニールすると、
図7(a) に示すようなSEM写真が得られ、TiN 膜に部
分的な剥がれが生じていることが分かった。そのSEM
写真を倍率を小さくしてみると、図7(b) に示すよう状
態になり、TiN 膜の表面に凹凸が生じてTiN 膜に膜剥が
れが生じ易くなる。Therefore, the protective film in which the SiO 2 film is formed on the SRO film and the SiN film is formed on the SiO 2 film is stable and is effective for preventing the SRO film from being deteriorated or decomposed. You can see that. In this case, it is preferable that the SiO 2 film has a thickness of 50 nm or less. Fifth Sample FIG. 6 shows a fifth sample immediately after being formed by setting a substrate temperature within a range of 20 ° C. or higher and lower than 400 ° C. and forming a 20 nm-thick TiN film on the SRO film. It is a SEM photograph. When this fifth sample is annealed under the above conditions,
An SEM photograph as shown in FIG. 7A was obtained, and it was found that the TiN film was partially peeled. The SEM
When the photograph is reduced in magnification, the state becomes as shown in FIG. 7 (b), and the surface of the TiN film becomes uneven, so that the TiN film is easily peeled off.
【0024】これに対して、SRO膜の上に厚さ5nm
のTiN 膜を形成し、これを上記した条件でアニールした
ところ、図8のようなSEM写真が得られ、TiN 膜の表
面には凹凸が発生しなかった。また、SRO膜の上のTi
N 膜の膜厚を20nmよりも薄くした場合には、そのア
ニール後にも凹凸が発生せず、しかも、コンタクト抵抗
は殆ど変化が生なかった。On the other hand, the SRO film has a thickness of 5 nm.
When a TiN film was formed and annealed under the above conditions, an SEM photograph as shown in FIG. 8 was obtained, and no irregularities were generated on the surface of the TiN film. Also, Ti on the SRO film
When the thickness of the N film was smaller than 20 nm, no irregularities occurred even after annealing, and the contact resistance hardly changed.
【0025】なお、TiN 膜の形成時の基板温度を400
℃以上にすると、SRO膜とTiN 膜が反応するので好ま
しくない。例えば、基板温度を500℃としてSRO膜
上にTiN 膜を形成すると、SRO膜は酸素を失い、SR
O膜とTiN 膜の間には酸化チタン(TiO2)が形成され
る。その酸化チタンによりSRO膜とTiN 膜の間に寄生
容量が生じて、キャパシタの総容量が低くなってしま
う。The substrate temperature at the time of forming the TiN film is 400
C. or higher is not preferable because the SRO film reacts with the TiN film. For example, when the substrate temperature is set to 500 ° C. and a TiN film is formed on the SRO film, the SRO film loses oxygen,
Titanium oxide (TiO 2 ) is formed between the O film and the TiN film. The titanium oxide causes a parasitic capacitance between the SRO film and the TiN film, and the total capacitance of the capacitor is reduced.
【0026】以上のことから、SRO膜の保護膜として
厚さ20nmよりも薄いTiN 膜が有効であることがわか
る。上記した第1〜第5の試料のSEM写真とX線回折
によれば、SRO膜のアニール時の保護膜として、酸化
シリコン膜と窒化シリコン膜の二層構造か、あるいは膜
厚20nmより薄い窒化チタン膜が、SRO膜の分解を
防止し、上部電極とタングステンプラグのコンタクト抵
抗を低減させるもことがわかった。したがって、そのよ
うな保護膜は、SRO/BST/SROキャパシタの劣
化を防止するために有効である。From the above, it can be seen that a TiN film thinner than 20 nm is effective as a protective film for the SRO film. According to the SEM photograph and the X-ray diffraction of the above-mentioned first to fifth samples, as the protective film at the time of annealing of the SRO film, a two-layer structure of a silicon oxide film and a silicon nitride film or a nitride film having a thickness less than 20 nm It has been found that the titanium film prevents the decomposition of the SRO film and reduces the contact resistance between the upper electrode and the tungsten plug. Therefore, such a protective film is effective for preventing deterioration of the SRO / BST / SRO capacitor.
【0027】次に、SRO膜の保護膜としてSiN /SiO2
の二層構造膜、又は20nmより薄い窒化チタン膜を用
いた場合のキャパシタ構造を図9、図10に基づいて説
明する。図9において、シリコン基板11の表面にはL
OCOS膜12に隣接して不純物拡散層13が形成され
ている。そのシリコン基板11の上には、SiO2、PS
G、BPSG等の第一の層間絶縁膜14が形成され、そ
のうち不純物拡散層13の上にはコンタクトホール15
が形成されている、コンタクトホール15内には、タン
グステン層16a上にバリアメタル層16bを重ねて構
成される第一のプラグ16が形成されている。また、第
一のプラグ16と第一の層間絶縁膜14の上には第二の
層間絶縁膜17が形成され、そこには第一のプラグ16
を露出する凹部18が形成されている。Next, SiN / SiO 2 is used as a protective film for the SRO film.
The capacitor structure in the case of using the two-layer structure film or the titanium nitride film thinner than 20 nm will be described with reference to FIGS. In FIG. 9, the surface of the silicon substrate 11 has L
An impurity diffusion layer 13 is formed adjacent to the OCOS film 12. On the silicon substrate 11, SiO 2 , PS
A first interlayer insulating film 14 of G, BPSG or the like is formed.
Is formed in the contact hole 15, a first plug 16 formed by stacking a barrier metal layer 16b on a tungsten layer 16a is formed. A second interlayer insulating film 17 is formed on the first plug 16 and the first interlayer insulating film 14, and the first plug 16
Is formed.
【0028】その凹部18の底面と側面には、第一のS
RO膜19が形成されている。さらに、第一のSRO膜
19の上と第二の層間絶縁膜17の上には、BST20
と第二のSRO膜21が順に形成され、それらの膜は所
望の形状にパターニングされている。第二のSRO膜2
1の上には、TEOSガスを用いて膜厚50nm以下の
SiO2膜22aが形成され、そのSiO2膜22aの上にはシ
ランとアンモニアを用いてSiN 膜22bが形成されてい
る。そのSiO2膜22aとSiN 膜22bの二層構造は第二
のSRO膜21の保護膜22として機能し、その保護膜
22は、フォトリソグラフィー法によって微細にパター
ニングすることが容易である。The first S
An RO film 19 is formed. Further, a BST 20 is formed on the first SRO film 19 and the second interlayer insulating film 17.
And a second SRO film 21 are sequentially formed, and these films are patterned into a desired shape. Second SRO film 2
On top of No. 1, a film having a thickness of 50 nm or less was formed using TEOS gas.
An SiO 2 film 22a is formed, and a SiN film 22b is formed on the SiO 2 film 22a using silane and ammonia. The two-layer structure of the SiO 2 film 22a and the SiN film 22b functions as a protective film 22 of the second SRO film 21, and the protective film 22 can be easily finely patterned by photolithography.
【0029】第一のSRO膜19はキャパシタの下部電
極として、BST膜20はキャパシタの誘電体膜とし
て、第二のSRO膜21はキャパシタの上部電極として
使用される。さらに、保護膜22の上には第三の層間絶
縁膜23が形成されている。第三の層間絶縁膜23と保
護膜22は連続的にパターニングされて、第二のSRO
膜21の一部の上に開口24が形成されている。The first SRO film 19 is used as a capacitor lower electrode, the BST film 20 is used as a capacitor dielectric film, and the second SRO film 21 is used as a capacitor upper electrode. Further, a third interlayer insulating film 23 is formed on the protective film 22. The third interlayer insulating film 23 and the protective film 22 are continuously patterned to form the second SRO
An opening 24 is formed on a part of the film 21.
【0030】その開口24内には、窒化チタン膜25a
とタングステン25bよりなる第二のプラグ25が埋め
込まれている。その窒化チタン膜25aは、20nmよ
りも薄く、且つ400℃よりも低い基板温度で形成され
ることが好ましい。以上のような構造を有する半導体装
置を水素含有雰囲気で加熱しても、SiN /SiO2保護膜2
2により第二のSRO膜21の膜質の劣化が防止され
る。なお、第二のプラグ25と第二のSRO膜22の間
の窒化チタン膜24は膜厚20nmより薄く、400℃
以下で形成されることが好ましい。In the opening 24, a titanium nitride film 25a is formed.
And a second plug 25 made of tungsten 25b. It is preferable that the titanium nitride film 25a is formed at a substrate temperature thinner than 20 nm and lower than 400 ° C. Even if the semiconductor device having the above structure is heated in a hydrogen-containing atmosphere, the SiN / SiO 2 protective film 2
2, the deterioration of the film quality of the second SRO film 21 is prevented. The titanium nitride film 24 between the second plug 25 and the second SRO film 22 is thinner than 20 nm and
It is preferably formed as follows.
【0031】図10は、第二のSRO膜21上の保護膜
として、 SiN/SiO2膜の代わりに窒化チタン膜を用いた
例を示している。図10において、図9と同じ符号は同
じ要素を示している。図10において、第二のSRO膜
21の上には窒化チタンよりなる保護膜30が形成され
ている。400℃よりも低い基板温度条件でスパッタに
より窒化チタン保護膜30が20nmよりも薄い例えば
15nm以下の厚さに形成されている。そして、その保
護膜30は、フォトリソグラフィー法により所望の形状
にパターニングが容易であり、そのパターニングの後に
窒化チタン保護膜30と第二の層間絶縁膜17は第三の
層間絶縁膜23に覆われる。FIG. 10 shows an example in which a titanium nitride film is used as a protective film on the second SRO film 21 instead of the SiN / SiO 2 film. 10, the same reference numerals as in FIG. 9 indicate the same elements. In FIG. 10, a protective film 30 made of titanium nitride is formed on the second SRO film 21. The titanium nitride protective film 30 is formed to a thickness of less than 20 nm, for example, 15 nm or less by sputtering under a substrate temperature condition lower than 400 ° C. The protective film 30 is easily patterned into a desired shape by a photolithography method, and after the patterning, the titanium nitride protective film 30 and the second interlayer insulating film 17 are covered with a third interlayer insulating film 23. .
【0032】第三の層間絶縁膜23には、窒化チタン保
護膜30の一部に達する開口24aが形成され、その開
口24a内には窒化チタン25aとタングステン膜25
bよりなる第二のプラグ25が埋め込まれる。そのよう
な構造を有する半導体装置を水素雰囲気で加熱しても、
窒化チタン保護膜30によって第二のSRO膜21の膜
質の劣化が防止される。An opening 24a reaching a part of the titanium nitride protective film 30 is formed in the third interlayer insulating film 23, and the titanium nitride 25a and the tungsten film 25 are formed in the opening 24a.
The second plug 25 made of b is embedded. Even if a semiconductor device having such a structure is heated in a hydrogen atmosphere,
The titanium nitride protective film 30 prevents the quality of the second SRO film 21 from deteriorating.
【0033】なお、キャパシタの上部電極としてSRO
膜に限定されるものではなく、その他のルテニウムを含
む導電膜を用いてもよい。また、上部電極に接続される
プラグとして、アルミニウムを含む膜を用いてもよい。
キャパシタの誘電体膜として、BST((Ba x Sr1-x )T
iO3 、但し0≦x≦1)の代わりにSTO(SrTiO3)、
酸化タンタル(Ta2O5 )、PZT(Pb(Zr x Ti 1-x )
O3 、但し0≦x≦1) 、PLZT((Pb y La1-y )(Zr
x Ti1-x )O3 、但し0≦x≦1、0≦y≦1) を用いて
もよい。また、保護膜として、上記した材料の他にアル
ミナ(Al2O3 )を用いてもよい。 {付 記} (1)半導体基板上方に形成されたルテニウムを含む導
電膜の上に、下から順に酸化シリコンと窒化シリコンを
積層してなる二層構造膜と窒化チタン膜の少なくとも1
つを保護膜として形成する工程と、前記保護膜の形成後
に前記半導体基板を還元雰囲気中で加熱する工程とを有
する半導体装置の製造方法。 (2)前記二層構造膜を構成する前記酸化シリコンは5
0nmよりも薄いことを特徴とする(1)に記載の半導
体装置の製造方法。 (3)前記窒化チタン膜は、400℃よりも低い基板温
度で20nmより薄く形成されることを特徴とする
(1)に記載の半導体装置の製造方法。Note that SRO is used as the upper electrode of the capacitor.
It is not limited to a film and contains other ruthenium.
Alternatively, a conductive film may be used. Also connected to the upper electrode
As the plug, a film containing aluminum may be used.
As a dielectric film of a capacitor, BST ((BaxSr1-x) T
iOThreeHowever, instead of 0 ≦ x ≦ 1, STO (SrTiOThree),
Tantalum oxide (TaTwoOFive), PZT (Pb (ZrxTi 1-x)
OThreeWhere 0 ≦ x ≦ 1), PLZT ((PbyLa1-y) (Zr
xTi1-x) OThreeWhere 0 ≦ x ≦ 1, 0 ≦ y ≦ 1)
Is also good. In addition, other than the above-mentioned materials,
Mina (AlTwoOThree) May be used. << Supplementary Note >> (1) Conduction containing ruthenium formed above the semiconductor substrate
Silicon oxide and silicon nitride in order from the bottom
At least one of a laminated two-layer structure film and a titanium nitride film
Forming one as a protective film, and after forming the protective film
Heating the semiconductor substrate in a reducing atmosphere.
Semiconductor device manufacturing method. (2) The silicon oxide constituting the two-layer structure film is 5
Semiconductor according to (1), characterized by being thinner than 0 nm.
Manufacturing method of body device. (3) The titanium nitride film has a substrate temperature lower than 400 ° C.
Characterized by being formed thinner than 20 nm in degree
The method for manufacturing a semiconductor device according to (1).
【0034】[0034]
【発明の効果】以上述べたように本発明によれば、SR
O膜のようなルテニウムを含む導電膜上に形成される保
護膜として、酸化シリコンと窒化シリコンの二層構造膜
と窒化チタン膜のうち少なくとも1つを選択したので、
そのような保護膜によれば、基板を還元雰囲気中でアニ
ールする際に、ルテニウムを含む導電膜の劣化を防止で
き、しかも、その導電膜とその上に形成されるプラグと
のコンタクト抵抗の上昇を抑制し、保護膜剥がれを防止
することができる。As described above, according to the present invention, the SR
As a protective film formed on a conductive film containing ruthenium such as an O film, at least one of a two-layer structure film of silicon oxide and silicon nitride and a titanium nitride film was selected.
According to such a protective film, when the substrate is annealed in a reducing atmosphere, the deterioration of the conductive film containing ruthenium can be prevented, and the contact resistance between the conductive film and the plug formed thereon can be increased. Can be suppressed, and peeling of the protective film can be prevented.
【図1】従来の半導体装置の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a conventional semiconductor device.
【図2】半導体装置に使用されるSRO膜のアニーリン
グの前と後の状態を示すSEM写真である。FIG. 2 is SEM photographs showing states before and after annealing of an SRO film used in a semiconductor device.
【図3】半導体装置に使用されるSRO膜を窒化シリコ
ン膜で覆った状態を示すSEM写真である。FIG. 3 is an SEM photograph showing a state in which an SRO film used for a semiconductor device is covered with a silicon nitride film.
【図4】半導体装置に使用されるSRO膜を酸化シリコ
ン膜で覆った状態を示すSEM写真である。FIG. 4 is an SEM photograph showing a state where an SRO film used for a semiconductor device is covered with a silicon oxide film.
【図5】本発明の実施形態に係る半導体装置のSiN /Si
O2/SRO構造をアニーリングする前と後の状態を示す
SEM写真である。FIG. 5 shows the SiN / Si of the semiconductor device according to the embodiment of the present invention.
It is a SEM photograph which shows the state before and after annealing the O2 / SRO structure.
【図6】半導体装置に使用されるSRO膜を膜厚20n
mのSiN 膜で覆い、アニーリングする前の状態を示すS
EM写真である。FIG. 6 shows an SRO film having a thickness of 20 n used for a semiconductor device.
S before covering with SiN film
It is an EM photograph.
【図7】半導体装置に使用されるSRO膜を膜厚20n
mのSiN 膜で覆い、アニーリングした後の状態を示すS
EM写真である。FIG. 7 shows an SRO film used for a semiconductor device having a film thickness of 20 n.
m after being covered with a SiN film and annealing.
It is an EM photograph.
【図8】本発明の実施形態に係る半導体装置における窒
化チタン/SROをアニーリングした後の状態を示すS
EM写真である。FIG. 8 shows S after annealing titanium nitride / SRO in the semiconductor device according to the embodiment of the present invention.
It is an EM photograph.
【図9】本発明の実施形態に係る第1の半導体装置を示
す断面図である。FIG. 9 is a cross-sectional view illustrating a first semiconductor device according to an embodiment of the present invention.
【図10】本発明の実施形態に係る第2の半導体装置を
示す断面図である。FIG. 10 is a sectional view showing a second semiconductor device according to the embodiment of the present invention.
11…シリコン基板(半導体基板)、12…LOCO
S、13…不純物拡散層、14、17、23…層間絶縁
膜、15…コンタクトホール、16…第一のプラグ、1
8…凹部、19…第一のSRO膜、20…BST膜、2
1…第二のSRO膜、22…保護膜、22a…酸化シリ
コン膜、22b…窒化シリコン膜、24…開口、25…
プラグ、25a…窒化チタン膜、25b…タングステン
膜、30…保護膜。11: silicon substrate (semiconductor substrate), 12: LOCO
S, 13: impurity diffusion layer, 14, 17, 23: interlayer insulating film, 15: contact hole, 16: first plug, 1
8: recess, 19: first SRO film, 20: BST film, 2
DESCRIPTION OF SYMBOLS 1 ... 2nd SRO film, 22 ... protective film, 22a ... silicon oxide film, 22b ... silicon nitride film, 24 ... opening, 25 ...
Plug, 25a: titanium nitride film, 25b: tungsten film, 30: protective film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 江口 和弘 神奈川県横浜市磯子区新杉田町8番地 株 式会社東芝横浜事業所内 (72)発明者 稗田 克彦 神奈川県横浜市磯子区新杉田町8番地 株 式会社東芝横浜事業所内 Fターム(参考) 5F083 FR01 GA21 JA06 JA14 JA15 JA36 JA39 JA40 JA44 MA06 MA17 MA18 NA08 PR21 PR33 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuhiro Eguchi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Katsuhiko Hieda 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term in Toshiba Yokohama Office (reference) 5F083 FR01 GA21 JA06 JA14 JA15 JA36 JA39 JA40 JA44 MA06 MA17 MA18 NA08 PR21 PR33
Claims (7)
含む導電膜の上に、下から順に酸化シリコンと窒化シリ
コンを積層してなる二層構造膜と窒化チタン膜の少なく
とも1つを保護膜として形成する工程と、 前記保護膜の形成後に前記半導体基板を還元雰囲気中で
加熱する工程とを有する半導体装置の製造方法。An at least one of a two-layer structure film and a titanium nitride film, in which silicon oxide and silicon nitride are sequentially stacked from above on a ruthenium-containing conductive film formed above a semiconductor substrate, is used as a protective film. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of heating the semiconductor substrate in a reducing atmosphere after forming the protective film.
に、前記半導体基板の上に第一の絶縁膜を形成し、該第
一の絶縁膜内に第一のプラグを埋め込み、該第一のプラ
グに接続されるキャパシタ下部電極を前記第一の絶縁膜
上に形成し、キャパシタ下部電極の上にキャパシタ誘電
体膜を形成した後に、該キャパシタ誘電体膜の上に前記
ルテニウムを含む導電膜をキャパシタ上部電極として形
成し、 さらに、前記保護膜の上に第二の絶縁膜を形成し、該第
二の絶縁膜に、前記ルテニウムを含む導電膜に電気的に
接続される第二のプラグを埋め込むことを特徴とする請
求項1に記載の半導体装置の製造方法。2. A method according to claim 1, further comprising: forming a first insulating film on the semiconductor substrate before forming the ruthenium-containing conductive film; embedding a first plug in the first insulating film; Forming a capacitor lower electrode connected to the plug on the first insulating film, forming a capacitor dielectric film on the capacitor lower electrode, and then forming the ruthenium-containing conductive film on the capacitor dielectric film Is formed as a capacitor upper electrode. Further, a second insulating film is formed on the protective film, and a second plug electrically connected to the ruthenium-containing conductive film is formed on the second insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
O、Ta2O5 、PZT又はPLZTのいずれかであること
を特徴とする請求項2に記載の半導体装置の製造方法。3. A capacitor dielectric film according to claim 1, wherein
3. The method according to claim 2, wherein the semiconductor device is one of O, Ta 2 O 5 , PZT, and PLZT.
む導電膜の上に、窒化チタン膜を介して形成されたタン
グステン又はアルミニウムを含む膜から構成されること
を特徴とする請求項2に記載の半導体装置の製造方法。4. The semiconductor device according to claim 2, wherein the second plug is formed of a film containing tungsten or aluminum formed on the conductive film containing ruthenium via a titanium nitride film. The manufacturing method of the semiconductor device described in the above.
含む導電膜と、 前記ルテニウムを含む導電膜の上に形成され、かつ、下
から順に酸化シリコンと窒化シリコンを積層してなる二
層構造膜と窒化チタン膜の少なくとも1つからなる保護
膜とを有することを特徴とする半導体装置。5. A two-layer structure film formed on a conductive film containing ruthenium formed above a semiconductor substrate, and formed on the conductive film containing ruthenium and laminated with silicon oxide and silicon nitride in order from the bottom. And a protective film made of at least one of a titanium nitride film.
ンは50nmよりも薄いことを特徴とする請求項5に記
載の半導体装置。6. The semiconductor device according to claim 5, wherein said silicon oxide forming said two-layer structure film is thinner than 50 nm.
とを特徴とする請求項5又は請求項6に記載の半導体装
置。7. The semiconductor device according to claim 5, wherein said titanium nitride film is thinner than 20 nm.
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Cited By (1)
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KR100877093B1 (en) * | 2002-06-21 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor of semiconductor memory device |
Citations (3)
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JPH07273297A (en) * | 1994-03-28 | 1995-10-20 | Olympus Optical Co Ltd | Ferroelectric substance memory |
JPH1126716A (en) * | 1997-06-30 | 1999-01-29 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JP2000022109A (en) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
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2000
- 2000-03-24 JP JP2000083827A patent/JP4583544B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273297A (en) * | 1994-03-28 | 1995-10-20 | Olympus Optical Co Ltd | Ferroelectric substance memory |
JPH1126716A (en) * | 1997-06-30 | 1999-01-29 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JP2000022109A (en) * | 1998-06-30 | 2000-01-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100877093B1 (en) * | 2002-06-21 | 2009-01-07 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor of semiconductor memory device |
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