JP2001274193A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2001274193A JP2001274193A JP2000085844A JP2000085844A JP2001274193A JP 2001274193 A JP2001274193 A JP 2001274193A JP 2000085844 A JP2000085844 A JP 2000085844A JP 2000085844 A JP2000085844 A JP 2000085844A JP 2001274193 A JP2001274193 A JP 2001274193A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- film
- electrode
- substrate
- anisotropic conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は異方性導電接着剤を
用いて回路基板に接続する半導体装置およびその製造方
法に関する。The present invention relates to a semiconductor device connected to a circuit board using an anisotropic conductive adhesive and a method for manufacturing the same.
【0002】[0002]
【従来の技術】半導体装置を直接基板に接続するベアチ
ップ実装は年々小型化する電子機器にとって理想的な実
装方法である。2. Description of the Related Art Bare chip mounting, in which a semiconductor device is directly connected to a substrate, is an ideal mounting method for electronic equipment that is becoming smaller year by year.
【0003】ストレートウォール形状の突起電極を有す
る半導体装置と液晶表示装置とを異方性導電接着剤で接
続する実装方法を例に、図面を用いて説明する。図9か
ら図11は半導体装置の構造を示す断面図、図12は、
半導体装置と回路基板とを接続した実装構造を示す断面
図である。An example of a mounting method for connecting a semiconductor device having a straight wall-shaped projection electrode and a liquid crystal display device with an anisotropic conductive adhesive will be described with reference to the drawings. 9 to 11 are sectional views showing the structure of the semiconductor device, and FIG.
FIG. 3 is a cross-sectional view illustrating a mounting structure in which a semiconductor device and a circuit board are connected.
【0004】〔半導体装置と回路基板の実装構造説明:
図12〕図12に示すように、半導体装置10はシリコ
ン基板11の素子形成面に設けた接続電極パッド12を
配置する。半導体装置10の接続電極パッド12が開口
するように保護膜13を設ける。[Description of mounting structure of semiconductor device and circuit board:
[FIG. 12] As shown in FIG. 12, in a semiconductor device 10, connection electrode pads 12 provided on an element formation surface of a silicon substrate 11 are arranged. The protective film 13 is provided so that the connection electrode pad 12 of the semiconductor device 10 is opened.
【0005】接続電極パッド12の上に共通電極膜14
を、さらに共通電極膜14の上に突起電極17を形成す
る。The common electrode film 14 is formed on the connection electrode pad 12.
Then, a protruding electrode 17 is formed on the common electrode film 14.
【0006】またさらに、半導体装置10の突起電極1
7と基板22の基板電極23とを異方性導電接着剤31
の導電粒子31aで接続する。Further, the bump electrode 1 of the semiconductor device 10
7 and the substrate electrode 23 of the substrate 22 are anisotropic conductive adhesive 31
Are connected by conductive particles 31a.
【0007】〔半導体装置の製造方法説明:図9から図
12〕つぎに半導体装置の製造方法を説明する。図9に
示すように、半導体装置10はシリコン基板11の素子
形成表面にアルミニウムからなる接続電極パッド12を
厚さ1μm形成する。[Description of Method of Manufacturing Semiconductor Device: FIGS. 9 to 12] Next, a method of manufacturing a semiconductor device will be described. As shown in FIG. 9, in the semiconductor device 10, a connection electrode pad 12 made of aluminum is formed to a thickness of 1 μm on the element formation surface of a silicon substrate 11.
【0008】図10に示すように、接続電極パッド12
を含む半導体装置10の全面に、半導体素子の保護を目
的とする保護膜13を形成する。この保護膜13は一般
的に燐を含有したシリコン酸化膜,窒化シリコン膜等の
無機質膜用いて、形成する膜厚は1μmである。[0010] As shown in FIG.
A protective film 13 for protecting a semiconductor element is formed on the entire surface of the semiconductor device 10 including. The protective film 13 is generally made of an inorganic film such as a silicon oxide film or a silicon nitride film containing phosphorus, and has a thickness of 1 μm.
【0009】その後、フォトソリグラフィーとエッチン
グにより接続電極パッド12が露出するように保護膜1
3を開口する。Then, the protective film 1 is exposed by photolithography and etching so that the connection electrode pad 12 is exposed.
3 is opened.
【0010】共通電極膜14を半導体装置10の全面に
アルミニウムを1μm、クロムを0.01μm、銅を1
μmの厚さで順次金属多層膜をスパッタリング法や真空
蒸着法等の方法で形成する。The common electrode film 14 is formed on the entire surface of the semiconductor device 10 by aluminum of 1 μm, chromium of 0.01 μm, and copper of 1 μm.
A metal multilayer film having a thickness of μm is sequentially formed by a method such as a sputtering method or a vacuum evaporation method.
【0011】つぎに半導体装置10の全面に、厚膜液状
感光性レジストからなるメッキレジスト16を厚さ20
μm形成する。その後フォトリソグラフィーにより、接
続電極パッド12の上の共通電極膜14の部分のメッキ
レジスト16に開口部を設ける。Next, a plating resist 16 made of a thick liquid photosensitive resist is coated on the entire surface of the semiconductor device 10 to a thickness of 20 mm.
μm is formed. Thereafter, an opening is provided in the plating resist 16 in the portion of the common electrode film 14 on the connection electrode pad 12 by photolithography.
【0012】さらに金からなる突起電極17を電解メッ
キにて15μmの厚さで形成する。Further, a protruding electrode 17 made of gold is formed to a thickness of 15 μm by electrolytic plating.
【0013】図11に示すように、不用になったメッキ
レジスト16を除去する。さらに突起電極17の付け根
部分以外の共通電極膜14を除去する。As shown in FIG. 11, the unnecessary plating resist 16 is removed. Further, the common electrode film 14 other than the base of the protruding electrode 17 is removed.
【0014】〔半導体装置と液晶表示装置の基板との接
続方法説明:図12〕つぎに半導体装置と液晶表示装置
の基板との接続方法を説明する。図12に示すように、
ガラスからなる基板22に基板電極23となる酸化イン
ジウムすずを0.2μm形成する。その後フォトリソグ
ラフィーにより、半導体装置10の突起電極17に対応
するようにパターニングする。[Explanation of Method of Connecting Semiconductor Device to Substrate of Liquid Crystal Display Device: FIG. 12] Next, a method of connecting the semiconductor device to the substrate of the liquid crystal display device will be described. As shown in FIG.
Indium tin oxide serving as a substrate electrode 23 is formed to a thickness of 0.2 μm on a substrate 22 made of glass. Thereafter, patterning is performed by photolithography so as to correspond to the protruding electrodes 17 of the semiconductor device 10.
【0015】基板22に異方性導電接着剤31を配置す
る。異方性導電接着剤31はエポキシ樹脂からなる絶縁
性樹脂に導電粒子31aを混ぜたもので厚さ25μmの
シート状のものである。導電粒子31aはプラスチック
ビーズの表面にニッケルさらに金の2層めっきした外形
5μmものを用いている。An anisotropic conductive adhesive 31 is disposed on a substrate 22. The anisotropic conductive adhesive 31 is obtained by mixing conductive particles 31a with an insulating resin made of an epoxy resin, and is a sheet having a thickness of 25 μm. The conductive particles 31a have a particle size of 5 μm, in which two layers of nickel and gold are plated on the surface of plastic beads.
【0016】つぎに半導体装置10の突起電極17と基
板22の基板電極23とを位置会わせした後、加熱加圧
処理を行い異方性導電接着剤31を硬化する。Next, after the protruding electrodes 17 of the semiconductor device 10 are aligned with the substrate electrodes 23 of the substrate 22, a heating and pressurizing process is performed to cure the anisotropic conductive adhesive 31.
【0017】加熱加圧条件は、温度が170℃〜200
℃、加圧は400Kg/cm2である。The heating and pressing conditions are as follows: a temperature of 170 ° C. to 200 ° C.
C., pressure is 400 Kg / cm 2 .
【0018】異方性導電接着剤31を加熱加圧処理する
と、異方性導電接着剤31が流動し半導体装置10の突
起電極17と基板22の基板電極23との間に異方性導
電接着剤31の導電粒子31aが介在して電気的な接続
が得られる。When the anisotropic conductive adhesive 31 is heated and pressurized, the anisotropic conductive adhesive 31 flows, and the anisotropic conductive adhesive 31 flows between the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22. Electrical connection is obtained through the conductive particles 31a of the agent 31.
【0019】[0019]
【発明が解決しようとする課題】このように説明した従
来の技術では、異方性導電接着剤31を硬化させるため
加熱加圧処理によって、半導体装置10と基板22との
隙間すなわち保護膜13の表面と基板22の表面との距
離は突起電極17の高さと異方性導電接着剤31の導電
粒子31aの外形によって決まり約20μmになる。In the prior art described above, the gap between the semiconductor device 10 and the substrate 22, that is, the protective film 13 is hardened by heating and pressing to cure the anisotropic conductive adhesive 31. The distance between the surface and the surface of the substrate 22 is determined by the height of the protruding electrode 17 and the outer shape of the conductive particles 31a of the anisotropic conductive adhesive 31, and is about 20 μm.
【0020】加熱加圧処理を行なう前の異方性導電接着
剤31の厚さは25μmなので、5μmの厚さ分と突起
電極17の分の異方性導電接着剤31が半導体装置10
と基板22との隙間から流れ出す。Since the thickness of the anisotropic conductive adhesive 31 before the heating and pressurizing treatment is 25 μm, the anisotropic conductive adhesive 31 corresponding to the thickness of 5 μm and the projection electrode 17 is applied to the semiconductor device 10.
Flows out of the gap between the substrate and the substrate 22.
【0021】この異方性導電接着剤31の流動は半導体
装置10の突起電極17と基板22の基板電極23との
間に捕獲する異方性導電接着剤31の導電粒子31aの
数に影響を与える。The flow of the anisotropic conductive adhesive 31 affects the number of conductive particles 31 a of the anisotropic conductive adhesive 31 captured between the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22. give.
【0022】異方性導電接着剤31の流動が速いと、捕
獲する異方性導電接着剤31の導電粒子31aの数が少
なくなる。When the flow of the anisotropic conductive adhesive 31 is fast, the number of the conductive particles 31a of the anisotropic conductive adhesive 31 to be captured decreases.
【0023】図8に示すように、突起電極17は半導体
装置10の長辺の二辺に配置しているため、この突起電
極17によって異方性導電接着剤31の流動は妨げら
れ、半導体装置10の短辺方向へ流動が速くなる。As shown in FIG. 8, since the protruding electrodes 17 are arranged on two long sides of the semiconductor device 10, the flow of the anisotropic conductive adhesive 31 is hindered by the 10, the flow becomes faster in the short side direction.
【0024】半導体装置10の長辺にある多数の突起電
極17は、配置された位置によって半導体装置10の突
起電極17と基板22の基板電極23との間に捕獲する
異方性導電接着剤31の導電粒子31aの数はばらつ
き、半導体装置10の短辺に近い部分の端子では、半導
体装置10の突起電極15と基板22の基板電極23と
の間に捕獲する異方性導電接着剤31の導電粒子31a
の数は極端に減少し半分以下になる。A large number of the protruding electrodes 17 on the long side of the semiconductor device 10 form an anisotropic conductive adhesive 31 that is trapped between the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22 depending on the arrangement position. The number of the conductive particles 31a of the semiconductor device 10 fluctuates, and the terminal of the portion near the short side of the semiconductor device 10 has the anisotropic conductive adhesive 31 trapped between the protruding electrode 15 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22. Conductive particles 31a
Is extremely reduced to less than half.
【0025】接続抵抗値1Ω以下を必要とする場合、1
端子あたり10個の異方性導電接着剤31の導電粒子3
1aが必要となるので、半導体装置10の短辺に近い部
分の端子では2倍以上の接続面積にしなければならな
い。When the connection resistance value of 1Ω or less is required, 1
Conductive particles 3 of ten anisotropic conductive adhesives 31 per terminal
Since 1a is required, the connection area of the terminal near the short side of the semiconductor device 10 must be twice or more.
【0026】そのために従来の技術では、狭接続面積に
よる実装である微細接続を低抵抗かつ高信頼性に実現さ
せるには非常に困難である。For this reason, it is very difficult with the conventional technology to realize fine connection, which is mounting with a small connection area, with low resistance and high reliability.
【0027】異方性導電接着剤31の流動を抑える方法
として、加熱加圧処理を行う前の異方性導電接着剤31
の厚さを半導体装置10と基板22との隙間である20
μmにすることが考えられる。As a method for suppressing the flow of the anisotropic conductive adhesive 31, the anisotropic conductive adhesive 31 before the heating and pressing treatment is performed.
The thickness of the semiconductor device 10 and the substrate 22
It can be considered to be μm.
【0028】しかしながら、この手段によって異方性導
電接着剤31の流動を抑えることが可能になるが、半導
体装置10と基板22との間に気泡を抱き込み異方性導
電接着剤31が硬化する。However, it is possible to suppress the flow of the anisotropic conductive adhesive 31 by this means, but the air bubbles are trapped between the semiconductor device 10 and the substrate 22 so that the anisotropic conductive adhesive 31 is cured. .
【0029】この気泡は耐信頼性試験に悪影響を与え
る。温度サイクル試験では、気泡に最も近い端子に歪み
が集中して不良を誘発する。また、高温試験での異方性
導電接着剤の剥離、耐湿性試験での吸水など不良の要因
となる。These bubbles adversely affect the reliability test. In the temperature cycle test, strain concentrates on the terminal closest to the bubble and induces a failure. In addition, it causes defects such as peeling of the anisotropic conductive adhesive in a high temperature test and water absorption in a moisture resistance test.
【0030】このため、半導体装置10と基板22との
隙間より若干厚い25μmの異方性導電接着剤31を用
いて実装するのが一般的である。For this reason, it is common to mount the semiconductor device 10 using a 25 μm anisotropic conductive adhesive 31 which is slightly thicker than the gap between the semiconductor device 10 and the substrate 22.
【0031】〔発明の目的〕本発明の目的は上記課題を
解決し、半導体装置と基板との加圧加熱接続時に発生す
る異方性導電接着剤の流動を制御して、半導体装置の突
起電極と基板の基板との間に捕獲する異方性導電接着剤
の導電粒子の数を確保し、このことによって低抵抗であ
るとともに高信頼性のある微細接続が可能な半導体装置
およびその製造方法を提供することが本発明の目的であ
る。[Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to control the flow of an anisotropic conductive adhesive generated at the time of pressurizing and heating connection between a semiconductor device and a substrate to thereby form a projection electrode of a semiconductor device. A semiconductor device capable of ensuring the number of conductive particles of an anisotropic conductive adhesive to be captured between a substrate and a substrate of a substrate, thereby providing a low-resistance and highly reliable fine connection and a method of manufacturing the same. It is an object of the present invention to provide.
【0032】[0032]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置およびその製造方法において
は、下記記載の手段を採用する。In order to solve the above-mentioned problems, the following means are employed in a semiconductor device and a method of manufacturing the same according to the present invention.
【0033】本発明の半導体装置においては、接続電極
パッドの上に開口部を有する保護膜と、半導体装置の外
周部において接続領域以外部分の保護膜の上に設ける流
動制御膜と、接続電極パッドの上に設ける共通電極膜
と、共通電極膜の上に設ける突起電極とを有する半導体
装置を特徴とする。In the semiconductor device of the present invention, a protection film having an opening on the connection electrode pad, a flow control film provided on the protection film in a portion other than the connection region on the outer periphery of the semiconductor device, and a connection electrode pad A semiconductor device having a common electrode film provided on the common electrode film and a projecting electrode provided on the common electrode film.
【0034】本発明の半導体装置の製造方法において
は、接続電極パッドを有する半導体装置に保護膜を形成
し、接続電極パッドが開口するように保護膜をパターン
ニングする工程と、流動制御膜を半導体装置に形成する
工程と、流動制御膜を半導体装置の外周部において接続
領域以外の部分に配置するようにパターンニングする工
程と、共通電極膜を半導体装置に形成する工程と、メッ
キレジストを半導体装置に形成する工程と、メッキレジ
ストを突起電極形成領域が開口するようにパターンニン
グする工程と、メッキレジスト開口部にメッキにより突
起電極を形成する工程と、メッキレジストを除去する工
程と、突起電極の付け根以外の部分の共通電極膜を除去
する工程とを有することを特徴とする。In the method of manufacturing a semiconductor device according to the present invention, a step of forming a protective film on a semiconductor device having connection electrode pads and patterning the protective film so that the connection electrode pads are opened; Forming a flow control film on an outer peripheral portion of the semiconductor device in a portion other than a connection region, forming a common electrode film on the semiconductor device, and forming a plating resist on the semiconductor device. Forming a plating resist, patterning the plating resist so that the protruding electrode formation region is opened, forming a protruding electrode by plating the plating resist opening, removing the plating resist, Removing the common electrode film other than at the base.
【0035】〔作用〕本発明による半導体装置の実装構
造は、半導体装置の短辺に配置した流動制御膜によって
異方性導電接着剤の流動をコントロールして、半導体装
置のどの端子の場所でも同じ流動になるようにした。[Operation] In the mounting structure of the semiconductor device according to the present invention, the flow of the anisotropic conductive adhesive is controlled by the flow control film disposed on the short side of the semiconductor device so that the same position is applied to any terminal of the semiconductor device. It was made to flow.
【0036】どの半導体装置の端子でも導体装置の突起
電極と基板の基板との間に捕獲する異方性導電接着剤の
導電粒子を均一に充分確保できる。In any of the terminals of the semiconductor device, the conductive particles of the anisotropic conductive adhesive captured between the protruding electrode of the conductor device and the substrate can be sufficiently ensured uniformly.
【0037】このことにより本発明においては、接続面
積を最小にすることができ、低抵抗かつ高信頼性な微細
接続を提供することが可能である。As a result, in the present invention, the connection area can be minimized, and a low-resistance and highly reliable fine connection can be provided.
【0038】[0038]
【発明の実施の形態】以下、図面を用いて本発明を実施
するための最良の形態における半導体装置の実装構造
を、半導体装置と液晶表示装置との実装を例に説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The mounting structure of a semiconductor device according to the best mode for carrying out the present invention will be described below with reference to the drawings, taking the mounting of a semiconductor device and a liquid crystal display device as an example.
【0039】図1から図6は本発明の半導体装置の構造
および製造方法を示す断面図、図2および図7は本発明
の半導体装置の構造および製造方法を示す平面図であ
る。FIGS. 1 to 6 are sectional views showing the structure and manufacturing method of the semiconductor device of the present invention, and FIGS. 2 and 7 are plan views showing the structure and manufacturing method of the semiconductor device of the present invention.
【0040】〔半導体装置の実装構造説明:図1〕本発
明の実施形態における半導体装置の構造および半導体装
置と液晶表示装置との実装構造を説明する。[Description of Mounting Structure of Semiconductor Device: FIG. 1] The structure of the semiconductor device according to the embodiment of the present invention and the mounting structure of the semiconductor device and the liquid crystal display device will be described.
【0041】図1に示すように、半導体装置10の突起
電極17と基板22の基板電極23とを異方性導電接着
剤31の導電粒子31aで接続する。As shown in FIG. 1, the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22 are connected by conductive particles 31 a of an anisotropic conductive adhesive 31.
【0042】半導体装置10はシリコン基板11の素子
形成面に設けた接続電極パッド12を配置する。半導体
装置10の接続電極パッド12が開口するように保護膜
13を設ける。半導体装置10の外周部で接続領域以外
の部分の保護膜13の上に流動制御膜15を設ける。接
続電極パッド12の上に共通電極膜14を、さらに共通
電極膜14の上に突起電極17を形成する。In the semiconductor device 10, connection electrode pads 12 provided on an element formation surface of a silicon substrate 11 are arranged. The protective film 13 is provided so that the connection electrode pad 12 of the semiconductor device 10 is opened. The flow control film 15 is provided on the protective film 13 in a portion other than the connection region on the outer peripheral portion of the semiconductor device 10. The common electrode film 14 is formed on the connection electrode pad 12, and the protruding electrodes 17 are formed on the common electrode film 14.
【0043】〔半導体装置の構造説明:図1から図3〕
つぎに半導体装置の構造を説明する。図3に示すよう
に、半導体装置10はシリコン基板11の素子形成面に
設けた接続電極パッド12を配置する。[Structural Description of Semiconductor Device: FIGS. 1 to 3]
Next, the structure of the semiconductor device will be described. As shown in FIG. 3, the semiconductor device 10 has a connection electrode pad 12 provided on the element formation surface of a silicon substrate 11.
【0044】図2に示すように、接続電極パッド12は
外部からの信号を接続する入力信号端子と液晶表示装置
の表示素子に接続する出力信号端子がある。液晶表示装
置の引き回し配線の抵抗値の問題で、半導体装置の長辺
の二辺を用いてレイアウトするのが一般的である。半導
体装置11の接続電極パッド12が開口するように保護
膜13を設ける。As shown in FIG. 2, the connection electrode pad 12 has an input signal terminal for connecting an external signal and an output signal terminal for connecting to a display element of a liquid crystal display device. Due to the problem of the resistance value of the routing wiring of the liquid crystal display device, it is general to lay out using two long sides of the semiconductor device. The protective film 13 is provided so that the connection electrode pad 12 of the semiconductor device 11 is opened.
【0045】感光性ポリイミドなどの有機材料からなる
流動制御膜15を半導体装置10の短辺の二辺の外周部
の保護膜13の上に配置する。The flow control film 15 made of an organic material such as a photosensitive polyimide is disposed on the protective film 13 on the outer periphery of two short sides of the semiconductor device 10.
【0046】図1に示すように、接続電極パッド12の
上に共通電極膜14を、さらに共通電極膜14の上に突
起電極17を形成する。突起電極17の頂部が流動制御
膜15の頂部より高さが若干高くなるように構成する。As shown in FIG. 1, a common electrode film 14 is formed on the connection electrode pad 12, and a projection electrode 17 is formed on the common electrode film 14. The top of the protruding electrode 17 is configured to be slightly higher than the top of the flow control film 15.
【0047】半導体装置10の突起電極17と基板22
の基板電極23とを異方性導電接着剤31の導電粒子3
1aで接続する。The protruding electrode 17 of the semiconductor device 10 and the substrate 22
Substrate electrode 23 and conductive particles 3 of anisotropic conductive adhesive 31
Connect at 1a.
【0048】半導体装置10の短辺に配置した流動制御
膜15によって、異方性導電接着剤31の流動をコント
ロールして、半導体装置10のどの端子の場所でも同じ
流動になる。The flow of the anisotropic conductive adhesive 31 is controlled by the flow control film 15 arranged on the short side of the semiconductor device 10 so that the flow becomes the same at any terminal of the semiconductor device 10.
【0049】このことにより、半導体装置10の突起電
極17と基板22の基板電極23との間に捕獲する異方
性導電接着剤31の導電粒子31aの数を確保する。As a result, the number of conductive particles 31a of the anisotropic conductive adhesive 31 captured between the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22 is ensured.
【0050】〔半導体装置の製造方法説明:図3から図
5〕つぎに半導体装置の製造方法を説明する。図3に示
すように、半導体装置10はシリコン基板11の素子形
成表面にアルミニウムからなる接続電極パッド12を厚
さ1μm形成する。[Description of Method of Manufacturing Semiconductor Device: FIGS. 3 to 5] Next, a method of manufacturing a semiconductor device will be described. As shown in FIG. 3, in the semiconductor device 10, a connection electrode pad 12 made of aluminum is formed to a thickness of 1 μm on the element formation surface of a silicon substrate 11.
【0051】接続電極パッド12は半導体装置の長辺の
二辺にレイアウトする。The connection electrode pads 12 are laid out on two long sides of the semiconductor device.
【0052】図4に示すように、接続電極パッド12を
含む半導体装置10の全面に、半導体素子の保護を目的
とする窒化シリコン膜からなる保護膜13を形成する。As shown in FIG. 4, a protective film 13 made of a silicon nitride film for protecting a semiconductor element is formed on the entire surface of the semiconductor device 10 including the connection electrode pads 12.
【0053】この保護膜13は、プラズマ化学的気相成
長法によって膜厚1μm形成する。また保護膜13は、
燐を含有したシリコン酸化膜を化学的気相成長法によっ
て形成しても良い。This protective film 13 is formed to a thickness of 1 μm by a plasma chemical vapor deposition method. The protective film 13
A silicon oxide film containing phosphorus may be formed by a chemical vapor deposition method.
【0054】感光性レジスト(図示せず)を回転塗布し
た後、所定のマスクを用いて露光現像処理を行う。After spin-coating a photosensitive resist (not shown), exposure and development are performed using a predetermined mask.
【0055】さらに、四フッ化炭素を主成分とするエッ
チングガスを用いたドライエッチング法により接続電極
パッド12が露出するように保護膜13を開口する。Further, an opening is formed in the protective film 13 so that the connection electrode pad 12 is exposed by a dry etching method using an etching gas containing carbon tetrafluoride as a main component.
【0056】その後不要になった感光性レジストをレジ
スト剥離液で除去する。Thereafter, the unnecessary photosensitive resist is removed with a resist stripper.
【0057】半導体装置10の全面に旭化成製感光性ポ
リイミド樹脂PIMEL(商品名)からなる流動制御膜
15を14μmの膜厚で回転塗布する。A flow control film 15 made of a photosensitive polyimide resin PIMEL (trade name) manufactured by Asahi Kasei is spin-coated on the entire surface of the semiconductor device 10 to a thickness of 14 μm.
【0058】その後、所定のマスクを用いて露光現像処
理を行い半導体装置10の短辺の二辺に流動制御膜15
を配置する。Thereafter, an exposure and development process is performed using a predetermined mask, and the flow control film 15 is formed on two short sides of the semiconductor device 10.
Place.
【0059】さらに共通電極膜14を半導体装置10の
全面にアルミニウムを1μm、クロムを0.01μm、
銅を1μmの厚さで順次金属多層膜をスパッタリング法
や真空蒸着法等の方法で形成する。Further, the common electrode film 14 is formed on the entire surface of the semiconductor device 10 by aluminum 1 μm, chromium 0.01 μm,
A metal multilayer film is formed of copper in a thickness of 1 μm sequentially by a method such as a sputtering method or a vacuum evaporation method.
【0060】つぎにシリコン基板11の全面に、厚膜液
状感光性レジストからなるメッキレジスト16を厚さ2
0μm回転塗布して形成する。Next, a plating resist 16 made of a thick liquid photosensitive resist is coated on the entire surface of the silicon substrate 11 to a thickness of 2 mm.
It is formed by spin coating at 0 μm.
【0061】その後、所定のフォトマスクを用いて露光
現像処理を行ない、接続電極パッド12の上の共通電極
膜14の部分のメッキレジスト16に一辺50μmの四
角形の開口部を、端子間の隙間10μmで設ける。Thereafter, an exposure and development process is performed using a predetermined photomask, and a rectangular opening having a side of 50 μm is formed in the plating resist 16 in the portion of the common electrode film 14 on the connection electrode pad 12 by a gap of 10 μm between terminals. To be provided.
【0062】つぎに非シアン系金メッキ液を用いて0.
5A/dm2で金からなる突起電極17を電解メッキに
て15μmの厚さで形成する。Next, a non-cyanide-based gold plating solution was used for 0.1.
A protruding electrode 17 made of gold is formed at a thickness of 15 μm by electrolytic plating at 5 A / dm 2 .
【0063】図5に示すように、不用になったメッキレ
ジスト16を東京応化工業製剥離液104(商品名)に
より除去する。As shown in FIG. 5, the unnecessary plating resist 16 is removed with a stripping solution 104 (trade name) manufactured by Tokyo Ohka Kogyo.
【0064】さらに突起電極17の付け根部分以外の共
通電極膜14を除去する。共通電極膜14の上層メタル
である銅をメルテックス製銅エッチング液エンストリッ
プC(商品名)によりエッチング除去する。つぎに硝酸
セリウムアンモニウムとフェリシアン化カリウムの混合
液により、共通電極膜14の中層メタルのクロムと下層
メタルのアルミニウムのエッチングを行う。Further, the common electrode film 14 other than the base of the protruding electrode 17 is removed. Copper, which is the upper layer metal of the common electrode film 14, is etched away using a copper etchant Enstrip C (trade name) manufactured by Meltex. Next, the chromium of the middle metal and the aluminum of the lower metal of the common electrode film 14 are etched with a mixed solution of cerium ammonium nitrate and potassium ferricyanide.
【0065】共通電極膜14はアルミニウムとクロムと
銅との膜構成を用いたが、チタンやチタン・タングステ
ン合金やニッケルやニッケル・バナジウム合金でも適用
可能である。Although the common electrode film 14 has a film structure of aluminum, chromium, and copper, titanium, a titanium-tungsten alloy, nickel, and a nickel-vanadium alloy are also applicable.
【0066】〔半導体装置と基板との接続方法:図6〕
つぎに半導体装置と基板との接続方法を説明する。図6
に示すように、ガラスからなる基板22に基板電極23
となる酸化インジウムすずを0.2μmの厚さで形成す
る。[Method of Connecting Semiconductor Device to Substrate: FIG. 6]
Next, a method for connecting the semiconductor device to the substrate will be described. FIG.
As shown in FIG.
Is formed at a thickness of 0.2 μm.
【0067】その後、フォトリソグラフィー処理とエッ
チング処理により半導体装置の突起電極に対応するよう
にパターニングする。Thereafter, patterning is performed by photolithography and etching to correspond to the protruding electrodes of the semiconductor device.
【0068】基板22に異方性導電接着剤31を配置す
る。異方性導電接着剤31はエポキシ樹脂からなる絶縁
性樹脂に導電粒子31aを混ぜたもので、25μmの厚
さでシート状にする。導電粒子31aはプラスチックビ
ーズの表面にニッケルさらに金の2層めっきした外形5
μmものを用いている。The anisotropic conductive adhesive 31 is arranged on the substrate 22. The anisotropic conductive adhesive 31 is obtained by mixing conductive particles 31a with an insulating resin made of epoxy resin, and is formed into a sheet having a thickness of 25 μm. The conductive particles 31a have an outer shape 5 in which two layers of nickel and gold are plated on the surface of plastic beads.
μm is used.
【0069】つぎに半導体装置10の突起電極17と基
板22の基板電極23とを位置会わせして異方性導電接
着剤31の上に仮固定する。Next, the projecting electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22 are positioned and temporarily fixed on the anisotropic conductive adhesive 31.
【0070】半導体装置10の裏面をヒートツール32
によって400kg/cm2の圧力にて加圧しながら1
70℃〜220℃の温度で加熱を加えて、異方性導電接
着剤31を硬化する。The back surface of the semiconductor device 10 is
While applying a pressure of 400 kg / cm 2
Heating is applied at a temperature of 70 to 220 ° C. to cure the anisotropic conductive adhesive 31.
【0071】異方性導電接着剤31を硬化させるため加
熱加圧処理により、半導体装置10と基板22との隙間
すなわち保護膜13の表面と基板22の表面との距離は
突起電極17の高さと異方性導電接着剤31の導電粒子
31aの外形によって決まり約20μmになる。The gap between the semiconductor device 10 and the substrate 22, that is, the distance between the surface of the protective film 13 and the surface of the substrate 22 is changed by the heating and pressurizing treatment to cure the anisotropic conductive adhesive 31. The thickness is determined by the outer shape of the conductive particles 31 a of the anisotropic conductive adhesive 31 to be about 20 μm.
【0072】加熱加圧処理を行なう前の異方性導電接着
剤31の厚さは25μmなので、5μmの厚さ分と突起
電極17の分の異方性導電接着剤31が半導体装置10
と基板22との隙間から流れ出す。Since the thickness of the anisotropic conductive adhesive 31 before the heating and pressurizing treatment is 25 μm, the anisotropic conductive adhesive 31 corresponding to the thickness of 5 μm and the protrusion electrode 17 has the semiconductor device 10.
Flows out of the gap between the substrate and the substrate 22.
【0073】異方性導電接着剤31の流動は、半導体装
置10の長辺の二辺に配置している突起電極17と短辺
二辺に配置している流動制御膜15とによって、半導体
装置10のどの端子の場所でも同じ異方性導電接着剤3
1の流動になる。The flow of the anisotropic conductive adhesive 31 is controlled by the protruding electrodes 17 disposed on two long sides of the semiconductor device 10 and the flow control film 15 disposed on two short sides. The same anisotropic conductive adhesive 3 at any of the terminals 10
It becomes 1 flow.
【0074】このことにより、半導体装置10の突起電
極17と基板22の基板電極23との間に捕獲する異方
性導電接着剤31の導電粒子31aの数を確保する。As a result, the number of conductive particles 31a of the anisotropic conductive adhesive 31 captured between the protruding electrode 17 of the semiconductor device 10 and the substrate electrode 23 of the substrate 22 is ensured.
【0075】以上の説明のように半導体装置10の短辺
の二辺に設けた流動制御膜15によって、半導体装置1
0の長辺の二辺に多数ある突起電極17すべて均一に異
方性導電接着剤31の導電粒子31aを捕獲することが
可能となった。As described above, the flow control films 15 provided on the two short sides of the semiconductor device 10 allow the semiconductor device 1
It is possible to uniformly capture the conductive particles 31a of the anisotropic conductive adhesive 31 on all of the many protruding electrodes 17 on the two long sides of 0.
【0076】本発明の実施形態の説明においては、突起
電極17の大きさを一辺50μmの四角形、隣の端子と
の隙間10μmの半導体装置を基板と実装する場合、流
動制御膜15を半導体装置10の短辺の二辺に配置し、
流動制御膜15の頂部が突起電極17の頂部より高さが
3μm低くなるような構造を用いた。In the description of the embodiment of the present invention, when the size of the projecting electrode 17 is 50 μm on a side and a semiconductor device having a gap of 10 μm between adjacent terminals is mounted on the substrate, the flow control film 15 is connected to the semiconductor device 10. Placed on the two short sides of
A structure was used in which the top of the flow control film 15 was 3 μm lower than the top of the bump electrode 17.
【0077】しかし、流動制御膜15を突起電極17の
頂部とほぼ同じ高さに形成し、突起電極17と同じ大き
さで同じ間隔である一辺50μmの四角形、隣の端子と
の隙間10μmで半導体装置10の短辺の二辺に多数配
置しても、同じ効果が得られる。However, the flow control film 15 is formed at substantially the same height as the top of the protruding electrode 17, and is a square having the same size and the same interval as the protruding electrode 17, 50 μm on a side, and a 10 μm gap between adjacent terminals. The same effect can be obtained by arranging a large number on two short sides of the device 10.
【0078】流動制御膜15を半導体装置10の短辺の
二辺に配置し、流動制御膜15の頂部が突起電極17の
頂部より高さが低くなる構造と、流動制御膜15を突起
電極17の頂部とほぼ同じ高さに形成し、突起電極17
と同じ大きさで同じ間隔で半導体装置10の短辺の二辺
に多数配置する構造とは、流動制御膜の形成する高さに
よって選択する。The flow control film 15 is arranged on two short sides of the semiconductor device 10, and the top of the flow control film 15 is lower than the top of the protruding electrode 17. Are formed at substantially the same height as the top of the projection electrode 17.
The structure in which a large number are arranged on two short sides of the semiconductor device 10 at the same size and at the same interval is selected depending on the height of the flow control film.
【0079】流動制御膜の形成する高さが10μm以下
場合は優劣の差は無いが、流動制御膜の形成する高さが
10μmを越えてる場合、流動制御膜15を突起電極1
7の頂部とほぼ同じ高さに形成し、突起電極17と同じ
大きさで同じ間隔で半導体装置10の短辺の二辺に多数
配置する構造が不利になる。When the height of the flow control film is 10 μm or less, there is no difference between the two. However, when the height of the flow control film exceeds 10 μm, the flow control film 15
7 is formed at substantially the same height as the top of the semiconductor device 10, and a large number of the semiconductor devices 10 are arranged at the same size and at the same interval as the protruding electrodes 17.
【0080】つまり、10μmの厚さで塗布した感光性
ポリイミド樹脂からなる流動制御膜15を突起電極17
と同じ大きさで同じ間隔で形成することは非常に難し
い。That is, the flow control film 15 made of a photosensitive polyimide resin applied with a thickness of 10 μm is
It is very difficult to form them at the same size and at the same intervals.
【0081】また、可能であっても高感度の感光性ポリ
イミド樹脂は非常に高価でコスト的に問題となるからで
ある。Further, even if possible, a photosensitive polyimide resin having high sensitivity is very expensive and causes a problem in cost.
【0082】また、図7に示すように、隣の端子との隙
間の距離が広く開いて異方性導電接着剤31の流動が変
わる場合には、隣の端子と隙間の距離が広く開い部分に
流動制御膜15を設けることで、半導体装置10の端子
レイアウトに影響されない実装が実現できる。Further, as shown in FIG. 7, when the distance between the adjacent terminals is widened and the flow of the anisotropic conductive adhesive 31 changes due to wide open, the distance between the adjacent terminals and the open space is large. By providing the flow control film 15 in the semiconductor device, mounting that is not affected by the terminal layout of the semiconductor device 10 can be realized.
【0083】[0083]
【発明の効果】以上の説明で明らかなように本発明によ
る半導体装置の実装構造は、半導体装置10の短辺に配
置した流動制御膜15によって異方性導電接着剤31の
流動をコントロールして、半導体装置10のどの端子の
場所でも同じ流動になるようにした。どの半導体装置1
0の端子でも導体装置の突起電極17と基板22の基板
電極23との間に捕獲する異方性導電接着剤31の導電
粒子31aを均一に充分確保できる。As is clear from the above description, the mounting structure of the semiconductor device according to the present invention controls the flow of the anisotropic conductive adhesive 31 by the flow control film 15 disposed on the short side of the semiconductor device 10. The flow is the same at any terminal location of the semiconductor device 10. Which semiconductor device 1
Even with the terminal of 0, the conductive particles 31a of the anisotropic conductive adhesive 31 captured between the protruding electrode 17 of the conductor device and the substrate electrode 23 of the substrate 22 can be uniformly and sufficiently secured.
【0084】このことにより、接続面積を最小にするこ
とができ、低抵抗かつ高信頼性な微細接続を提供するこ
とが可能である。As a result, the connection area can be minimized, and a fine connection with low resistance and high reliability can be provided.
【図1】本発明の実施形態における半導体装置の実装構
造を示す断面図である。FIG. 1 is a cross-sectional view illustrating a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図2】本発明の実施形態における半導体装置を示す平
面図である。FIG. 2 is a plan view showing a semiconductor device according to the embodiment of the present invention.
【図3】本発明の実施形態における半導体装置の製造方
法を示す断面図である。FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図4】本発明の実施形態における半導体装置の製造方
法を示す断面図である。FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.
【図5】本発明の実施形態における半導体装置の製造方
法を示す断面図である。FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図6】本発明の実施形態における半導体装置の製造方
法を示す断面図である。FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
【図7】本発明の実施形態における半導体装置を示す平
面図である。FIG. 7 is a plan view showing a semiconductor device according to the embodiment of the present invention.
【図8】従来技術における発明が解決しようとする課題
を説明するための半導体装置を示す平面図である。FIG. 8 is a plan view showing a semiconductor device for describing a problem to be solved by the invention in the related art.
【図9】従来技術を説明するための半導体装置を示すの
断面図である。FIG. 9 is a cross-sectional view showing a semiconductor device for explaining a conventional technique.
【図10】従来技術を説明するための半導体装置を示す
の断面図である。FIG. 10 is a cross-sectional view showing a semiconductor device for explaining a conventional technique.
【図11】従来技術を説明するための半導体装置を示す
の断面図である。FIG. 11 is a cross-sectional view showing a semiconductor device for explaining a conventional technique.
【図12】従来技術を説明するための半導体装置の実装
構造を示すの断面図である。FIG. 12 is a cross-sectional view showing a mounting structure of a semiconductor device for explaining a conventional technique.
10:半導体装置 11:シリコン基板 12:接続電極パッド 13:保護膜 14:共通電極膜 15:流動制御膜 16:メッキレジスト 17:突起電極 22:基板 23:基板電極 3
1:異方性導電接着剤Reference Signs List 10: semiconductor device 11: silicon substrate 12: connection electrode pad 13: protective film 14: common electrode film 15: flow control film 16: plating resist 17: projecting electrode 22: substrate 23: substrate electrode 3
1: Anisotropic conductive adhesive
Claims (7)
護膜と、 半導体装置の外周部において接続領域以外部分の保護膜
の上に設ける流動制御膜と、 接続電極パッドの上に設ける共通電極膜と、 共通電極膜の上に設ける突起電極とを有することを特徴
とする半導体装置。A protection film having an opening on the connection electrode pad; a flow control film provided on the protection film in a portion other than the connection region in an outer peripheral portion of the semiconductor device; and a common electrode provided on the connection electrode pad. A semiconductor device comprising: a film; and a protruding electrode provided on the common electrode film.
体装置。2. The semiconductor device according to claim 1, wherein the flow control films are provided on two short sides of the semiconductor device.
突起電極間の隙間が突起電極の幅よりも間隔が広い領域
に設ける請求項1に記載の半導体装置。3. The flow control film according to claim 1, wherein the gap between the protruding electrodes on the two short sides of the semiconductor device and the two long sides of the semiconductor device is provided in a region where the gap is wider than the width of the protruding electrodes. 3. The semiconductor device according to claim 1.
導体装置。4. The semiconductor device according to claim 1, wherein the top of the flow control film is lower than the top of the protruding electrode.
記載の半導体装置。5. The semiconductor device according to claim 1, wherein the height of the top of the flow control film is substantially the same as the height of the top of the protruding electrode.
護膜を形成し、接続電極パッドが開口するように保護膜
をパターンニングする工程と、 流動制御膜を半導体装置に形成する工程と、 流動制御膜を半導体装置の外周部において接続領域以外
の部分に配置するようにパターンニングする工程と、 共通電極膜を半導体装置に形成する工程と、 メッキレジストを半導体装置に形成する工程と、 メッキレジストを突起電極形成領域が開口するようにパ
ターンニングする工程と、 メッキレジスト開口部にメッキにより突起電極を形成す
る工程と、 メッキレジストを除去する工程と、突起電極の付け根以
外の部分の共通電極膜を除去する工程とを有することを
特徴とする半導体装置の製造方法。7. A step of forming a protective film on a semiconductor device having connection electrode pads and patterning the protective film so that the connection electrode pads are opened; a step of forming a flow control film on the semiconductor device; A step of patterning the film so as to be arranged in a portion other than the connection region in an outer peripheral portion of the semiconductor device; a step of forming a common electrode film on the semiconductor device; a step of forming a plating resist on the semiconductor device; Patterning a projection electrode forming region so as to be opened; forming a projection electrode by plating in a plating resist opening; removing a plating resist; and removing a common electrode film in a portion other than the base of the projection electrode. Removing the semiconductor device.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008172022A (en) * | 2007-01-11 | 2008-07-24 | Seiko Epson Corp | Semiconductor device, electronic device, and manufacturing method of electronic device |
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2000
- 2000-03-27 JP JP2000085844A patent/JP2001274193A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008172022A (en) * | 2007-01-11 | 2008-07-24 | Seiko Epson Corp | Semiconductor device, electronic device, and manufacturing method of electronic device |
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