JP2001036309A - Multichip module connection structure - Google Patents
Multichip module connection structureInfo
- Publication number
- JP2001036309A JP2001036309A JP20183599A JP20183599A JP2001036309A JP 2001036309 A JP2001036309 A JP 2001036309A JP 20183599 A JP20183599 A JP 20183599A JP 20183599 A JP20183599 A JP 20183599A JP 2001036309 A JP2001036309 A JP 2001036309A
- Authority
- JP
- Japan
- Prior art keywords
- line
- chip
- connection structure
- film
- dielectric substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Waveguide Connection Structure (AREA)
- Waveguides (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はマルチチップモジュ
ール(MCM)接続構造、特にコプレーナ線路又は入出
力端にRF(無線周波数)プローバ測定部を有するMM
IC(モノリシックマイクロ波集積回路)チップ、マイ
クロストリップライン又はコプレーナ線路を構成する誘
電体基板であるマイクロ波回路要素間を接続線路を用い
て接続する接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module (MCM) connection structure, particularly a MM having an RF (radio frequency) prober measuring section at a coplanar line or at an input / output end.
The present invention relates to a connection structure for connecting microwave circuit elements, which are dielectric substrates constituting an IC (monolithic microwave integrated circuit) chip, a microstrip line, or a coplanar line, using connection lines.
【0002】[0002]
【従来の技術】マイクロ波回路において、高周波トラン
ジスタ、FET(電界効果トランジスタ)、抵抗及びキ
ャパシタ(コンデンサ)等で構成したマイクロ波集積回
路を、半導体結晶(GaAs、Si等)等の基板上にモ
ノリシックに集積化するMMICチップは、小型、高信
頼性、低価格等の大きな利点を有している。2. Description of the Related Art In a microwave circuit, a microwave integrated circuit composed of a high-frequency transistor, an FET (field effect transistor), a resistor and a capacitor (capacitor) is monolithically mounted on a substrate such as a semiconductor crystal (GaAs, Si, etc.). An MMIC chip integrated into a semiconductor device has significant advantages such as small size, high reliability, and low price.
【0003】近年、斯かるMMICチップを複数個使用
して電子機器モジュールを構成するMCM技術が検討さ
れている。従来、このMCM技術は、金属又は全面導体
の誘電体基板から成るベース基板に、MMICチップ、
マイクロ波回路を構成する誘電体基板等をマウントし、
これらをボンディングワイヤ又はリボンで接続した構造
が一般的である。このMCM接続構造を使用する技術
は、例えば特開平9−148524号公報の「高周波回
路装置」に開示されている。即ち、擬似的なコプレーナ
線路による接続構造である。In recent years, MCM technology for configuring an electronic device module using a plurality of such MMIC chips has been studied. Conventionally, this MCM technology employs an MMIC chip,
Mount the dielectric substrate etc. that constitute the microwave circuit,
A structure in which these are connected by a bonding wire or a ribbon is generally used. A technique using the MCM connection structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-148524, entitled "High Frequency Circuit Device". That is, the connection structure is a pseudo coplanar line.
【0004】斯かるMCM接続構造を図8乃至図10を
参照して説明する。図8は、従来のMCM接続構造の斜
視図、図9は上面図、図10は図9の線A−A’に沿う
断面図である。このMCM接続構造は、ベース基板16
0上に配置された複数のMMICチップ6を有する。各
MMICチップ6の裏面には接地導体9を有し、上面に
入出力信号線路端8を有する。各MMICチップ6の端
部近傍には、ビアホール7を介して接地導体9と接属さ
れたMMICチップ接地端子5を有する。対向配置され
たMMICチップ6の信号線路8同士及び接地端子5同
士は、金ワイヤ又は金リボン等で構成される接地導体付
き擬似コプレーナ線路11で相互接続される。また、こ
の従来技術において、接地導体付き擬似コプレーナ線路
11の直下には、高誘電体材料13を含んだ樹脂12を
有する。[0004] Such an MCM connection structure will be described with reference to FIGS. 8 is a perspective view of a conventional MCM connection structure, FIG. 9 is a top view, and FIG. 10 is a cross-sectional view taken along line AA ′ of FIG. This MCM connection structure is based on the base substrate 16
It has a plurality of MMIC chips 6 arranged on the “0”. Each MMIC chip 6 has a ground conductor 9 on the back surface and an input / output signal line end 8 on the top surface. An MMIC chip ground terminal 5 connected to a ground conductor 9 via a via hole 7 is provided near an end of each MMIC chip 6. The signal lines 8 and the ground terminals 5 of the MMIC chips 6 disposed opposite to each other are interconnected by a pseudo-coplanar line 11 with a ground conductor formed of a gold wire or a gold ribbon. In this prior art, a resin 12 containing a high dielectric material 13 is provided immediately below the pseudo coplanar line 11 with a ground conductor.
【0005】このように構成された接地導体付き擬似的
コプレーナ接続線路は、接続部での特性インピーダンス
不整合を抑えることができる。また、誘電体樹脂12及
び内部に含まれる高誘電体材料の材質、混入密度を変更
して、接続線路の特性インピーダンスを広範囲で制御可
能である。[0005] The pseudo coplanar connection line with the ground conductor configured as described above can suppress the characteristic impedance mismatch at the connection portion. Further, the characteristic impedance of the connection line can be controlled in a wide range by changing the material and the mixing density of the dielectric resin 12 and the high dielectric material contained therein.
【0006】また、関連技術は、特開昭63−2335
46号公報の「入力信号伝送回路」、特開平7−245
11号公報の「混成集積回路」、特開平6−37202
号公報の「マイクロ波ICパッケージ」、特開平4−3
8855号公報の「マイクロ波帯IC用パッケージ」及
び特開昭61−234055号公報の「半導体装置」に開
示されている。A related technique is disclosed in Japanese Patent Application Laid-Open No. 63-2335.
No. 46, “Input signal transmission circuit”, JP-A-7-245
No. 11, "Hybrid integrated circuit", JP-A-6-37202
Publication "Microwave IC Package",
No. 8,855, "Microwave band IC package" and Japanese Patent Application Laid-Open No. 61-234055, "Semiconductor Device".
【0007】[0007]
【発明が解決しようとする課題】しかし、上述した従来
技術では、信号用及び設置用の3線路が独立の金ワイヤ
または金リボン等で構成される為に、接続線路の長さ
(L1)、接続線路間の幅(W1)及び高さ(h1)を
3線路とも等しく平行に接地することは不可能である。
また、振動や加速度により3線路が異なる形状へ変化す
るおそれもあり、これらは全て特性インピーダンスの変
動を生じることとなる。However, in the above-mentioned prior art, since the three lines for signal and for installation are composed of independent gold wires or gold ribbons, the length of the connection line (L1), It is impossible to ground the width (W1) and the height (h1) between the connection lines equally and parallel to all three lines.
In addition, the three lines may change to different shapes due to vibration or acceleration, and all of these will cause variations in characteristic impedance.
【0008】本発明の目的は、MCMにおける接続部で
の特性インピーダンスを安定化させると共に、接続線路
の特性インピーダンスを広範囲にわたって定量的に制御
でき且つ簡単に接続できるMCM接続構造を提供するこ
とである。SUMMARY OF THE INVENTION It is an object of the present invention to provide an MCM connection structure that stabilizes the characteristic impedance at a connection portion in an MCM, and that can quantitatively control the characteristic impedance of a connection line over a wide range and can easily connect. .
【0009】[0009]
【課題を解決するための手段】前述の課題を解決するた
め、本発明によるマルチチップモジュール接続構造は、
次のような特徴的な構成を採用している。In order to solve the above-mentioned problems, a multi-chip module connection structure according to the present invention comprises:
The following characteristic configuration is adopted.
【0010】(1)誘電体基板上にマイクロ波ICチッ
プを直接搭載し、該マイクロ波ICチップの信号線路と
前記誘電体基板上の信号線路との間を相互接続するマル
チチップモジュール接続構造において、前記誘電体基板
及び前記マイクロ波ICチップの接続部に、可撓性フィ
ルム上に線路が並列に被着形成されたフィルム状コプレ
ーナ型接続線路を設け、前記誘電体基盤と前記マイクロ
波ICチップの前記信号線路間を相互接続するマルチチ
ップモジュール接続構造。(1) A multi-chip module connection structure in which a microwave IC chip is directly mounted on a dielectric substrate and a signal line of the microwave IC chip and a signal line on the dielectric substrate are interconnected. A connecting portion between the dielectric substrate and the microwave IC chip, a film-shaped coplanar type connecting line in which a line is formed in parallel on a flexible film, and the dielectric substrate and the microwave IC chip are provided. A multi-chip module connection structure for interconnecting the signal lines.
【0011】(2)前記フィルム状コプレーナ型接続線
路と、前記信号線路間はマイクロカプセル型異方導電性
接着剤を用いて接続する上記(1)のマルチチップモジ
ュール接続構造。(2) The multi-chip module connection structure according to (1), wherein the film-shaped coplanar type connection line and the signal line are connected using a microcapsule type anisotropic conductive adhesive.
【0012】(3)前記誘電体基板の前記信号線路は、
マイクロストリップ線路である上記(1)又は(2)の
マルチチップモジュール接続構造。(3) The signal line of the dielectric substrate is:
The multichip module connection structure according to the above (1) or (2), which is a microstrip line.
【0013】(4)前記誘電体基板の前記信号線路は、
信号線路と接地パターンとを有するコプレーナ線路であ
る上記(1)又は(2)のマルチチップモジュール接続
構造。(4) The signal line of the dielectric substrate is:
The multi-chip module connection structure according to the above (1) or (2), which is a coplanar line having a signal line and a ground pattern.
【0014】(5)誘電体基板上に直接搭載された複数
のマイクロ波ICチップの信号線路及び接地端子間を相
互接続するマルチチップモジュール接続構造において、
前記マイクロ波ICチップの対向部に、可撓性フィルム
上に線路が並列に被着形成されたフィルム状コプレーナ
型接続線路を設け、前記マイクロ波ICチップの前記信
号線路及び接地端子間を前記フィルム状コプレーナ型接
続線路により相互接続するマルチチップモジュール接続
構造。(5) In a multi-chip module connection structure for interconnecting signal lines and ground terminals of a plurality of microwave IC chips directly mounted on a dielectric substrate,
A film-like coplanar type connection line in which lines are formed in parallel on a flexible film is provided on a facing portion of the microwave IC chip, and the film between the signal line and the ground terminal of the microwave IC chip is the film. Multi-chip module connection structure interconnected by coplanar connection lines.
【0015】(6)前記フィルム状コプレーナ型接続線
路は表面に塗布したマイクロカプセル型導電性接着剤を
用いて接続する上記(5)のマルチチップモジュール接
続構造。(6) The multi-chip module connection structure according to (5), wherein the film-shaped coplanar connection lines are connected using a microcapsule-type conductive adhesive applied to the surface.
【0016】(7)前記各マイクロ波ICチップは、裏
面に接地導体を有し、該接地導体と前記接地端子間をビ
アホールにより接続する上記(5)又は(6)のマルチ
チップモジュール接続構造。(7) The multi-chip module connection structure according to (5) or (6), wherein each of the microwave IC chips has a ground conductor on a back surface, and the ground conductor and the ground terminal are connected by a via hole.
【0017】[0017]
【発明の実施の形態】以下、本発明によるマルチチップ
モジュール(MCM)接続構造の好適実施形態例の構成
及び動作を添付図、特に図1乃至図7を参照して詳細に
説明する。尚、上述した従来技術の構成要素と対応する
構成要素には、便宜上同一参照符号を使用するものとす
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction and operation of a preferred embodiment of a multi-chip module (MCM) connection structure according to the present invention will be described below in detail with reference to the accompanying drawings, particularly FIGS. Note that, for convenience, the same reference numerals are used for components corresponding to the above-described components of the related art.
【0018】先ず、図1乃至図3は、本発明によるMC
M接続構造の第1実施形態例を示し、図1は斜視図、図
2は上面図及び図3は図2中の線A−A’に沿う断面図
である。First, FIGS. 1 to 3 show an MC according to the present invention.
FIG. 1 is a perspective view, FIG. 2 is a top view, and FIG. 3 is a sectional view taken along line AA ′ in FIG.
【0019】これら図1乃至図3のMCM接続構造は、
MMICチップ6を誘電体基板2に接続する例である。
誘電体基板2は、裏面に接地導体1を有すると共に、上
面にマイクロストリップ線路(信号線路)3及び接続部
接地パターン101を有する。他方、MMICチップ6
は、裏面に接地導体9を有し、上面に入出力信号線路8
及び接地端子5を有する。更に、MMICチップ6は、
裏面の接地導体1と接地端子5との間を連通するビアホ
ール7を有する。The MCM connection structure shown in FIGS.
This is an example in which the MMIC chip 6 is connected to the dielectric substrate 2.
The dielectric substrate 2 has a ground conductor 1 on the back surface and a microstrip line (signal line) 3 and a connection part ground pattern 101 on the upper surface. On the other hand, the MMIC chip 6
Has a ground conductor 9 on the back surface and an input / output signal line 8 on the top surface.
And a ground terminal 5. Further, the MMIC chip 6
There is a via hole 7 communicating between the ground conductor 1 on the back surface and the ground terminal 5.
【0020】誘電体基板2上のマイクロストリップ線路
3は、接続部接地パターン101との間にギャップgを
設けた構造であり、線路は接地導体付きコプレーナ線路
を形成する。接続部接地パターン101とマイクロスト
リップ線路3間のギャップg及びマイクロストリップ線
路3の幅及びそれらの形状は、マイクロストリップ線路
3を伝わる伝送信号が接地導体付きコプレーナ線路に効
率良く変換及び伝送されるよう設定する。The microstrip line 3 on the dielectric substrate 2 has a structure in which a gap g is provided between the microstrip line 3 and the connection portion ground pattern 101, and the line forms a coplanar line with a ground conductor. The gap g between the connection ground pattern 101 and the microstrip line 3 and the width and shape of the microstrip line 3 are set so that the transmission signal transmitted through the microstrip line 3 is efficiently converted and transmitted to the coplanar line with the ground conductor. Set.
【0021】誘電体基板2とその上に搭載されるMMI
Cチップ6間は、フィルム状コプレーナ型接続線路10
0により相互接続される。このフィルム状コプレーナ型
接続線路100は、極めて可撓性が高く且つ耐熱性を有
する誘電体フィルムの表面に一定幅且つ一定間隔で平行
に配設された導電箔を有する。Dielectric substrate 2 and MMI mounted thereon
Between the C chips 6, a film-shaped coplanar connection line 10
0 interconnected. The film-shaped coplanar connection line 100 has conductive foils which are arranged in parallel with a constant width and a constant interval on the surface of a dielectric film having extremely high flexibility and heat resistance.
【0022】図4は、上述したフィルム状コプレーナ型
接続線路100は、例えば特開平2−91956号公報
に開示されるコプレーナ線路を有する接地導体付きフィ
ルムキャリアを改良した線路である。このフィルム状コ
プレーナ型接続線路100は、可撓性の絶縁フィルム
(誘電体層)123の上面に接着剤層122を介して第
1接続線路120と、その両側の第2接続線路121を
被着形成する。更に、これら表面に、マイクロカプセル
型異方導電性接着剤134を塗布してコプレーナ型接続
線路とする。斯かる構成のフィルム状コプレーナ型接続
線路100によると、特性インピーダンスZ0は、第1
及び第2接続線路120、121の幅W3、W4、線路
120、121間のピッチ(間隔)P、誘電体厚h3、誘
電体の比誘電率、線路導体厚tにより決定されること当
業者に周知のとおりである。これらのパラメータを適当
に選択して、接続線路の特性インピーダンスZ0を所望
値に設定する。FIG. 4 shows a film-shaped coplanar type connection line 100 obtained by improving a film carrier with a ground conductor having a coplanar line disclosed in, for example, JP-A-2-91956. This film-shaped coplanar connection line 100 has a first connection line 120 and a second connection line 121 on both sides of the first connection line 120 attached to the upper surface of a flexible insulating film (dielectric layer) 123 via an adhesive layer 122. Form. Further, a microcapsule type anisotropic conductive adhesive 134 is applied to these surfaces to form a coplanar type connection line. According to the film-like coplanar connection line 100 having such a configuration, the characteristic impedance Z0 is equal to the first impedance.
And the widths W3 and W4 of the second connection lines 120 and 121, the pitch (interval) P between the lines 120 and 121, the dielectric thickness h3, the relative permittivity of the dielectric, and the line conductor thickness t. It is well known. By appropriately selecting these parameters, the characteristic impedance Z0 of the connection line is set to a desired value.
【0023】図4に示す如きフィルム状コプレーナ型接
続線路100を、誘電体基板2上のマイクロストリップ
線路3とMMICチップ6の入出力端の接続部分におい
て、第1接続線路120は、マイクロストリップ線路3
とMMICチップ6の信号線路8を接続し、第2接続線
路121は、MMICチップ6の接地端子5及び誘電体
基板2上の接続部接地パターン101に接続する。接続
方法又は手段は、図5に拡大断面図で示す。即ち、表面
にマイクロカプセル型異方導電性接着剤134を塗布し
たフィルム状コプレーナ型接続線路100を上下反転
(フェースダウン)させ、各接続線路120、121の接
続部に上方から圧力を加える。これにより、マイクロカ
プセル型異方導電性接着剤134により電気的且つ機械
的に接続する。このマイクロカプセル型異方導電性接着
剤134は、電気的絶縁性及び耐湿性に優れた絶縁層
(樹脂)130でコーティングされた導電性金属粒子1
31が入った接着剤であり、接続部を加圧することによ
り、金属粒子131の外周のコーティングが破壊された
導電性金属粒子132を介して接続ライン133と接続
線路120、121間を電気的に接続する。A film-like coplanar type connection line 100 as shown in FIG. 4 is connected to the microstrip line 3 on the dielectric substrate 2 and the input / output end of the MMIC chip 6, and the first connection line 120 is a microstrip line. 3
And the signal line 8 of the MMIC chip 6, and the second connection line 121 is connected to the ground terminal 5 of the MMIC chip 6 and the connection ground pattern 101 on the dielectric substrate 2. The connection method or means is shown in an enlarged sectional view in FIG. That is, the film-shaped coplanar type connection line 100 having the surface coated with the microcapsule type anisotropic conductive adhesive 134 is turned upside down.
(Face down), and a pressure is applied to the connection between the connection lines 120 and 121 from above. Thus, the microcapsule type anisotropic conductive adhesive 134 is electrically and mechanically connected. The microcapsule type anisotropic conductive adhesive 134 is made of conductive metal particles 1 coated with an insulating layer (resin) 130 having excellent electrical insulation and moisture resistance.
31 is an adhesive, and by pressurizing the connection portion, the connection between the connection line 133 and the connection lines 120 and 121 is electrically conducted via the conductive metal particles 132 in which the coating on the outer periphery of the metal particles 131 is broken. Connecting.
【0024】斯かる接続構造により、従来構造で特性イ
ンピーダンス変動の問題となる各接続線路の長さL2、
幅W2及び高さh2のばらつきを均一化できる。また、
熱や振動及び衝撃による接続線路の形状変化があって
も、その特性インピーダンスZ0は極めて安定であるこ
とに注目されたい。また、上述したように、接続線路1
00の特性インピーダンスは、パラメータを選択するこ
とにより、誘電体基板2上のマイクロストリップ線路3
及びMMICチップ6の信号線路8の特性インピーダン
スに合わせて広範囲に制御可能である。With such a connection structure, the length L2 of each connection line, which causes a problem of characteristic impedance variation in the conventional structure,
Variations in the width W2 and the height h2 can be made uniform. Also,
Note that the characteristic impedance Z0 is extremely stable even when the shape of the connection line changes due to heat, vibration and shock. Also, as described above, the connection line 1
The characteristic impedance of the microstrip line 3 on the dielectric substrate 2 can be adjusted by selecting a parameter.
And can be controlled in a wide range according to the characteristic impedance of the signal line 8 of the MMIC chip 6.
【0025】図4に示す如き、フィルム状コプレーナ型
接続線路100を図5に示す如く接続方法で接続した図
1乃至図3のMCM接続構造によると、誘電体基板2上
のマイクロストリップ線路3の入力端から入力されるR
F信号は、マイクロストリップ線路3を伝送される。M
MICチップ6との接続部の手前でマイクロストリップ
線路3と接続部接地パターン101から成る接地導体付
きコプレーナ線路を伝送する信号に変換される。更に、
フィルム状コプレーナ型接続線路100を伝送してMM
ICチップ6の入力端に供給される。尚、MMICチッ
プ6の出力端と誘電体基板2のマイクロストリップ線路
間についても、図1乃至図3は図示しないが、入力端と
同様に動作する。フィルム状コプレーナ型接続線路10
0の特性インピーダンスをマイクロストリップ線路3及
びMMICチップ6の信号線路8の特性インピーダンス
と整合することにより、信号歪や損失なく相互接続が可
能である。As shown in FIG. 4, according to the MCM connection structure shown in FIGS. 1 to 3 in which film-shaped coplanar connection lines 100 are connected by a connection method as shown in FIG. R input from the input end
The F signal is transmitted through the microstrip line 3. M
Before the connection with the MIC chip 6, the signal is converted into a signal transmitted through a coplanar line with a ground conductor composed of the microstrip line 3 and the connection ground pattern 101. Furthermore,
MM is transmitted through the film-shaped coplanar connection line 100.
It is supplied to the input terminal of the IC chip 6. Although not shown in FIGS. 1 to 3, the operation between the output terminal of the MMIC chip 6 and the microstrip line of the dielectric substrate 2 is the same as that of the input terminal. Coplanar film connecting line 10
By matching the characteristic impedance of 0 with the characteristic impedance of the microstrip line 3 and the signal line 8 of the MMIC chip 6, interconnection is possible without signal distortion or loss.
【0026】[0026]
【発明の他の実施形態例】次に図6及び図7を参照し
て、本発明によるマルチチップモジュール接続構造の他
の実施形態例を説明する。Next, another embodiment of the multi-chip module connection structure according to the present invention will be described with reference to FIGS. 6 and 7. FIG.
【0027】図6は、本発明によるマルチチップモジュ
ール接続構造の第2実施形態例の斜視図である。このM
CM接続構造は、図1〜図3に示した第1実施形態例の
MCM接続構造と類似する。主要相違点は、誘電体基板
2’の上面に信号線路151と、これを包囲する接地パ
ターン150からなるコプレーナ線路が形成されている
ことである。このコプレーナ線路151、150をフィ
ルム状コプレーナ型接続線路100によりMMICチッ
プ6の信号線路8及び接地端子5と相互接続している。
MMICチップ6は、図1のMMICチップ6と同様に
上面に信号線路8と接地端子5、裏面に接地導体9を有
する。更に、ビアホール7により、接地端子5と接地導
体9間を接続している。このフィルム状コプレーナ型接
続線路100と、誘電体基板2及びMMICチップ6と
の接続は、図5で説明した方法で接続しても良い。FIG. 6 is a perspective view of a multi-chip module connection structure according to a second embodiment of the present invention. This M
The CM connection structure is similar to the MCM connection structure of the first embodiment shown in FIGS. The main difference is that a signal line 151 and a coplanar line including a ground pattern 150 surrounding the signal line 151 are formed on the upper surface of the dielectric substrate 2 '. The coplanar lines 151 and 150 are interconnected to the signal line 8 and the ground terminal 5 of the MMIC chip 6 by a film-shaped coplanar connecting line 100.
The MMIC chip 6 has a signal line 8 and a ground terminal 5 on the upper surface and a ground conductor 9 on the back surface, similarly to the MMIC chip 6 of FIG. Further, the ground terminal 5 and the ground conductor 9 are connected by the via hole 7. The connection between the film-shaped coplanar connection line 100 and the dielectric substrate 2 and the MMIC chip 6 may be performed by the method described with reference to FIG.
【0028】次に、図7は、本発明によるMCM接続構
造の第3実施形態例の斜視図である。このMCM接続構
造によると、誘電体基板160上に搭載した一対のMM
ICチップ6、6をフィルム状コプレーナ型接続線路1
00を使用して相互接続する場合を示す。即ち、金属又
は全面導体化された誘電体基板(ベース基板)160上に
載置された一対のMMICチップ6、6の信号線路8と
接地端子5同士をフィルム状コプレーナ型接続線路10
0にて相互接続する。このフィルム状コプレーナ型接続
線路100は、図4に示すフィルム状コプレーナ型接続
線路100と同じでよく、その線路120、121によ
り各MMICチップ6の信号線路8および接地端子5間
を特性インピーダンス整合状態で相互接続する。接続方
法も上述した如く、マイクロカプセル型異方導電性接着
剤を使用するのが好ましい。FIG. 7 is a perspective view of a third embodiment of the MCM connection structure according to the present invention. According to this MCM connection structure, a pair of MMs mounted on the dielectric substrate 160
The IC chip 6 is connected to the film-shaped coplanar connection line 1
The case of interconnection using 00 is shown. That is, the signal line 8 and the ground terminal 5 of the pair of MMIC chips 6 and 6 mounted on a dielectric substrate (base substrate) 160 which is made of a metal or a whole conductor are connected to the film-like coplanar connection line 10.
Connect at 0. This film-shaped coplanar type connection line 100 may be the same as the film-shaped coplanar type connection line 100 shown in FIG. 4, and the lines 120 and 121 establish a characteristic impedance matching state between the signal line 8 and the ground terminal 5 of each MMIC chip 6. To interconnect. As described above, it is preferable to use a microcapsule type anisotropic conductive adhesive.
【0029】以上、本発明によるMCM接続構造の好適
実施形態例の構成及び動作を詳述した。しかし、本発明
は上述した特定例のみに限定されるべきではなく、本発
明の要旨を逸脱することなく、種々の変形変更が可能で
ある。例えば、MMICチップは、入出力信号線路端の
みではなく、MMICチップ全面で接地導体付きコプレ
ーナ線路を構成しても良い。また、接続は導電性接着剤
以外の方法で行なってもよい。The configuration and operation of the preferred embodiment of the MCM connection structure according to the present invention have been described above in detail. However, the present invention should not be limited to only the specific examples described above, and various modifications can be made without departing from the gist of the present invention. For example, in the MMIC chip, a coplanar line with a ground conductor may be formed not only at the input / output signal line end but also over the entire surface of the MMIC chip. The connection may be made by a method other than the conductive adhesive.
【0030】[0030]
【発明の効果】上述の説明から理解される如く、本発明
のMCM接続構造によると、誘電体基板上のマイクロス
トリップ線路又はコプレーナ線路とMMICチップの信
号線路とをフィルム状コプレーナ型接続線路を用いて相
互接続することにより、安定的に特性インピーダンス整
合状態で接続可能である。また、マイクロカプセル型異
方導電性接着剤を使用することにより、簡単且つ自動化
して接続可能であるのでモジュールの小型化が可能であ
るという実用上の顕著な効果を有する。As will be understood from the above description, according to the MCM connection structure of the present invention, the microstrip line or coplanar line on the dielectric substrate and the signal line of the MMIC chip are formed using a film-shaped coplanar connection line. , And can be stably connected in a characteristic impedance matching state. Further, the use of the microcapsule type anisotropic conductive adhesive has a remarkable practical effect that the module can be miniaturized because it can be connected simply and automatically.
【図1】本発明によるMCM接続構造の第1実施形態例
の斜視図である。FIG. 1 is a perspective view of a first embodiment of an MCM connection structure according to the present invention.
【図2】図1のMCM接続構造の上面図である。FIG. 2 is a top view of the MCM connection structure of FIG. 1;
【図3】図2のMCM接続構造の線A−A’に沿う断面
図である。FIG. 3 is a cross-sectional view of the MCM connection structure of FIG. 2 taken along line AA ′.
【図4】本発明によるMCM接続構造に使用するフィル
ム状コプレーナ型接続線路の好適例の斜視図である。FIG. 4 is a perspective view of a preferred example of a film-shaped coplanar connection line used for the MCM connection structure according to the present invention.
【図5】図4のフィルム状コプレーナ型接続線路の接続
状態を示す拡大断面図である。FIG. 5 is an enlarged sectional view showing a connection state of the film-shaped coplanar connection line of FIG. 4;
【図6】本発明によるMCM接続構造の第2実施形態例
の斜視図である。FIG. 6 is a perspective view of a second embodiment of the MCM connection structure according to the present invention.
【図7】本発明によるMCM接続構造の第3実施形態例
の斜視図である。FIG. 7 is a perspective view of a third embodiment of the MCM connection structure according to the present invention.
【図8】従来のMCM接続構造の斜視図である。FIG. 8 is a perspective view of a conventional MCM connection structure.
【図9】図8のMCM接続構造の上面図である。FIG. 9 is a top view of the MCM connection structure of FIG. 8;
【図10】図9のMCM接続構造の線A−A’に沿う断
面図である。FIG. 10 is a cross-sectional view of the MCM connection structure of FIG. 9 taken along line AA ′.
【符号の説明】 1、9 接地導体 2、2’、160 誘電体基板(ベース基板) 3、8 信号線路 5 接地端子 6 マイクロ波ICチップ(MMICチ
ップ) 7 ビアホール 100 フィルム状コプレーナ型接続線路 101 接続部接地パターン 120、121 接続線路 123 誘電体層 130 絶縁層 131 金属粒子 134 マイクロカプセル型異方導電性接着
剤 150、151 コプレーナ線路[Description of Signs] 1, 9 Ground conductor 2, 2 ', 160 Dielectric substrate (base substrate) 3, 8 Signal line 5 Ground terminal 6 Microwave IC chip (MMIC chip) 7 Via hole 100 Film-shaped coplanar connection line 101 Connection part ground pattern 120, 121 Connection line 123 Dielectric layer 130 Insulation layer 131 Metal particles 134 Microcapsule type anisotropic conductive adhesive 150, 151 Coplanar line
Claims (7)
接搭載し、該マイクロ波ICチップの信号線路と前記誘
電体基板上の信号線路との間を相互接続するマルチチッ
プモジュール接続構造において、 前記誘電体基板及び前記マイクロ波ICチップの接続部
に、可撓性フィルム上に線路が並列に被着形成されたフ
ィルム状コプレーナ型接続線路を設け、前記誘電体基盤
と前記マイクロ波ICチップの前記信号線路間を相互接
続することを特徴とするマルチチップモジュール接続構
造。1. A multi-chip module connection structure for directly mounting a microwave IC chip on a dielectric substrate and interconnecting a signal line of the microwave IC chip and a signal line on the dielectric substrate. A connecting portion between the dielectric substrate and the microwave IC chip is provided with a film-shaped coplanar type connecting line in which a line is formed in parallel on a flexible film, and a connection between the dielectric substrate and the microwave IC chip is provided. A multi-chip module connection structure, wherein the signal lines are interconnected.
前記信号線路間はマイクロカプセル型異方導電性接着剤
を用いて接続することを特徴とする請求項1に記載のマ
ルチチップモジュール接続構造。2. The film-shaped coplanar connection line,
2. The multi-chip module connection structure according to claim 1, wherein the signal lines are connected using a microcapsule type anisotropic conductive adhesive.
ロストリップ線路であることを特徴とする請求項1又は
2に記載のマルチチップモジュール接続構造。3. The multi-chip module connection structure according to claim 1, wherein the signal line of the dielectric substrate is a microstrip line.
路と接地パターンとを有するコプレーナ線路であること
を特徴とする請求項1又は2に記載のマルチチップモジ
ュール接続構造。4. The multichip module connection structure according to claim 1, wherein said signal line of said dielectric substrate is a coplanar line having a signal line and a ground pattern.
クロ波ICチップの信号線路及び接地端子間を相互接続
するマルチチップモジュール接続構造において、 前記マイクロ波ICチップの対向部に、可撓性フィルム
上に線路が並列に被着形成されたフィルム状コプレーナ
型接続線路を設け、前記マイクロ波ICチップの前記信
号線路及び接地端子間を前記フィルム状コプレーナ型接
続線路により相互接続することを特徴とするマルチチッ
プモジュール接続構造。5. A multi-chip module connection structure for interconnecting signal lines and ground terminals of a plurality of microwave IC chips directly mounted on a dielectric substrate, wherein a flexible portion is provided on a facing portion of the microwave IC chip. A film-like coplanar connection line in which lines are formed in parallel on a conductive film, and the signal line and the ground terminal of the microwave IC chip are interconnected by the film-like coplanar connection line. Multi-chip module connection structure.
面に塗布したマイクロカプセル型導電性接着剤を用いて
接続することを特徴とする請求項5に記載のマルチチッ
プモジュール接続構造。6. The multi-chip module connection structure according to claim 5, wherein said film-shaped coplanar connection lines are connected using a microcapsule-type conductive adhesive applied to the surface.
地導体を有し、該接地導体と前記接地端子間をビアホー
ルにより接続することを特徴とする請求項5又は6に記
載のマルチチップモジュール接続構造。7. The multi-chip module according to claim 5, wherein each of the microwave IC chips has a ground conductor on a back surface, and the ground conductor and the ground terminal are connected by a via hole. Connection structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20183599A JP2001036309A (en) | 1999-07-15 | 1999-07-15 | Multichip module connection structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20183599A JP2001036309A (en) | 1999-07-15 | 1999-07-15 | Multichip module connection structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001036309A true JP2001036309A (en) | 2001-02-09 |
Family
ID=16447694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20183599A Pending JP2001036309A (en) | 1999-07-15 | 1999-07-15 | Multichip module connection structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001036309A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2378045A (en) * | 2001-07-25 | 2003-01-29 | Marconi Caswell Ltd | Electrical connection with flexible coplanar transmission line |
US6807063B2 (en) | 2002-03-14 | 2004-10-19 | Fujitsu Limited | High-frequency integrated circuit module |
JP2005123894A (en) * | 2003-10-16 | 2005-05-12 | Matsushita Electric Works Ltd | High frequency multichip module board |
KR100779168B1 (en) | 2006-12-07 | 2007-11-26 | 한국전자통신연구원 | Signal transmission line for millimeter wave band |
JP2010161416A (en) * | 2010-04-07 | 2010-07-22 | Hitachi Ltd | Electronic device |
WO2012027081A3 (en) * | 2010-08-25 | 2012-04-19 | Oracle International Corporation | Optical communication in a ramp-stack chip package |
US8283766B2 (en) | 2010-09-02 | 2012-10-09 | Oracle America, Inc | Ramp-stack chip package with static bends |
US8373280B2 (en) | 2010-09-01 | 2013-02-12 | Oracle America, Inc. | Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component |
EP2805427A1 (en) * | 2012-01-18 | 2014-11-26 | Tyco Electronics Corporation | Waveguide structure for a contactless connector |
US9082632B2 (en) | 2012-05-10 | 2015-07-14 | Oracle International Corporation | Ramp-stack chip package with variable chip spacing |
-
1999
- 1999-07-15 JP JP20183599A patent/JP2001036309A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2378045A (en) * | 2001-07-25 | 2003-01-29 | Marconi Caswell Ltd | Electrical connection with flexible coplanar transmission line |
US6807063B2 (en) | 2002-03-14 | 2004-10-19 | Fujitsu Limited | High-frequency integrated circuit module |
JP2005123894A (en) * | 2003-10-16 | 2005-05-12 | Matsushita Electric Works Ltd | High frequency multichip module board |
KR100779168B1 (en) | 2006-12-07 | 2007-11-26 | 한국전자통신연구원 | Signal transmission line for millimeter wave band |
US7626473B2 (en) | 2006-12-07 | 2009-12-01 | Electronics And Telecommunications Research Institute | Signal transmission line for millimeter-wave band |
JP2010161416A (en) * | 2010-04-07 | 2010-07-22 | Hitachi Ltd | Electronic device |
WO2012027081A3 (en) * | 2010-08-25 | 2012-04-19 | Oracle International Corporation | Optical communication in a ramp-stack chip package |
US8290319B2 (en) | 2010-08-25 | 2012-10-16 | Oracle America, Inc. | Optical communication in a ramp-stack chip package |
US8373280B2 (en) | 2010-09-01 | 2013-02-12 | Oracle America, Inc. | Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component |
US8283766B2 (en) | 2010-09-02 | 2012-10-09 | Oracle America, Inc | Ramp-stack chip package with static bends |
EP2805427A1 (en) * | 2012-01-18 | 2014-11-26 | Tyco Electronics Corporation | Waveguide structure for a contactless connector |
US9082632B2 (en) | 2012-05-10 | 2015-07-14 | Oracle International Corporation | Ramp-stack chip package with variable chip spacing |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6847100B2 (en) | High speed IC package configuration | |
US4949224A (en) | Structure for mounting a semiconductor device | |
US20030060172A1 (en) | Radio frequency module | |
US20020125553A1 (en) | Method of packaging a device with a lead frame, and an apparatus formed therefrom | |
JPH08213474A (en) | Integrated circuit and manufacture | |
US8436450B2 (en) | Differential internally matched wire-bond interface | |
JP2001036309A (en) | Multichip module connection structure | |
JPH0629428A (en) | Semiconductor device | |
CA1301949C (en) | Device for interconnection and protection of a bare microwave componentchip | |
US6884656B2 (en) | Semiconductor device having a flip-chip construction | |
JP2004022667A (en) | Semiconductor modular structure | |
JP2002009193A (en) | Semiconductor device | |
JPH11330298A (en) | Package provided with signal terminal and electronic device using the package | |
JP3489926B2 (en) | High frequency circuit device | |
JPH0936617A (en) | High frequency module | |
US7105924B2 (en) | Integrated circuit housing | |
JP3048992B2 (en) | MMIC module | |
JP4127589B2 (en) | High frequency semiconductor device package and high frequency semiconductor device | |
JPS6271301A (en) | Microwave integrated circuit device | |
JP3181036B2 (en) | Mounting structure of high frequency package | |
JP3112253B2 (en) | High frequency semiconductor device | |
JP2666156B2 (en) | Film carrier for high frequency IC | |
JP2001267487A (en) | High frequency module | |
JP2791301B2 (en) | Microwave integrated circuit and microwave circuit device | |
JP3145670B2 (en) | Mounting structure of high frequency semiconductor package |